9/20/6 Lecture 2 - Prog Model 1

MicroBabyA simple micro-controller

encompassing all the basics

Start this class by organizing into groups.

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Lecture Overview What is MicroBaby The architecture Addressing modes Instructions Internal registers and control signals

What is MicroBaby? Micro-Baby is a simple computer

architecture, in fact, very simple. All microcontrollers and microprocessors are

computer architectures, in most cases fairly simple ones.

In today’s world even microcontrollers are eons beyond basic.

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Basic assumptions It is assumed that the reader possesses a basic

understanding of the binary number system and the implementation of logic equations in digital logic using AND, OR, NAND, NOR, XOR and NOT gates.

It is also assumed that the reader also has a somewhat beyond basic understanding of computer architecture.

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Basic styles of architecture Micro-Baby is a accumulator based load-store

architecture. It embodies the essence of the principles of a

RISC architecture. All instruction execution results are left in the

accumulator. The accumulator based load-store architecture is

the base processor architecture that all other architectures build upon

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MicroBaby internal structure High level and high level internal structure

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InputDevice

OutputDevice

Memory Unit

Central Processing Unit

Control Unit

Arithmetic/LogicUnit

Accumulator

Controller

CPU

ACC

Instruction Memory

Data Memory

256 bytes

256 bytes

256 bytes

FF Reset Vector

000000xx I/O addresses

PC

ALU

Memory Data Bus

Memory Address Bus

Instr Reg

8

8

8

SR

MemoryLoader

On startup

The memory modules Interface to the memory modules

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MemoryRAM

Data8

8Address

r/w

ce

The ALU Version 1 of the alu

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LogicUnit

Lout

A B

F(3 dt 0)Add/Sub

CoutCin

A B

Sum

MuxAddSub

MuxArlo

Cin

AddSub

Cin’

CselCsel(1 dt 0)

8

8

8

8

8

8 8

8

00 – Cin01 – NOT Cin10 – ‘0’11 – ‘1’

1 = B0 = B’

1 = Sum0 = Lout

All 0’s

N

Z

mbALU

The datapath The datapath showing the internal data bus

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ALU

Accumulator

Cout

Ldac

NZ

F(3 dt 0)AddSubCinArlo

Data Bus

MuxAalMuxBbu

Bus

Dr

DrAcc

alures

accout

amuxtoacc

bmuxout

zero

Csel

Aal 1 = alures 0 = Dbus

Bbu 1 = zero 0 = Dbus

F function AND 1000 OR 1110 INV 0011 XOR 0110

The controller Version 2 of the conroller

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Program Counter

PCsel

incrementer

Fixval

PC

Controller

PC unit

Instr Reg

SR

AalBbu

LdaccDracc

AddSubArloCsel

F(3 dt 0)

CinNZ

Rst

The instructions The instruction

set Offers the

basics Would like to

have logical shift instruction

Maybe rotate9/20/6 Lecture 2 - Prog Model 11

I NSTR Op Code 2nd by Addr mode dpcsvec ecsvec/e2csvec LDA 1000 0010 Addr Direct 00000000 01001 / 01000 LDA 1000 0001 Arg Immediate 01100000 00101 STA 1010 0010 Addr Direct ADD 0100 0010 Addr Direct ADD 0100 0001 Arg Immediate ADDC 0100 1010 Addr Direct ADDC 0100 1001 Arg Immediate SUB 0101 0010 Addr Direct SUB 0101 0001 Arg Immeddiate SUBC 0111 0010 Addr Direct SUBC 0111 0001 Arg Immeddiate INC 0100 1100 Na Inherent DEC 0100 0100 NA Inherent AND 0101 1010 Addr Direct AND 0101 1001 Arg Immeddiate OR 0101 1110 Addr Direct OR 0101 1101 Arg Immeddiate INV 0101 1000 Na Inherent XOR 0101 0110 Addr Direct XOR 0101 0101 Arg Immeddiate CLRA 0100 1111 Na Inherent CLRC 0100 0000 Na Inherent CSET 0100 1000 Na Inherent CMP 0100 1010 Addr Direct CMP 0100 1001 Arg Immeddiate JMP 11cn zuuu Addr Direct

Debugging the controller The controller encoding in the microcode

needs debugging to insure correctness. Note the multiple control signals need to

allow the architecture to function. Friday will be simulation demonstration and

general discussion of microbaby and what it teaches. Along with discussion of MU0

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General note on this class The only way the format of the class works is

if the students participate. After presentations a discussion will be lead

to fill in the blanks from the presentations. Attendance will be taken and will be

incorporated into the grade.

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Topics of talks Friday – continue with microbaby Wednesday – Chapter 1 of text – setting the

tone. Topic for beyond Friday will be shown

Friday.

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Topics for presentation next week Next Wednesday Jan 21st Group 1 – Chapter 1 of text

Processor architecture and organization Hardware Design Abstraction MU0 – a simple processor

Group 2 – Chapter 1 of text Processor design tradeoffs RISC – organization – advantages – drawbacks Design for low power

Discussion – compare and contrast MU0 to microbaby9/20/6 Lecture 2 - Prog Model 15

Future topics The Acorn RISC – history of deployment,

more details on company development and interaction with Apple, VLSI Technology. This led to Acorn RISC Machines, Ltd. which became ARM.

Architectural inheritenance from the Berkeley RISC I and II. Details of the Berkeley RISC and its history

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Future topics The ARM programmer’s model – what the

programmer sees. (2 presentations) - This includes what is in the datapath and the structure of memory and I/O seen. Tools for assembler language programming.

It would be nice to have a “free” simulation tool for ARM about now. ARM Sim from the University of Victoria may be the one we use.

Free textbook is available online Also, wikipedia is a great source for information.

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