8085 Presentation FINAL

Rohan A. Borgalli.M.Tech (Digital Systems)

MNNIT Allahabad

Presentation Objectives Define microprocessor.

Provide a history of microprocessors.

Introduce you to microprocessor.

Detail Description & Working of one among the most

popular microprocessor family, The MPU-8085.

Introduction of Peripheral units.

Enlist some of programs & its simulation using Simulator.

Applications of microprocessor.

Comparison of Microprocessor and Microcontroller

MicroprocessorThe microprocessor is a programmable

device that takes in numbers, performs arithmetic or logical operations on them according to the program stored in memory and then produces other numbers as a result.

A Central processing unit (CPU) in a computer system or handheld device consists of one or more microprocessors.

History of MicroprocessorThe very first microprocessor is considered to

be the Intel 4004. It was released in 1971 and was a 4 Bit processor.

Then the 8 bit 8008 microprocessor. It was developed by Intel in 1972

The first multi-chip 16 bit processor was released by National Semiconductor in 1973

Intel upgraded the 8008 into a 16 bit version they called the 8086. It was the first of the x86 family by which many modern PCs are powered.

32 bit designs didn't require much to improve performance since it has double the size of instructions as well as the amount of addressable memory.

68000 by Motorola was one of the first microprocessors developed to 32 bit architectures. It was released in 1979 and continued to be in use today.

Most of today's computers are turning to 64 bit designs to handle dealing with very large amounts of data. This is needed especially as demand for 3D Graphics and fast video has risen. E.g. AMD Athlon, Pentium i5/i7 processors.

Classifications of microprocessorsMicroprocessors are classified into different types on the basis

of the bit of operation. Based on bit of operation at a time, the following are the types of microprocessors:

==> 4 bit. e.g. Intel 4004==> 8 bit. e.g. Intel 8085, 8088, Zilog Z80, Z180==> 16 bit. e.g. Intel 8086, 80186, 80286, 80386, ==> 32 bit. e.g. Intel Pentium, Celeron, AMD Sempron==> 64 bit. e.g. AMD Athlon.

Based on the instruction set microprocessors are classified into:

RISC — Reduced Instruction Set Computing. These types of processors are commonly used in ovens, air conditioners, etc.

CISC — Complex Instruction Set Computing. The types of processors are used in desktops, laptops and servers.

Registers

Registers

Block diagram of microprocessor

InstructionCache

Arithmetic& Logic

Unit

ControlUnitBus

InterfaceUnit

DataCache

InstructionDecoder

I/O

RAM

MemoryBus

SystemBus

FloatingPointUnit

The 8085 MicroprocessorThe 8085 microprocessor was introduced by

Intel in the year 1976. This microprocessor is an update of 8080

microprocessor. The 8080 processor was updated with Enable/Disable instruction pins and Interrupt pins to form the 8085 microprocessor.

It is an 8-bit microprocessor with a 40 pin dual in line package

Intel 8085 Pin Intel 8085 Pin

ConfigurationConfiguration

8085 Microprocessor Signals and I/O Pins

Architecture of 8085 Microprocessor

8085 Microprocessor Registers

Flag RegisterFlag Register is given by:

S:Sign flag is set when result of an operation is negative.

Z:Zero flag is set when result of an operation is 0.Ac:Auxiliary carry flag is set when there is a carry out

of lower nibble or lower four bits of the operation.CY:Carry flag is set when there is carry generated by

an operation.P:Parity flag is set when result contains even number

of 1’s.Rest are don’t care flip flops.

SS ZZ XX ACAC XX PP XX CYCY

The 8085 and Its BusesThe 8085 Buses can be grouped into 3 groups:Address Bus.Data Bus.Control Bus.

Different units and bus systems stay connected:

A15-A8

LatchAD7-AD0

D7- D0

A7- A0

8085

ALE

IO/MRDWR

1K ByteMemory

Chip

WRRD

CS

A9- A0

A15- A10Chip Selection

Circuit

TIMING AND STATE DIAGRAM The µP operates with reference to clock

signal. The rise and fall of the pulse of the clock gives one clock cycle.

Each clock cycle is called a T state and a collection of several T states gives a machine cycle.

Important machine cycles are :1. Op-code fetch.2. Memory read.3. Memory write. 4. I/Op-read.5. I/O write.

MPU Communication and Bus TimingMPU Communication and Bus Timing

18 8085 timing diagram for Opcode fetch cycle for MOV C, A .

8085 Memory InterfacingThere needs to be a lot of interaction

between the microprocessor and the memory for the exchange of information during program execution.Memory has its requirements on control

signals and their timing.The microprocessor has its requirements

as well.The interfacing operation is simply the

matching of these requirements.

Memory structure & its requirements

The way of interfacing the above two chips to the microprocessor is the same. However, the ROM does not have a WR signal.

AddressLines

DateLines

CS

RDOutput Buffer

ROM

AddressLines

Data Lines

CS

RDOutput Buffer

RAM

WRInput Buffer

Data Lines

Cont…Example: Interface 2Kbytes of Memory to 8085

with starting address 8000H.Initially we realize that 2K memory requires 11

address lines(2^11=2048). So we use A0-A10 .Write down A15 –A0

AA15151414 1313 1212 1111 1010 99 88 77 66 55 44 33 22 11 00

11

11

00

00

00

00

00

00

00

00

00

11

00

11

00

11

00

11

00

11

00

11

00

11

00

11

00

11

00

11

00

11

ADDADD

8000H8000H

87FFH87FFH

Chip Selection Example

22

CS

RD WR

A0

A1

CS

RD WR

A0

A1

CS

RD WR

A0

A1

CS

RD WR

A0

A1

2 X4

DecoderA3

A2

A1

A0

RD

WR

D1

D0

The 8085 Machine LanguageThe 8085 (from Intel) is an 8-bit

microprocessor. The 8085 uses a total of 246 bit patterns to form its instruction set.These 246 patterns represent only 74 instructions. The reason for the difference is that some (actually

most) instructions have multiple different formats.Because it is very difficult to enter the bit patterns

correctly, they are usually entered in hexadecimal instead of binary.

For example, the combination 0011 1100 which translates into “increment the number in the register called the accumulator”, is usually entered as 3C.

Assembly Language

Entering the instructions using hexadecimal is quite easier than entering the binary combinations. However, it still is difficult to understand what a program written in hexadecimal does.

So, each company defines a symbolic code for the instructions.

These codes are called “mnemonics”.The mnemonic for each instruction is usually

a group of letters that suggest the operation performed.

8085 Instruction Set Data transfer operations

1.Between registers 2.Between memory location and a register 3.Direct write to a register / memory 4.Between I/O device and accumulator

Arithmetic operations (ADD, SUB, INR, DCR)

Logic operations (AND,OR,RRC,RLC) Branching operations (JMP, CALL, RET)

Data Transfer Instruction for 8085 Microprocessor

Arithmetic & logical Instruction for 8085 Microprocessor

Branching Instruction for 8085 Microprocessor

Writing Assembly Language Program Define the problem clearly and make the

problem statement. Analyze the problem thoroughly. In this

step we divide the problem into smaller steps to examine the process of writing programs.

Draw the flow chart. The steps listed in the problem analysis and the sequences are represented in a block diagram.

Translate the blocks shown in the flowchart into 8085 operations and then subsequently into mnemonics.

Conversion and ExecutionConvert the mnemonics into Hex code; we

need to look up the code in 8085 instruction set.

Store the program in Read/Write memory of a single-board microcomputer. This may require the knowledge about memory addresses and the output port addresses.

Finally execute the program.

Flow Chart for Programming Start

Initialisation Section

Processing Section

Loop Control Section

Is task Over?

Concluding Section

Stop

Yes

No

Counters A loop counter is set up by loading a register

with a certain value Then using the DCR (to decrement) and INR

(to increment) the contents of the register are updated.

A loop is set up with a conditional jump instruction that loops back or not depending on whether the count has reached the termination count.

8-BIT ADDITION & SUBTRACTIONProgram:MVI A, 04HMVI B, 06HMVI C, 00HADD BJNC LP1INR CLP1: STA 4500HMOV A, CSTA 4501HHLT

Program:MVI A, 06HMVI B, 04HMVI C, 00HSUB BJNC LP1INR CLP1: STA 4500HMOV A, CSTA 4501HHLT

8 BIT MULTIPLICATIONMVI A, 00 HMVI B, 05 HMVI D, 04 HMVI C, 00 HUp: ADD BJNC downINR CDown: DCR DJNZ UpSTA 9000 HMOV A, CSTA 9001 HHLT

8 BIT DIVISIONMVIA, 04 HMVIB, 02 HMVIC, 00 HUp : SUB BINR CJNC UpADD BDCR CSTA 9000 HMOV A, CSTA 9001 HHLT

Time DelaysCalculation of Delay using 8 bit counter:

Consider following example: MVI C, count(8 bit) H 7 T

stateUP: DCR C 4 T

states JNZ UP

10/7 T RET 10THere loop UP is executed (N-1) times.

Cont…Thus delay is Td=M+[(count)x N) -3.Where M= no.of T states outside loop. N=no.of T states inside loop.Here value of M= 17, N= 14.The maximum delay will occur if count is 255 or

FF H.Thus Td max =17+[255x14]-3= 3584 T states.For 0.33 µsec delay for a T state, we get Td max=0.33 µsec x 3584= 1180 µsec or 1.18 m

sec.

INTERRUPTS IN 8085In many real-time operations, the microprocessor

should be able to receive an external asynchronous signal (interrupt) while it is running a routine.

It has two types: 1.Software Interrupts 2.Hardware InterruptsWhen the interrupt signal arrives:

The processor will break its routine Go to a different routine (service routine)Complete the service routineGo back to the “regular” routine

Software interrupts The 8085 recognizes 8 RESTART

instructions: RST0 - RST7 . Each of these would send the execution to a predetermined hard-wired memory location:

Restart Restart InstructionInstruction

Equivalent toEquivalent to

RST0RST0 CALL 0000HCALL 0000H








Hardware interruptThe 8085 has 5 Hardware interrupt.The INTR input. The INTR input is the

only non-vectored interrupt.INTR is maskable using the EI/DI

instruction pair.RST 5.5, RST 6.5, RST 7.5 are all

automatically vectored.RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-maskable interrupt in the 8085

TRAP is also automatically vectored

INTERRUPT PRIORITY & VECTOR

Interrupt Instructions

EI ( Enable Interrupt) This instruction sets the interrupt enable Flip Flop to activate the interrupts.

DI ( Disable Interrupt)This instruction resets the interrupt enable Flip Flop and deactivates all the interrupts except the non-maskable interrupt i.e. TRAP

RESET This also resets the interrupt enable Flip Flop.

SIM INSTRUCTION

44

SO

DS

DE

XX

XR

7.5

MS

EM

7.5

M6.

5M

5.5

01234567

RST5.5 Mask

RST6.5 MaskRST7.5 Mask

} 0 - Available1 - Masked

Mask Set Enable0 - Ignore bits 0-21 - Set the masks according to bits 0-2

Force RST7.5 Flip Flop to resetNot Used

Enable Serial Data0 - Ignore bit 71 - Send bit 7 to SOD pin

Serial Out Data

•SIM Instruction helps activate a particular interrupt.

•It can also mask a maskable interrupt.

RIM INSTRUCTION

Serial Data In

RST5.5 Interrupt Pending

RST6.5 Interrupt PendingRST7.5 Interrupt Pending

0 - Available1 - Masked

Interrupt EnableValue of the Interrupt EnableFlip Flop

SD

IP

7.5

P6.

5P

5.5

IEM

7.5

M6.

5M

5.5

01234567

RST5.5 Mask

RST6.5 MaskRST7.5 Mask

}

•Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending.

•Using the RIM instruction, it is possible to can read the status of the interrupt lines and find if there are any pending interrupts.

Internal Structure of Interrupts

Hardware Generation of RST Opcode

The following is an example of generating RST 5:RST 5’s opcode is EF= D7D6D5D4D3D2D1D0

1 1 1 0 1 1 1 1

Multiple interrupts and priority

Serial Transmission & Reception

Transmission Reception

The 8259A programmable Interrupt Controller• The 8259A is a programmable interrupt controller

designed to work with Intel microprocessors 8085, 8086, and 8088. It can

1. manage eight interrupt according to the instructions written into its control registers. This is equivalent to providing eight interrupt pins on the processor in place of one INTR (8085) pin.

2. vector an interrupt request anywhere in the memory map.

3. Resolve eight levels of interrupt priorities in a variety of modes, such as fully nested mode, automatic rotation mode, and specific rotation mode

4. Mask each interrupt request individually. 5. Read the status of pending interrupts, in-service

interrupts, and masked interrupts.6. Be expanded to 64 priority levels by cascading

additional 8259As.

INTERFACING 8085 & 8259

The 8279 Programmable Keyboard/Display Interface

The 8279 is a hardware approach to interfacing a matrix keyboard and a multiplexed display.

The 8279 is a 40-pin device with two major segments: keyboard and display. The keyboard segment can be connected to a 64-contact key matrix. Keyboard entries are debounced and stored in the internal FIFO (First-In-First-Out) memory; an interrupt signal is generated with each entry.

The display segment can provide a 16-character scanned display interface with such devices as LEDs. This segment has 16x8 R/W memory (RAM), which can be used to read/write information for display purposes. The display can be set up in either right-entry or left entry format.

Block Diagram of 8279

Keyboard/Display Interfacing using the 8279

Introduction to 82C55The 82C55 is a popular interfacing component,

that can interface any TTL-compatible I/O device to a microprocessor.

It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated chipset).

Requires insertion of wait states if used with a microprocessor using higher that an 8 MHz clock.

PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct modes of operation.

8255 PIN DIAGRAMPA0-PA7PA0-PA7 I/OI/O Port A PinsPort A Pins

PB0-PB7PB0-PB7 I/OI/O Port B PinsPort B Pins

PC0-PC7PC0-PC7 I/O I/O Port C PinsPort C Pins

D0-D7D0-D7 I/OI/O Data PinsData Pins

RESETRESET II Reset pinReset pin

RDRD¯̄ II Read inputRead input

WR WR ¯̄ II Write inputWrite input

A0-A1A0-A1 II Address pinsAddress pins

CS CS ¯̄ II Chip selectChip select

Vcc , GndVcc , Gnd II +5volt supply+5volt supply

8255 MODESMode 0 : Simple I/O

• Any of A, B, CL and CH can be programmed as input or output

Mode 1: I/O with Handshake• A and B can be used for I/O• C provides the handshake signals

Mode 2: Bi-directional with handshake• A is bi-directional with C providing handshake

signals• B is simple I/O (mode-0) or handshake I/O (mode-1)

BSR (Bit Set Reset) Mode• Only C is available for bit mode access.• Allows single bit manipulation for control

applications

INTERFACING 8085 & 8255

82558085 3:8 decoder

74373

(AD0-AD7)

D7-D0

A0-A7

/CS

A0A1

O0O1

O7

A13A12A11

ALE

RD ¯WR ¯

RD¯WR¯

G2A G2B G1

A15

A14

IO/M

A

B

C PA

PB

PC

Program for initialize 8255Example:Take data from 8255 port B.Add FF

H .Output result to port A.MVI A,82H Initialize 8255.OUT 20H IN 22H Take data from port B ADI FFH Add FF H to dataOUT 21H. OUT Result to port A. RST1. STOP.

Direct Memory Access (DMA)Direct Memory Access (DMA)DMA is an IO technique where external IO

device requests the use of the MPU buses.Allows external IO devices to gain high

speed access to the memory.Example of IO devices that use DMA: disk

memory system. HOLD and HLDA are used for DMA. If HOLD=1, 8085 will place it address, data

and control pins at their high-impedance.A DMA acknowledgement is signaled by

HLDA=1.

62

I/O Data Transfer

11-63

DMA controller details

8253 FeaturesIt is Programmable interval Timer(PIT).Three independent 16 bit counters.24 pin Dual in line Package.Counting facility in Both BCD and Binary modes.Dc to 2 MHz operating Frequency.Can be used as a clock generator.

Block Diagram 8253 PIT

CONTROL WORD SC1SC1 SC0SC0 RL1RL1 RL0RL0 M2M2 M1M1 M0M0 BCDBCD

D0D7

00 00 Counter0Counter0



11 11 ILLEGALILLEGAL

SC1 SC0 Select counter

00 00 Counter latchingCounter latching

00 11 Read/load LSBRead/load LSB

1 1 00 Read/load MSBRead/load MSB

11 11 R/L MSB 1R/L MSB 1stst then LSB.then LSB.

RL1 RL0 Read/Load

Cont…

00 00 00 Mode 0Mode 0

00 00 11 Mode 1Mode 1

X X 11 00 Mode 2Mode 2

XX 11 11 Mode 3Mode 3

11 00 00 Mode 4Mode 4

11 00 11 Mode 5Mode 5

M2 M1 M0

BCD =0 Binary counter

BCD =1 BCD counter

Program of 8253 SQUARE WAVEExample: Use 8253 as a square wave generator

with 1ms period if the input frequency is 1MHz.We use counter 0 as a square wave generator

and address of counter 0 =10H and control register =13H.

I/P frequency is 1MHz.So time is 1µsec.Count value = Required period /Input period =

1ms/1 µsec=1000(Decimal).Thus we use 8253 as a decimal counter.

Cont…Program: MVI A,37H Initialize counter 0 mode 3 OUT 13H 16 bit count BCD MVI A,00H Load LSB count to counter

0 OUT 10H MVI A,10H Load MSB count to

counter 0 OUT 10H. Thus, the output will be a square wave.

INTERFACING ADC with 8255

Interfacing LED’s with 8255

INTERFACING STEPPER MOTOR with 8255

8085 Simulation Trainer kit

8085 Dynalog Trainer Kit

8259(PIC) Trainer Kit

8279 Trainer Kit

Elevator Simulator kit

8253 Trainer Kit

Thumbwheel Kit

DAC Kit

Traffic Controller Kit

ADC kit

Real life applications of microprocessorMicroprocessors are used to handle a set of tasks that

control one or more external events or systems. Microprocessors are typically used in either reactive or

embedded systems. Reactive systems are those that have an ongoing

interaction with their environment - for example, a fire-control system that constantly reacts to buttons pressed by a pilot.

Embedded systems are those used to control specialized hardware in which the computer system is installed - for example, the microprocessor system used to control the fuel/air mixture in the carburetor of many automobiles. In embedded systems the software system is completely

encapsulated by the hardware that it controls.

Microprocessor Vs. MicrocontrollerComponents of a microprocessor/controller

CPU: Central Processing UnitI/O: Input /OutputBus: Address bus & Data busMemory: RAM & ROMTimerInterruptSerial PortParallel Port

General-purpose microprocessorCPU for ComputersCommonly no RAM, ROM, I/O on CPU chip

itself

85

CPU

General-Purpose Micro-processor

RAM ROM I/O Port

TimerSerial COM Port

Data Bus

Address Bus

Microcontroller :A single-chip computerOn-chip RAM, ROM, I/O ports...Example ： Motorola’s 6811, Intel’s 8051,

Zilog’s Z8 and PIC 16X

86

RAM ROM

I/O Port

TimerSerial COM Port

CPU

A single chip

Microcontroller

Microprocessor vs. MicrocontrollerMicroprocessor CPU is stand-alone,

RAM, ROM, I/O, timer are separate

designer can decide on the amount of ROM, RAM and I/O ports.

Expensivegeneral-purposeHigh processing powerHigh power

consumptionInstruction sets focus

on processing-intensive operations

Typically 32/64 – bit87

Microcontroller

• CPU, RAM, ROM, I/O and timer are all on a single chip

• fixed amount of on-chip ROM, RAM, I/O ports

• for applications in which cost, power and space are critical

• single-purpose (control-oriented)

• Low processing power

• Low power consumption

• Instruction sets focus on control and bit-level operations

• Typically 8/16 bit

Program for ADC

MVI A, 91HOUT CR

BEGIN: CALL CONVERSATION

CPI 41HJC NEXTMVI A, 0EHOUT PCJMP BEGIN

NEXT: MVI A, 0FH

OUT PCJMP BEGIN

Conversion Subroutine:CONVERSION:

MVI A,00HOUT PB ; Send address to

select IN0MVI A,08H ;Latch address by giving ALE

HighOUT PB

BACK: MVI A,18H

OUT PB ; Make SOC HighMVI A,08HOUT PB ; Make SOC LowMVI A,00HOUT PB ; Make ALE Low

LOOP: IN PC

ANI 01HJZ LOOP ; Wait for EOCIN PARET ; Return value and store

Accumulator

Program for Elevator SimulatorLXI H, C090 ; Load message in HLCall 1844 ; Call Display SubroutineMVI A, 82 ; Display Port A in O/P mode &OUT 13 Port B in I/P modeMVI B, 00 ; B Stores Present status value of

liftUP: MVI A, 00 ; A Stores Input value for lift

OUT 10 MVI A, F0 ; LED S4 on (GND Floor)

OUT 10MOV A, BOUT 10

Cont…NXT: IN 11 ; Check for floor request

ANI 0FJZ NXTRRCJC GND ; On LED S4 (GND)RRCJC FIRST ; Goto 1st Floor routineRRCJC SECOND ; Goto 2nd Floor routineRRCJC THIRD ; Goto 3rd Floor routine

Cont…GND: MVI C, F0 ; C Stores PermanentCALL DOWN status value of liftJMP UPFIRST: MVI C, F3

CALL DOWNJMP UP

SECOND: MVI C, F6CALL DOWNJMP UP

THIRD: MVI C, F9CALL DOWNJMP UP

Cont…DOWN: MOV A, B

CMP CJZ DNJC DN1

ORI F0UP1: OUT 10 ; Lift going down

DCR AMOV B, ALXI D, FFFFCALL 05F1 ; Delay SubroutineMOV A, BCMP CJNZ UP1

RET

Cont…DN1: ORI F0 ; Lift Going upUP2: OUT 10INR AMOV B, A

LXI D, FFFFCALL 05F1 ; Delay Subroutine

MOV A, BCMP CJNZ UP2

DN: RET

Program for Traffic Light ControllerMVI A, 70 ; Move immediate data into ACC. To make RED & left GREEN

ON.OUT 20 ; initially give RED & left GREEN onOUT 28 all portsOUT 30OUT 38REDO: MVI A, B0 ; Make YELLOW & left GREEN

on port 1 for slow traffic.OUT 20CALL DLYSMALL; Small delay subroutine

Cont…MVI A, C0 ; All GREENS on for port 1OUT 20CALL DLYBIG ; Big delay subroutineMVI A, B0 ; Make YELLOW & left GREEN onOUT 20 port 1 for slow traffic.CALL DLYSMALL; Small delay subroutineMVI A, 70 ; Move immediate data into ACC.

toOUT 20 make RED & left GREEN ON.CALL DLYSMALL; Small delay subroutine

Cont…MVI A, B0 ; Make YELLOW & left GREEN onOUT 28 port 2 for slow traffic.CALL DLYSMALL ; Small delay subroutineMVI A, C0 ; All GREENS on for port 2OUT 28CALL DLYBIG ; Big delay subroutineMVI A, B0 ; Make YELLOW & left GREEN onOUT 28 port 2 for slow traffic.CALL DLYSMALL ; Small delay subroutineMVI A, 70 ; Move immediate data into ACC.

toOUT 28 make RED & left GREEN ON.CALL DLYSMALL ; Small delay subroutine

Cont…MVI A, B0 ; Make YELLOW & left GREEN on port

3 forOUT 30 slow traffic.CALL DLYSMALL ; Small delay subroutineMVI A, C0 ; All GREENS on for port 1OUT 30CALL DLYBIG ; Big delay subroutineMVI A, B0 ; Make YELLOW & left GREEN on port

3 forOUT 30 slow traffic.CALL DLYSMALL ; Small delay subroutineMVI A, 70 ; Move immediate data into ACC. to

makeOUT 30 RED & left GREEN ON.CALL DLYSMALL ; Small delay subroutine

Cont…MVI A, B0 ; Make YELLOW & left GREEN on port 4

forOUT 38 slow traffic.CALL DLYSMALL ; Small delay subroutineMVI A, C0 ; All GREENS on for port 4OUT 38CALL DLYBIG ; Big delay subroutineMVI A, B0 ; Make YELLOW & left GREEN on port 4

forOUT 38 slow traffic.CALL DLYSMALL ; Small delay subroutineMVI A, 70 ; Move immediate data into ACC. to makeOUT 38 RED & left GREEN ON.CALL DLYSMALL ; Small delay subroutineJMP REDO

ReferenceDouglas Hall, Microprocessors and

Interfacing, New York, McGraw Hill 1986.

Ramesh Gaonkar, Microprocessor Architecture, Programming and Application with 8085.

Sim8085 Version 2.2 Microprocessor Simulator

8085 Presentation FINAL

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