8-Bit Kogge Stone Adder Ppt
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Transcript of 8-Bit Kogge Stone Adder Ppt
![Page 1: 8-Bit Kogge Stone Adder Ppt](https://reader036.fdocuments.in/reader036/viewer/2022082214/55cf97c1550346d033936c17/html5/thumbnails/1.jpg)
8‐bit Kogge Stone Adder
EE619 Course ProjectEE619 Course Project
Ashish Bhatia (Y5827121)Anurag Sindhu(Y5106)g ( )
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Kogge Stone Adder(KSA)Kogge Stone Adder(KSA)
• Most popular carry look ahead adderMost popular carry look ahead adder
• Fastest adder design
C i f i d• Fast Computation at cost of increased area
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TheoryTheory
• Pre processingPre processing– Generate (pi, gi) from (Ai, Bi)
p = A xor B– pi = Ai xor Bi– gi = Ai and Bi
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TheoryTheory
• Carry look ahead networkCarry look ahead network – Generate (Pij, Gij) from (Gi, Pi) and (Gj, Pj)
P = P and P– Pi:j = Pi:k+1 and Pk:j– Gi:j = Gi:k+1 or (Pi:k+1 andGk:j )
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TheoryTheory
• Post processingPost processing– Sumi = pi xor Carryi‐1C = G or (C and P )– Ci = Gi:0 or (Cin and Pi:0)
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Ill iIllustration
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B3=1 A3=1 B2=1 A2=0 B1=0 A1=1 B0=0 A0=1 Cin=0
g3=1 p3=0 g2=0 p2=1 g1=0 p1=1 g0=0 p0=1g3 p3 g2 p2 g1 p1 g0 p0
Pre processingPre processing– pi = Ai xor Bi
d– gi = Ai and Bi
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B3=1 A3=1 B2=1 A2=0 B1=0 A1=1 B0=0 A0=1 Cin=0
g3=1 p3=0 g2=0 p2=1 g1=0 p1=1 g0=0 p0=1g3 p3 g2 p2 g1 p1 g0 p0
G3:2=1 P3:2 =0
G2:1=0 P2:1 =1
G1:0=0 P1:0 =1
G0=C0 =0
Carry look ahead networkCarry look ahead network – Pi:j = Pi:k+1 and Pk:j– G = G or (P andG )– Gi:j = Gi:k+1 or (Pi:k+1 andGk:j )
– Ci = Gi:0 or (Cin and Pi:0)
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B3=1 A3=1 B2=1 A2=0 B1=0 A1=1 B0=0 A0=1 Cin=0
g3=1 p3=0 g2=0 p2=1 g1=0 p1=1 g0=0 p0=1g3 p3 g2 p2 g1 p1 g0 p0
G3:2=1 P3:2 =0
G2:1=0 P2:1 =1
G1:0=0 P1:0 =1
G0=C0 =0
G3:0=1 P3:0 =0
G1 = C1 =0G2 = C2 =0
3:0
Carry look ahead networkCarry look ahead network – Pi:j = Pi:k+1 and Pk:j– G = G or (P andG )– Gi:j = Gi:k+1 or (Pi:k+1 andGk:j )
– Ci = Gi:0 or (Cin and Pi:0)
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B3=1 A3=1 B2=1 A2=0 B1=0 A1=1 B0=0 A0=1 Cin=0
g3=1 p3=0 g2=0 p2=1 g1=0 p1=1 g0=0 p0=1g3 p3 g2 p2 g1 p1 g0 p0
G3:2=1 P3:2 =0
G2:1=0 P2:1 =1
G1:0=0 P1:0 =1
G0=C0 =0
G3:0=1 P3:0 =0
G1 = C1 =0G2 = C2 =0
3:0
G3 = C3 =1 Carry look ahead networkCarry look ahead network – Pi:j = Pi:k+1 and Pk:j– G = G or (P andG )– Gi:j = Gi:k+1 or (Pi:k+1 andGk:j )
– Ci = Gi:0 or (Cin and Pi:0)
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Cin=0
p3=0 p2=1 p1=1 p0=1
• Post processing
p3 p2 p1 p0
G0=C0 =0– Si = pi xor Ci‐1
G1 = C1 =0G2 = C2 =0
G3 = C3 =1
S0= 1S1= 1S2= 1S3= 0Cout = 1 0123out
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B3=1 A3=1 B2=1 A2=0 B1=0 A1=1 B0=0 A0=1 Cin=0
g3=1 p3=0 g2=0 p2=1 g1=0 p1=1 g0=0 p0=1g3 p3 g2 p2 g1 p1 g0 p0
A = 1011
G3:2=1 P3:2 =0
G2:1=0 P2:1 =1
G1:0=0 P1:0 =1
G0=C0 =0B = 1100Cin = 0
S = 0111
G3:0=1 P3:0 =0
G1 = C1 =0G2 = C2 =0
S 0111Ccout = 1
3:0
G3 = C3 =1
S0= 1S1= 1S2= 1S3= 0Cout = 1 0123out
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SpecificationsSpecifications
• Max frequency = 374.94 MHzMax frequency 374.94 MHz
• Area = 440 µm X 300 µm = 0.132 mm^2
• Power = 460 uWPower = 460 uW
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Worst Case DelayWorst Case Delay
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Power ConsumptionPower Consumption
Avg Power = (1.224*10^‐12)*fmax = 0 46 mW0.46 mW
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Implementation DetailsImplementation Details
• Designed schematic of 8‐bit KSA (Full adder)es g ed sc e at c o 8 b t S ( u adde )– Technology = AMS 0.35 µm (4 metal layer)– 518 MOSFETs (=259 CMOS)– Cadence Virtuoso Schematic Editor– Spectre (simulator)
• Designed complete layout– Cadence Virtuoso Layout Editor
f l d if d i• Successful DRC and LVS to verify design• Synthesis – Xilinx Spartan‐3 FPGA
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SchematicSchematic
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LayoutLayout
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DRC ReportDRC Report
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LVS ReportLVS Report
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Synthesis ReportSynthesis Report
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AdvantagesAdvantages
• High SpeedHigh Speed
• Low and regular Fan out
l i G• Regular structure – easy mapping to FPGA fabric
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Main ChallengesMain Challenges
• Layout DesignLayout Design
• DRC constraints
S i• LVS constraints
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ConclusionConclusion
• We designed and implemented 8 bit Kogge‐We designed and implemented 8 bit KoggeStone Tree Adder that operates at 375 MHz(f ) and complete layout takes an areaMHz(fmax) and complete layout takes an area of 440 X 300 um^2
24
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ReferencesReferences
• Swaroop Ghosh Patrick Ndai Kaushik Roy "ASwaroop Ghosh, Patrick Ndai, Kaushik Roy. A Novel Low Overhead Fault Tolerant Kogge‐Stone Adder Using Adaptive Clocking" DATEStone Adder Using Adaptive Clocking . DATE 2008.
• J Rabaey "Digital Integrated Circuits: A Design• J. Rabaey, Digital Integrated Circuits: A Design Perspective", Prentice Hall, 1996.