FPGA IMPLEMENTATION OF HIGH SPEED VEDIC MULTIPLIERUSING CSLA FOR PARALLEL FIR ARCHITECTURE

Amina Naaz.S 1, Mr.Pradeep M.N 2, Satish Bhairannawar 3, Srinivas halvi 4 1, 2, 3 Department of Electronics & Communication, Dayanandasagar College of Engineering, Bangalore, India

4 Department of Medical Electronics, Dayanandasagar College of Engineering, Bangalore, India1aminakhadeerulla@gmail.com, 2pradec023@gmail.com

Abstract In todays world lots of research work is going in the field of communication and signal processing applications. Every application demands for a higher throughput arithmetic operation. One of the key arithmetic operations is multiplication which takes maximum execution time. The development of efficient multiplier is a subject of interest over decades. So there is a need for an efficient multiplier which obtains higher performance for real time signal processing application. This paper presents the modular design of Vedic multiplier using carry select adder.The delay of proposed multiplier is reduced due to high speed carry select adder. The proposed multiplier is applied to parallel FIR filter. It can be observed that the combinational delay reduced for the proposed multiplier compared to existing architecture.

Keywords- Urdhva Tiryakbhyam, FIR (FINITE IMPULSE RESPONSE), Vedic Mathematics, Parallel FIR Architecture,FFA (FAST FIR ALGORITHM).

I. INTRODUCTION

In many DSP algorithms, the multiplier lies in the critical delay path and ultimately determines the performance of algorithm. The speed of multiplication operation is of great importance in DSP as well as in general processor. In the past multiplication was implemented generally with a sequence of addition, subtraction and shift operations. There have been many algorithms proposals in literature to perform multiplication, each offering different advantages and having tradeoffs in terms of speed, circuit complexity, area and power consumption. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to the square of its resolution i.e. amultiplier of size n bits has n gates. For multiplication algorithms performed in DSP applications latency and throughput are the two major concerns from delay perspective. Latency is the real delay of computing a function, a measure of how long the inputs to a device are stable is the final result available on outputs and throughput is the measure of how many multiplications can be performed in a given period of time.

Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers. The most common multiplication algorithms followed in the digital hardware are array multiplication algorithm and Booth multiplication algorithm. The computation time taken by the array multiplier is less because the partial products are calculated

independently in parallel. The delay associated with the array multiplier is the time taken by the signals to propagate through the gates that form the multiplication array. Booth multiplication is another important multiplication algorithm. Large booth arrays are required for high speed multiplication and exponential operations which in turn require large partial sum and partial carry registers. Multiplication of two n-bit operands using a radix-4 booth recording multiplier requires approximately n / (2m) clock cycles to generate the least significant half of the final product, where m is the number of Booth recorder adder stages. Thus, a large propagation delay is associated with this case. Due to the importance of digital multipliers in DSP, it has always been an active area of research and a number of interesting multiplication algorithms have been reported in the literature.

Vedic mathematics was rediscovered in the early twentieth century from ancient Indian scriptures (Vedas). The conventional mathematical algorithms can be simplified and even optimized by the use of Vedic mathematics. The Vedic algorithms can be applied to arithmetic, trigonometry, plain and spherical geometry, calculus. One of the main purposes of Vedic mathematics is to transform the tedious calculations into simpler and orally manageable operation. Vedicmathematics provides more than one method for basic operations like multiplication and division. For each operation there is at least one generic method provided along with somemethods which are directed towards specific cases simplifyingthe calculations further. Central Processing Unit isincreasingly working on higher frequencies with reduction in size of transistor. Arithmetic and Logic Unit (ALU) is one of the most important and critical blocks in Central Processing Unit. Hence it is imperative to have fast and efficient ALU. Division is the most time consuming among the basic mathematical calculation. In computing technology functions like Sine and Cosine are also frequently required and are implemented in hardware. With these considerations, it is always important to have fast and efficient mechanism toimplement mathematical functions. Vedic mathematics provides algorithms to simplify the mathematics and hence is perfect solution for the problem stated and also consumes less area.

Organization: The paper is organized as follows: Section II proposes the related work. Section III contains architecture ofproposed Vedic multiplier. Section IV provides application of proposed Vedic multiplier in parallel FIR filter. Section V contains results and discussion. Section VI conclusions followed by future work.

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 1

978-1-4799-1356-5/14/$31.00 2014 IEEE

II. RELATED WORK

Laxman P.Thakre et al., [1] proposed the concept of URDHVA TIRYAKBHYAM sutra and NIKILAM sutra. Theconventional multiplier has been synthesized, simulated & compared with Vedic multiplier individually & also tested in FFT operations. It reveals that 80% more hardware, memory& area are consumed by conventional multiplier whencompared to Vedic multiplier. S.S.Kerur et al., [2] proposed fast Vedic multiplications are required to compute Convolution, FFT, etc. Here multiplication is done using URDHVA TIRYAKBHYAM algorithm based on ancient Vedic mathematics. The combinational delay obtained is compared with the normal multiplier. Further the Vedicmultiplier is used in matrix multiplication. The proposed Vedic multiplier proves to be efficient in terms of speed.G.Vaithiyanathan et al., [3] proposed that Vedic multiplier implemented using URDHVA TIRYAKBHYAM sutraconsumes less power compared to array multiplier.PushpalataVerma and K.K.Mehta [4] proposed 8 bit architecture of Vedic multiplier using ripple carry adder. The proposed architecture is compared with conventional method of multiplication, it is inferred that proposed is faster compared to conventional method. Nivedita A. Pande et al., [5] proposed a design-methodology for high-speed multiplications, where two integers of n-bit size each are multiplied to produce a 2n-bit product. This paper presents an efficient and simple method for performing multiplications, where the lower level multipliers can be used to design higher level multipliers. Krishnaveni D and Umarani [6] proposed a4x4 binary multiplier designed using URDHVA TIRYAKBHYAM sutra. A new 4-bit adder is proposed which when used in multiplier, reduces its delay. R.Naresh Naik et al., [7] proposed floating point multipliers implemented usingURDHVA TIRYAKBHYAM sutra shows considerably improvement in speed when compared to normal Booth multiplier. R.Priya and J.Senthil Kumar [8] proposed amodified CLSA applied to Vedic multiplier which shows reduction in gate count compared to regular CLSA. Arushi Somani et al., [9] proposed Vedic multiplier and compared with conventional method in terms of power, delay, space, speed, power delay product and energy delay product.

III. PROPOSED ARCHITECTURE OF 16X16 VEDIC MULTIPLIER

The multiplication of 2x2 using Urdhva Tiryakbhyam for 13x12 is as explained below. The least significant digit 3 of multiplicand is multiplied vertically by least significant digit 2 of the multiplier, get their product 6 and set it down as the least significant part of the answer, then 2 and 1, 3 and 1 are multiplied crosswise, add the two, get 5 as the sum and set it down as the middle part of the answer, then 1 and 1 is multiplied vertically, get 1 as their product and put it down as the last the left hand most part of the answer.So 13 12 = 156.

1 3

1 2

1 5 6

The Urdhva Tiryagbhyam algorithm can be implemented for binary number system in the same way as decimal number. The 22 Vedic multiplier module is then used to implement higher level multipliers (44 multiplier, 88 multiplier, 1616 multiplier). The 16x16 proposed Urdhva Tiryakbhyam using 8x8 Vedic which are designed using 4x4 in turn 2x2 modules and high speed carry select adder is as shown in Figure 1. The proposed method was compared with existing architecture [10] where the modular design of Vedic Urdhva Tiryagbhyammethod using carry save adder and 17 bit ripple adder were discussed. In our proposed method the adders are replaced with high speed carry select adders which in turn reduce the delay and increases the speed of entire Vedic architecture.

B15-b8 a15-a8 b7-b0 a15-a8 b15-b8 a7-a0 b7-b0 a7-a0

(15-0) (15-0) (15-0) (15-8) (7-0)

Q31-Q16 Q15-Q8 Q7-Q0

Figure 1. Proposed architecture of 16x16 bit Vedic multiplier

The proposed 16x16 bit Vedic multiplier is structured using four 8x8 Vedic modules and two carry select adders. The carry select adder used in the design increases the speed of addition of partial products, as carry select adders has less delay when compared with all other adders. The 16 bit multiplicand A can be decomposed into pair of 8 bits AH-AL. Similarly multiplicand B can be decomposed into BH-BL.The least significant 8 bits of multiplicand i.e. (a7-a0) and (b7-b0) are multiplied vertically which gives the LSB 8 bitsproduct (Q7-Q0). The right most carry select adder adds three input from three right most 8x8 Vedic multiplier. The LSB bits of right most carry select adder is retained for the product(Q15-Q8) and the MSB bits are fed to the left most carry select adder, to add with the output of left most 8x8 Vedic multiplier which gives the final 16 bit product (Q31-Q16). The outputs of 8X8 bit multipliers are added according toUrdhvaTiryagbhyam Sutra to obtain the 32 bits final product. Thus, in the final stage two carry select adders were used so that there is considerable improvement in speed.

8x8VM 8x8 VM 8x8VM 8x8 VM

Carry Select Adder

Carry Select Adder

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 2

IV. PROPOSED VEDIC MULTIPLIER IN PARALLEL FIRARCHITECTURE

FAST FIR ALGORITHM (FFA) :

The Finite Impulse Response (FIR) performance speed can be improved by utilizing property of symmetry. To exploit thesymmetry of coefficients, main idea is to manipulate the polyphase decomposition to earn as many subfilter blocks as possible, which contain symmetric coefficients so that half the number of multipliers within a single subfilter block can be utilized for the multiplications of whole taps. For a set of symmetric coefficient in odd length N, when (N mod 3) equals zero as shown in equation 5 can earn two more sub filter blocks containing symmetric coefficients. The implementation of the three-parallel FIR filter [11] modified for 33-tap FIR filter is shown in Figure 2.

Example 1: Consider a 33-tap FIR filter with a set of symmetric coefficients as follows:

{h(0), h(1), h(2), h(3), h(4), h(5),

h(6), h(7), h(8), h(9), . . . , h(32)}

Where h (0) = h (32), h (1) = h(31),

h (2) = h (30), h (3) = h (29),

h (4) = h(28), h(5) = h(27), . . . ,h (12) = h (20),

The symmetric coefficients for 33 tap filters can be applied as shown in Figure 2.

H0 H2 = {h (0) h (2), h (3) h (5), h (6) h (8) . . . h (18)

h (20), h (21) h (23), h (24) h(26)}

Where h (0) h (2) = (h (32) h (30))

h (3) h (5) = (h (29) h (27))

h (6) h (8) = ( h (26) h (24))

h (9) h (11) = (h (23) h (21))

Y0 = H0X0 +

{(H1 + H2) (X1 + X2) H1X1

((H0 + H2) (X0 + X2) H0X0

[(H0 + H2) (X0 + X2)

(H0 H2) (X0 X2)])} (1)

Y1 = (H0 + H1 + H2) (X0 + X1 + X2) (H1+H2) (X1+X2) (H0 + H2)(X0 + X2)

+ {(H0 + H2) (X0 + X2)

[(H0 + H2) (X0 + X2)

(H0 H2) (X0 X2)] H0X0}

+++ {(H0 + H2) (X0 + X2)

[(H0 + H2) (X0 + X2)

(H0 H2) (X0 X2)] H0X0} (2)

Y2 = H1X1 +

[(H0+H2) (X0+X2) (H0H2) (X0X2)] (3)

X1 - - Y0

X2 - -

- Y2-

- Y3

-

X3

Figure 2. Three parallel FIR filter implemented using symmetric coefficients in odd length (N mod 3 =0)

H1

(H0-H2)

H1+H2

H0+H1+H2

H0

(H0+H2)

Design of H1subfilter block:

X1=2

h1=2 h4=5 h7=8 h10=11 h13=14 h16=17 h19=14 h22=11 h25=8 h28=5 h31=2

m1=4 m2=10 m3=16 m4=22 m5=28 m6=34 m7=28 m8 =22 m9=16 m10=10 m11=4

a1=14 a2=30 a3=52 a4=80 a5=114 a6=142 a7=164 a8=164 a9=190 a10=194

Figure 3. Internal structure of filter blocks H1.

The symmetric parallel FIR filter is shown in Figure 2. The three parallel FIR filter consists of filter blocks. The input to the system is represented as X0, X1, X2 and the response of the system as Y0, Y1 and Y2. Let X0=5, X1= 2, X2=3. The filter blocks H1 with its mod 3 coefficients are shown in Figure 3. It requires 11 multipliers, 10 adders with 10 delay elements to get H1.similarly filter blocks H0, H0+H1+H2, H0+H2, H0-H2, H1+H2 with its mod 3 coefficients each block requires 11 multipliers, 10 adders with 10 delay elements to .With similar approach other sub filter blocks can be drawn and Y0 +Y1+Y2 can be calculated. The proposed high speed Vedic multiplier isused in parallel FIR architecture. The proposed technique improves the speed of FIR filters and area utilization when compared to traditional Vedic multiplier. .V. RESULTS AND DISCUSSION

TABLE I : COMPARISON RESULTS OF EXISTING AND PROPOSED VEDIC MULTIPLIER

XC3S400 -5 PQ208 Existing Vedicmultiplier[10]

Proposed Vedicmultiplier

Delay 58.24ns 40.83ns

Number of Slices 461 out of 3584(12%) 445 out of 3584 (12%)

Number of 4inputLUTs

808 out of 7168(11%) 777 out of 7168(10%)

Number of bondedIOBs

64 out of 141 (45%) 64 out of 141 (45%)

It has been observed that for proposed 16x16 Vedic multiplier module has gate delay of 40.843ns with Device utilization of 12% while it is 58.24 ns with Device utilization of 12% for the

existing 16x16 Vedic multiplier module. It can clearly show that the proposed Vedic multiplier is faster compared to existing multiplier.

TABLE II: COMPARISON RESULTS OF PARALLEL FIR ARCHITECTURE USING EXISTING AND PROPOSED 16X16 BIT VEDIC MULTIPLIER

XC3S400 -5pq208

Parallel FIR Architecture with existing Vedic

multiplier[10]

Parallel FIR Architecture with proposed Vedic

multiplier

Delay 73.682ns 58.924ns

Number of Slices

3582 out of 3584 (99%) 3517 out of 3584(98%)

Number of slice flip flop

1024 out of 7168(14%) 1024 out of 7168(14%)

Number of 4-inputLUTs

6693 out of 7168(93%) 6382 out of 7168(89%)

Number of bondedIOBs

146 out of 141 (103%) 146 out of 141 (103%)

It has been observed that for parallel FIR architecture using proposed 16x16 bit Vedic multiplier module has gate delay of58.924ns with Device utilization 3517 out of 3584 and number of 4- input LUTs are 6382 out of 7168 while it is 73.68ns with device utilization of 35582 out of 3584 . This shows thatproposed Vedic multiplier applied to parallel FIR Architecture has less delay and area. It is clearly seen from the above results

D D D D D D D D D DD D DD DDD D DDDD D DDDDD D DDDDD D DDDDD D DDDDDDDDDD DD

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) 4

that there is considerable speed improvement. Therefore the proposed multiplier, when used in other applications can really yield good results.

A. RTL SCHEMATICS:

a. RTL View of proposed 16x16 bits Vedic multiplier

Figure 4. Hardware implementation of proposed Vedic multiplier.

The RTL view of proposed Vedic multiplier is shown in Figure 4.

b. RTL view of parallel FIR architecture using proposed16x16 bit Vedic multiplier

Figure 5. Hardware implementation of parallel FIR filters using proposed Vedic multiplier.

The RTL view of parallel FIR filter using proposed Vedic multiplier is shown in Figure 5.

VI. CONCLUSION

The proposed 16x16 Vedic multiplier architecture has been designed and synthesized using on Spartan 3 XC3S400 boardand is used in parallel FIR filter design. The proposed Vedic multiplier with carry select adder is compared with the existing Vedic multiplier and can be inferred that proposed is faster compared to existing Vedic multiplier. In future the proposed multiplier performance parameters can be improved by high level pipelining operations and applied in signal processing applications like image processing and video processing.

REFERENCES

[1] Laxman P.Thakre, Suresh Balpande, Umesh Akare, Sudhir Lande,Performance Evaluation and Synthesis of Multiplier used in FFT operation using Conventional and Vedic algorithms, Third international conference on emerging trends in Engineering and Technology , IEEE, 2010.

[2] S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V. A., Implementation of Vedic Multiplier for Digital Signal Processing, International Conference on VLSI ,Communication & Instrumentation (ICVCI), 2011.

[3] G.Vaithiyanathan, K.Venkatesan, S.Sivaramakrishnan, S.Sivaand, S.Jayakumar, Simulation and implementation of Vedic multiplier usingVHDL code, International Journal of Scientific & Engineering Research, vol.4, 2013.

[4] Pushpalata Verma and K. K. Mehta, Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool, International Journal of Engineering and Advanced Technology (IJEAT), vol.1, June 2012.

[5] Nivedita A. Pande, Vaishali Niranjane, Anagha V. Choudhari, Vedic Mathematics for Fast Multiplication in DSP, International Journal of Engineering and Innovative Technology (IJEIT) ,vol.2, 2013. [6] Krishnaveni D. and Umarani.T.G, Vlsi implementation of Vedic

multiplier with reduced delay, International Journal of Scientific &Engineering Research, vol.2, May-2011.

[7] R.Naresh Naik, P.Siva Nagendra Reddy, K. Madan Mohan, Design of Vedic Multiplier for Digital Signal Processing Applications,International Journal of Engineering Trends and Technology (IJETT),vol.4, 2013.

[8] R.Priya and J.Senthil Kumar, Implementation and comparison of Vedic Multiplier using Area Efficient CSLA Architectures, International Journal of Computer Applications, vol 73, July 2013.[9] Arushi Somani, Dheeraj Jain, Sanjay Jaiswal, Kumkum Verma and

Swati Kasht, Compare Vedic multipliers with Conventional Hierarchical array of array multipliers, Computer Technology and Electronics Engineering (IJCTEE),vol.2, 2012.

[10] Manoranjan Pradhan, Rutuparna Panda and Sushanta Kumar Sahu, Speed Comparison Of 16x16 Vedic Multipliers, International Journals of Computer Applications, vol.21, May 2011.

[11] Yu-Chi Tsao and Ken Choi, Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm, IEEE Transactions on circuits and systems, vol.59, June 2012 .

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/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 200 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages false /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 400 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 600 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile (None) /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

/CreateJDFFile false /Description >>> setdistillerparams> setpagedevice