7 Jan - CMOS Devices - Navakant.pdf

8/14/2019 7 Jan - CMOS Devices - Navakant.pdf

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Navakanta Bhat

CMOS Devices

Process Integration

Navakanta Bhat

ProfessorCentre for Nano Science and Engineering (CeNSE)

Dept. of Electrical Communication Engineering,

Indian Institute of Science, Bangalore


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Outline

CMOS Technology and Design Objectives

Isolation

Wells

Gate Stack

Junctions

Interconnects


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The Integrated Circuit Food Chain

Optimization across all the domains is necessary

Process Technology

Device Physics

Circuit Design

System Architecture

Application

Domain

Technology

Domain

CAD and Modeling

Computational State Variable

Digital Architecture

Boolean Logic

CMOS

Charge

Silicon


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What is in a IC Chip ?A large ensemble of transistors connected appropriately

through multilevel metal interconnection lines

Every thing should be made as simple as possible,but no simpler! Albert Einstein

INTEL IBM


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CMOS : NMOS + PMOS

switch modellay outschematic

Gate

Drain

Source

CMOS

IDcross section

NMOSFET

n n

Silicon

G

p-well

oxide

VG

Vth

p p

Silicon

G

n-well

oxide

PMOSFET

Vth

CMOS


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Performance Metrics in CMOS

P=CL*Vdd2*fD= CL*Vdd/Ids

CL

IN OUT

Vdd

Ids

Ids

CL , total capacitance at the switching node

Vdd , supply voltage

f , switching frequency

Ids , charging or discharging current

INVERTER Gate CapacitanceJunction Capacitance

Interconnect Capacitance

CAPACITANCE IS INERTIA


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Vt-Vdd design planeNormalized delay

Vt/Vdd0.4

Delay increases significantly for Vt/Vdd > 0.4

Pactive (Pac) = CVdd2

fPstandby (Psb) = WVddIoff

Vt

Vdd

Psb

Pac

Delay

Delay and Power are the only trade-off points for digital design


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Transistor Design Metrics

Ioff

Ion Ion

CDC Metric AC Metric

BETTERDESIGN

BETTERDESIGN


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Transistor design methodology for Digital CMOS

Design parameters: L, Vdd, Tox, N, Xj

S/D engineering

Channel engineering

Choice of materials and processes

Circuit characteristics:

Delay (Vt/Vdd)Active power (Vdd)

Standby power (Vt)

Hot carrier reliability

Vdd, L, N

Gate oxide reliability

Vdd, Tox

System compatibility

Vdd


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Constant Electric Field Scaling

Primary scaling factors:

Tox, L, W, Xj (all linear dimensions) 1/K

Na, Nd (doping concentration) K

Vdd (supply voltage) 1/K

Derived scaling behavior of transistor:Electric field 1

Ids 1/K

Capacitance 1/K

Derived scaling behavior of circuit:Delay (CV/I) 1/K

Power (VI) 1/K2

Power-delay product 1/K3

Circuit density (

1/A) K2

Technology scaling

Scaling factor K > 1



Technology Life cycle

Source : ITRS 2007



Worldwide Wafer Production across Technologies

Source : ITRS 2007



Microelectronics to Nanoelectronics

1960 2020

New Materials and

Device structuresSilicon CMOS

2010

45nm 15nm

Nano-scale building blocks and Giga-scale Integration!

Channel quantization

Quasi ballistic transport

SCALiNG

Gate tunneling



ITRS Projections

Year of Production

2007 2010 2013 2016 2019 2022

Technology Node (nm) 65 45 32 22 16 11

Printed Gate Length (nm)

Physical Gate Length (nm)

42

25

30

18

21

13

15

9

11

6.3

7.5

4.5

Wafer diameter (inch) 12 12 18 18 18 18

Number of masks required for

fabrication of Microprocessor

33 35 37 37 39 39

Number of Transistors inMicroprocessor (billion)

1.1 2.2 4.4 8.8 17.7 17.7

Number of interconnect wiring

levels in the Microprocessor

15 16 17 17 18 18

Number pins for packagedMicroprocessor chip

1088 1450 1930 2568 3418 3760

Operating voltage (V) 1.1 1.0 0.9 0.8 0.7 0.7

Microprocessor frequency, GHz 9.3 15.1 23 39.7 62.4 73.1

Chip power dissipation (Watts) 189 198 198 198 198 198



ISOLATION MODULE

LOCal Oxidation of Silicon (LOCOS)

Shallow Trench Isolation

SiO2 is used isolate two transistors



LOCOS Isolation

~10nm Pad SiO2Dry oxide

Si

~15nm Si3N4LPCVD

Si

Active Litho,

Dry etch

Si

~500nm Field SiO2Wet oxide

Si

Strip nitride, oxideWet etch

Si Si

Scalability is an issuedue to Birds beak

Not suitable for < 250nmComment on Wafer Type



Shallow Trench Isolation

~10nm Pad SiO2Dry oxide

Si

~15nm Si3N4LPCVD

Si

Active Litho,Dry etch

~350nm depth

Si

Si

Liner oxide (~10nm)HDPECVD trench fill

TEOS chemistry

Si

Chemical MechanicalPolishing, HF dip,

Nitride strip



Well Module

What are the requirements forNano MOSFET Design ?



SHORT

CHANNEL

EFFECTS

Nano MOSFET : Design Issues

S D

GS D

G

Leakage current

L (m)

Vt

~1m

Drain Induced

Barrier Lowering (DIBL)

Vt roll-off



How do you minimize SCE?

Screen the electric field

Increase Substrate Doping Concentration

Increased impurity scattering

Degradation of sub-threshold slope

Increased junction capacitance

Minimize coupling volumeDecrease source/drain depth

Increased source/drain resistance

Junction spiking


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Transistor Structure Requirement

Y

X

Pocket halo

Super steep retrograde

channel

spacer

n+n+

p-well

gate

oxide

source drain

Short channel effects are controlled by shallow extensions,

pocket halos and super steep retrograde channel

Na

L0 Y

Na

0 X

Deep S/D and

Shallow Extension


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Other Requirements

Si

Prevent DeepPunch Through

Account for highfields at trenchcorner

Adjust Vt

USE CHAIN OF IMPLANTS


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Well Implant Chain

Boron ~ 200 KeV, 1012 1013 /cm2

Boron ~100 KeV, 1012 1013 /cm2

Boron ~50 KeV, 1012 1013 /cm2

Boron ~ 15 KeV, 1012 1013 /cm2

Indium ~ 120 KeV, 1012 1013 /cm2

Phosphorus ~ 600 KeV, 1012 1013 /cm2

Phosphorus ~300 KeV, 1012 1013 /cm2



Antimony ~ 150 KeV, 1012 1013 /cm2

P-Well N-Well

Multiple Vt Technology


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Gate Stack Module

SiO2, Dual Polysilicon Gate

High-K, Metal Gate


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Polysilicon Gate stack

Si

Phase Shift Litho

Resist Trim

Si

Poly Etch

Si

i-PolySiliconLPCVD

Si

Dry, 800C, O2+N2Nitridation

Si

RCA Clean

NBTI Reappears!

Comment on Dual

Gate technology


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Why High-K and Metal Gate

Increasing gate resistance

for short channel device

Activation of poly-Si

Direct Tunneling current

High K Metal Gate Gate stack


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High-K Metal Gate Gate stack

Si

RCA Clean

Si

PVD HfO2

Si

i-PolySiliconLPCVD

Si

Phase Shift Litho

Resist Trim

Si

Poly Etch

DISPOSABLE GATE PROCESS

Dispose -off polySi after

ILD0 and fill the gate

trench with dual metalgate materials

Ensures Self Aligned

transistor


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Junction Module


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NMOS Halo and Extension

Si

Si

Arsenic, 0o tilt, ~1014, 5KeV

Si

Boron, 45o

tilt, ~1012

, 15KeVNMOS S/D Litho

STORY #1:

Shadow


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PMOS Halo and Extension

Si

Phosphorus, 45o

tilt, ~1012

, 35KeV

Si

BF2, 0o tilt, ~1014, 3 KeV

Si

PMOS S/D Litho

STORY #2


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Spacer Formation

Deposit 10nm Oxide, 40nm nitride

What about Oxide spacers ??

Boron segregation degrades PMOS

Si

Anisotropic nitride etchSi

STORY #2: Cgd

Comment on offset spacers for extension

Deep S/D Implant and Anneal


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Deep S/D Implant and AnnealNMOS S/D Litho

Arsenic, 15 KeV, ~1015

Si

PMOS S/D Litho

Boron, 5 KeV, ~1015

Si

Si

RTA

Trade off between poly depletion,versusJunction depth & Boron Penetration

Sili id F ti


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Silicide Formation

PVD Metal

RTA

ETCH METAL

S D

G

Parasitic Channel Resistance

Si


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Interconnect Module


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ILD0 , Contact and Metal1

Si

ILD0 CVDContact Litho & Etch

W CVD and CMP

Aluminum PVDMetal Litho & Etch

Forming gas anneal

Same process continues for Via1, Metal2, Via2, Metal3

STORY #3: Yield


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Interconnect delay in Nano CMOS

Delay

0.50.350.250.18

Technology node (m)

Intrinsic gate delay

Interconnect delay

Gate delay decreases due to decrease in gate capacitanceInterconnect delay increases due to decreasing metal line width

and increasing intra-metal coupling capacitance

Interconnects are no longer afterthought in Nano CMOS

Copper Interconnects


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Copper Interconnects

ILD CVD (thickness for via and metal)

Litho Via holes and etch via hole

Litho Metal trenches and etch metal trenchCopper Electroplating and CMP

Si

Dual Damascene Process


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Beyond Bulk Silicon CMOS


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SOI CMOS ?

500mInsulator

SOI Bulk

Si wafer

Si film

(10-100nm)

Devices are built on thin Si film (~100nm) on insulatorHandle Si wafer may be underneath the insulator (VLSI)

Insulator itself may form the rest of the substrate (Displays)

Si wafer

Partially Depleted SOI (PDSOI) versus Fully Depleted SOI (FDSOI)


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Components of node capacitance

CL=Cg + Cj + Ci

Cg = gate oxide capacitance

Cj = junction capacitance

Ci = interconnect capacitance

Cj= s A/Wd

s, permittivity of Si

Wd, depletion width

A , cross section area


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Other SOI specific effects

Fewer processing steps

Better isolation resulting in dense circuits

Drain current overshoot

Lower body effect

Absence of latch-up problem

Better sub-threshold slope

Threshold voltage (Vt) instability due to DC floating body effect


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SOI device delay

SOI results in at least 30% lower delay compared to bulk

The improvement is more pronounced at lower voltages

IBM data

SOI results in about 70% lower power for the same speed

IBM data


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SOI Power dissipation

SOI results in about 70% lower power for the same speed

IBM data

N d f M lti t FET


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Need for Multigate FETs

Alternate structures required for better gate control over the chann

- Double Gate, FinFET, Surround Gate

SiO2

n+ n+p

Increase in P type doping

with decreasing L results

inn+-p+ tunnel junction

Intels data

Fin FET


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Fin FET

H.S.P Wong, IBM Technical Journal

C OS ?


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CMOS with new materials ?

Germanium / GaAs / GaN ?

Graphene ?

Planar Technologies are Circuit designer friendlyas opposed CNT and other vertical transistors


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Germanium Schottky Barrier MOSFETs

Doped S/D

RovR

dp

R

extRscd

GateSpacer

Silicid

e

oxide

Metal

Advantages

Reduced series resistanceReduced short channel effects

Low thermal budget process Easy for Metal gate

Reduced process variability

*

* S-D Kim et al., Advanced Model and analysis of series resistance for CMOS scaling , IEEE TED, Vol. 49, No. 3, Marc

What about NMOS Schottky


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What about NMOS Schottky

Junction Transistors on Ge (or Si)

Technologically hard problem

Fermi level pinning in the bottomhalf of the band gap

For Si : Eg/3 above valence band edge

For Ge : Close to valance band edge

Schottky junctions on n-type Ge/Si are possible Schottky junctions on p-type Ge/Si have never been

very efficient

Ec

Ev

Ei


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Is it possible to passivate the interfaceand De-pin the Fermi level?

Literature on Sulphur passivationof III-V semiconductors exists

C S f


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Current State-of-the-art

Sulphur implantation: results in ohmiccontacts to both substrate types. Not

possible to produce Schottky Source/Drain. Passivation studies for Ge High-k

interface

done only for p-channel devices. N-channel

devices have proved very difficult to

passivate.

No studies exist on the effect of passivation

on Schottky Interface.

S l h P i i f G f


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Sulphur Passivation of Ge surface

Ge cleaned in HCl-HBr mixture to remove

native oxide.

Subsequently treated in Aqueous

Ammonium Sulphide ((NH4)2S ) solution

Passivation treatment carried out close toboiling point.

Al, Zr, Ta (Low work function)W, Ni, Pt (High work function)

XPS t di


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XPS studies

1210 1215 1220 1225 1230Binding Energy (eV)

Intensity(ArbitraryUnits)

Ge-SGe 2p3/2

160 165 170Binding Energy (eV)

Intensity

(ArbitraryUnits)

S 2p

25 30 35Binding Energy (eV)

Intensity

(ArbitraryUnits)

GeO2

S-pass.

HCl-HBr

Ge 3d5/2

Bare Ge

Native oxide peak disappears after cleaningand sulphur passivation

Sulphur peak is evident on Sulphur treatedWafers

Ge-S peak also apperas indicating that sulphur

Is chemically active on the surface

S h ttk t t G


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Schottky contact on p-Ge

Modification of behavior on p-Ge

-1 -0.5 0 0.5 1-60

-40

-20

0

20

40

60

Voltage(V)

J(A/cm

2)

Al pass.Zr pass.

Zr Un-pass.

Al Un-pass.

EV

EC

Eg

S h ttk t t G


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Schottky contact on n-Ge

Modification of behavior on n-Ge

-1 -0.5 0 0.5 1-60

-40

-20

0

20

40

60

Voltage(V)

J(A/c

m2)

Al Un-pass.Zr Un-pass.

Al pass.

Zr pass.

B i h i h d f i ti


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Barrier height trend after passivation

4.05 4.5 5 5.5 60

0.1

0.2

0.3

0.4

0.5

0.6

0.66

Un - passivated.

S - passivatedZr

Al

Ta

Ta

Zr

AlW

Ni

Pt

mvac

Electron

Barrie

r(Bn

)

Sulphur

passivation

results in almost ideal Schottky

behaviour

Ideal Theory

Arun

& Bhat

APL, 2010

S


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Summary

CMOS Process Integration

Isolation module

Well module

Gate stack module

Junction module

Interconnect module

CMOS Process Complexity continues to

increase with technology scaling


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Thank You

7 Jan - CMOS Devices - Navakant.pdf

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