Fundamentals of CMOS VLSI Jan 2014

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USN 10ECs6 Fifth Semester B.E. Degree Examination, Dec. 2013 / Jan 2014. Fundamentals of GMOS VLSI Time: 3 hrs. Max. Marks:100 Note: Answer any FIVE full questions, selecting atleost TWO questions from euch part. , J ' -- -- PART. A I a. Explain the fabrication steps of CMOS P - well process with neat diagram and write the _ mask sequence. (12 Marks) b. List the threshold voltage equations and emphasize each term. (08 Marks) 2 a. Write the CMOS inverter circuit and briefly explain. Write the CMOS VTC showing regions A, B, C, D, E. Derive the expressions for output voltage in region 'B'. (10 Marks) b. Write the circuit and layout for Y : AB + CDLF E in CMOS style. (10 Marks) --fL--_, v1,t, 0.6 v vq l* 3a. b. c. o o o _3 o d () ! ?o i^r troo .=N oYt oi ao =P 3s 6: oc) =h o-o 26 -o(B ->B oE ^X o.' oj dtE !o 5." >.: 50- ecQ o= *o tr> o- t< -al (.) o Z Write the circuit and stick diagram for CMOS tristate inverter. write the circuit otBiCMos NAND and NoR gate and briefly explain. Explain the circuit of dynamic CMOS iogic by taking an eiampre Y = [1[1611ffi. 4 a. Define Sheet Resistance (Rs) and standard unit of capacitance (rCg). Calculate the on ,,,:iL D^ - t't-t'\t- '7 - 81 7 - 2) resistance of 4:1 nmos inverter with Rs : 10k0li, Zpu: ; , Zpd = :4. Also estimate the total power dissipated if Voo : 5V. b. Calculate the capaoitance in r Cg for the given metal layer shown in fig.e4(b),tii#,T:l size : 5prm and relative value of metal to substrate : 0.075. ' (05 Marks) 3rt Fie.eatb) * c. trxplain briefly the circuit a. Calculate the O/P voltage 5oA ---> of inverting and non - inverting super buffer. (04 Marks) (08 Marks) of the function (08 Marks) (07 Marks) PART - B Voul in tt. .t@uen below for different values of Vu, Vu. (04 Marks) *, *:# !-gY f Vs& J Fig.Qs(a) For More Question Papers Visit - www.pediawikiblog.com For More Question Papers Visit - www.pediawikiblog.com www.pediawikiblog.com

Transcript of Fundamentals of CMOS VLSI Jan 2014

Page 1: Fundamentals of CMOS VLSI Jan 2014

USN 10ECs6

Fifth Semester B.E. Degree Examination, Dec. 2013 / Jan 2014.Fundamentals of GMOS VLSI

Time: 3 hrs. Max. Marks:100

Note: Answer any FIVE full questions, selecting atleost TWO questions from euch part., J

' -- --

PART. AI a. Explain the fabrication steps of CMOS P - well process with neat diagram and write the

_ mask sequence. (12 Marks)b. List the threshold voltage equations and emphasize each term. (08 Marks)

2 a. Write the CMOS inverter circuit and briefly explain. Write the CMOS VTC showingregions A, B, C, D, E. Derive the expressions for output voltage in region 'B'. (10 Marks)

b. Write the circuit and layout for Y : AB + CDLF E in CMOS style. (10 Marks)

--fL--_, v1,t, 0.6 vvq l*

3a.b.

c.

ooo

_3

od()!

?o

i^rtroo.=N

oYtoiao

=P

3s6:

oc)=ho-o

26

-o(B->BoE

^Xo.'oj

dtE

!o5.">.:50-ecQo=*otr>o-

t<-al(.)

oZ

Write the circuit and stick diagram for CMOS tristate inverter.write the circuit otBiCMos NAND and NoR gate and briefly explain.Explain the circuit of dynamic CMOS iogic by taking an eiampreY = [1[1611ffi.

4 a. Define Sheet Resistance (Rs) and standard unit of capacitance (rCg). Calculate the on

,,,:iL D^ - t't-t'\t- '7 - 81 7 -

2)resistance of 4:1 nmos inverter with Rs : 10k0li, Zpu: ; , Zpd = :4. Also estimate the

total power dissipated if Voo : 5V.b. Calculate the capaoitance in r Cg for the given metal layer shown in fig.e4(b),tii#,T:l

size : 5prm and relative value of metal to substrate : 0.075. ' (05 Marks)

3rtFie.eatb) *

c. trxplain briefly the circuit

a. Calculate the O/P voltage

5oA --->

of inverting and non - inverting super buffer.

(04 Marks)(08 Marks)

of the function

(08 Marks)

(07 Marks)

PART - BVoul in tt. .t@uen below for different values of Vu, Vu.

(04 Marks)

*, *:# !-gY

fVs&

J

Fig.Qs(a)

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Page 2: Fundamentals of CMOS VLSI Jan 2014

Design Bus Arbitration logic for n - line bus.

10EC56

(10 Marks)b.

c.

and lpm thick? Assume Jtr,.: lrnA/(pm)2 , R": 10K0 / n , Voo :5V.,(06

MarkO

a.i',,Discuss the 4 phase clocking scheme to avoid the problem of cascading in dynamic CMOSlogie. (06 Marks)

Consider ), - based design rules and 5trrm technology. How many nmos 8:1 inverter

(rr- =* *O ,r^ =*)can be driven by a minimum size conductor which is 3)" wide

b. What are the adder enhancement techniques? Briefly explain. .:. (04 Marks)

c. Write ,,explair

6 - bit carry select adder. (10 Marks)

a. Write ana $aip 4 Transistor dynamic and 6 Transistor stiit'li CIIOS memory cell withsense amplifier. (12 Marks)

b. Explain the one trar{sistor dynamic memory cell emphasizfpg three plate capacitor.(08 Marks)

Write short notes on : " ' .

a. Latch up. (07 Marks)

c. I/O pads. (07 Marks)

2 of2

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