5V, 3.3V, ISR™ High-Performance CPLDs Sheets/Cypress PDFs/Ultra 370000... · 5V, 3.3V, ISR™...

5V, 3.3V, ISR™ High-Performance CPLDs

Ultra37000 CPLD Family

Features• In-System Reprogrammable™ (ISR™) CMOS CPLDs

— JTAG interface for reconfigurability— Design changes do not cause pinout changes— Design changes do not cause timing changes

• High density— 32 to 512 macrocells— 32 to 264 I/O pins— Five dedicated inputs including four clock pins

• Simple timing model— No fanout delays— No expander delays— No dedicated vs. I/O pin delays— No additional delay through PIM— No penalty for using full 16 product terms— No delay for steering or sharing product terms

• 3.3V and 5V versions• PCI-compatible[1]

• Programmable bus-hold capabilities on all I/Os • Intelligent product term allocator provides:

— 0 to 16 product terms to any macrocell— Product term steering on an individual basis— Product term sharing among local macrocells

• Flexible clocking— Four synchronous clocks per device — Product term clocking— Clock polarity control per logic block

• Consistent package/pinout offering across all densities— Simplifies design migration— Same pinout for 3.3V and 5.0V devices

• Packages— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,

BGA, and Fine-Pitch BGA packages— Lead (Pb)-free packages available

General DescriptionThe Ultra37000™ family of CMOS CPLDs provides a range ofhigh-density programmable logic solutions with unparalleledsystem performance. The Ultra37000 family is designed tobring the flexibility, ease of use, and performance of the 22V10to high-density CPLDs. The architecture is based on a numberof logic blocks that are connected by a Programmable Inter-connect Matrix (PIM). Each logic block features its ownproduct term array, product term allocator, and 16 macrocells.The PIM distributes signals from the logic block outputs and allinput pins to the logic block inputs.All of the Ultra37000 devices are electrically erasable andIn-System Reprogrammable (ISR), which simplifies bothdesign and manufacturing flows, thereby reducing costs. TheISR feature provides the ability to reconfigure the deviceswithout having design changes cause pinout or timingchanges. The Cypress ISR function is implemented through aJTAG-compliant serial interface. Data is shifted in and outthrough the TDI and TDO pins, respectively. Because of thesuperior routability and simple timing model of the Ultra37000devices, ISR allows users to change existing logic designswhile simultaneously fixing pinout assignments andmaintaining system performance. The entire family features JTAG for ISR and boundary scan,and is compatible with the PCI Local Bus specification,meeting the electrical and timing requirements. TheUltra37000 family features user programmable bus-holdcapabilities on all I/Os.

Ultra37000 5.0V DevicesThe Ultra37000 devices operate with a 5V supply and cansupport 5V or 3.3V I/O levels. VCCO connections provide thecapability of interfacing to either a 5V or 3.3V bus. Byconnecting the VCCO pins to 5V the user insures 5V TTL levelson the outputs. If VCCO is connected to 3.3V the output levelsmeet 3.3V JEDEC standard CMOS levels and are 5V tolerant.These devices require 5V ISR programming.

Ultra37000V 3.3V DevicesDevices operating with a 3.3V supply require 3.3V on all VCCOpins, reducing the device’s power consumption. Thesedevices support 3.3V JEDEC standard CMOS output levels,and are 5V-tolerant. These devices allow 3.3V ISRprogramming.

Note: 1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600Document #: 38-03007 Rev. *E Revised March 7, 2004


Selection Guide5.0V Selection Guide

General Information

Device Macrocells Dedicated Inputs I/O Pins Speed (tPD) Speed (fMAX)CY37032 32 5 32 6 200CY37064 64 5 32/64 6 200CY37128 128 5 64/128 6.5 167CY37192 192 5 120 7.5 154CY37256 256 5 128/160/192 7.5 154CY37384 384 5 160/192 10 118CY37512 512 5 160/192/264 10 118

Speed Bins

Device 200 167 154 143 125 100 83 66CY37032 X X XCY37064 X X XCY37128 X X XCY37192 X X XCY37256 X X XCY37384 X XCY37512 X X X

Device-Package Offering and I/O Count

Device44-

LeadTQFP

44-LeadPLCC

44-LeadCLCC

84-LeadPLCC

84-LeadCLCC

100-LeadTQFP

160-LeadTQFP

160-LeadCQFP

208-LeadPQFP

208-LeadCQFP

292-Lead

PBGA

388-Lead

PBGACY37032 37 37CY37064 37 37 37 69 69CY37128 69 69 69 133CY37192 125CY37256 133 133 165 197CY37384 165 197CY37512 165 165 197 269

3.3V Selection Guide

General InformationDevice Macrocells Dedicated Inputs I/O Pins Speed (tPD) Speed (fMAX)

CY37032V 32 5 32 8.5 143CY37064V 64 5 32/64 8.5 143CY37128V 128 5 64/80/128 10 125CY37192V 192 5 120 12 100CY37256V 256 5 128/160/192 12 100CY37384V 384 5 160/192 15 83CY37512V 512 5 160/192/264 15 83

Document #: 38-03007 Rev. *E of 64


Architecture Overview of Ultra37000 FamilyProgrammable Interconnect MatrixThe PIM consists of a completely global routing matrix forsignals from I/O pins and feedbacks from the logic blocks. ThePIM provides extremely robust interconnection to avoid fittingand density limitations. The inputs to the PIM consist of all I/O and dedicated input pinsand all macrocell feedbacks from within the logic blocks. Thenumber of PIM inputs increases with pin count and the numberof logic blocks. The outputs from the PIM are signals routed tothe appropriate logic blocks. Each logic block receives 36inputs from the PIM and their complements, allowing for 32-bitoperations to be implemented in a single pass through thedevice. The wide number of inputs to the logic block alsoimproves the routing capacity of the Ultra37000 family.An important feature of the PIM is its simple timing. The propa-gation delay through the PIM is accounted for in the timingspecifications for each device. There is no additional delay fortraveling through the PIM. In fact, all inputs travel through thePIM. As a result, there are no route-dependent timing param-eters on the Ultra37000 devices. The worst-case PIM delaysare incorporated in all appropriate Ultra37000 specifications. Routing signals through the PIM is completely invisible to theuser. All routing is accomplished by software—no hand routingis necessary. Warp® and third-party development packagesautomatically route designs for the Ultra37000 family in amatter of minutes. Finally, the rich routing resources of theUltra37000 family accommodate last minute logic changeswhile maintaining fixed pin assignments.

Logic BlockThe logic block is the basic building block of the Ultra37000architecture. It consists of a product term array, an intelligentproduct-term allocator, 16 macrocells, and a number of I/Ocells. The number of I/O cells varies depending on the deviceused. Refer to Figure 1 for the block diagram.

Product Term ArrayEach logic block features a 72 x 87 programmable productterm array. This array accepts 36 inputs from the PIM, whichoriginate from macrocell feedbacks and device pins. ActiveLOW and active HIGH versions of each of these inputs aregenerated to create the full 72-input field. The 87 productterms in the array can be created from any of the 72 inputs. Of the 87 product terms, 80 are for general-purpose use forthe 16 macrocells in the logic block. Four of the remainingseven product terms in the logic block are output enable (OE)product terms. Each of the OE product terms controls up toeight of the 16 macrocells and is selectable on an individualmacrocell basis. In other words, each I/O cell can selectbetween one of two OE product terms to control the outputbuffer. The first two of these four OE product terms areavailable to the upper half of the I/O macrocells in a logic block.The other two OE product terms are available to the lower halfof the I/O macrocells in a logic block. The next two product terms in each logic block are dedicatedasynchronous set and asynchronous reset product terms. Thefinal product term is the product term clock. The set, reset, OEand product term clock have polarity control to realize ORfunctions in a single pass through the array.

Speed Bins

Device 200 167 154 143 125 100 83 66CY37032V X XCY37064V X XCY37128V X XCY37192V X XCY37256V X XCY37384V X XCY37512V X X

Device-Package Offering and I/O Count

Device 44-

Lead

TQFP

44-

Lead

CLC

C48

-Le

adFB

GA

84-

Lead

CLC

C10

0-Le

adTQ

FP10

0-Le

adFB

GA

160-

Lead

TQFP

160-

Lead

CQ

FP20

8-Le

adPQ

FP20

8-Le

adC

QFP

292-

Lead

PBG

A25

6-Le

adFB

GA

388-

Lead

PBG

A40

0-Le

adFB

GA

CY37032V 37 37CY37064V 37 37 37 69 69CY37128V 69 69 85 133CY37192V 125CY37256V 133 133 165 197 197CY37384V 165 197CY37512V 165 165 197 269 269



Low-Power OptionEach logic block can operate in high-speed mode for criticalpath performance, or in low-power mode for power conser-vation. The logic block mode is set by the user on a logic blockby logic block basis.

Product Term AllocatorThrough the product term allocator, software automaticallydistributes product terms among the 16 macrocells in the logicblock as needed. A total of 80 product terms are available fromthe local product term array. The product term allocatorprovides two important capabilities without affecting perfor-mance: product term steering and product term sharing.

Product Term SteeringProduct term steering is the process of assigning productterms to macrocells as needed. For example, if one macrocellrequires ten product terms while another needs just three, theproduct term allocator will “steer” ten product terms to onemacrocell and three to the other. On Ultra37000 devices,product terms are steered on an individual basis. Any numberbetween 0 and 16 product terms can be steered to anymacrocell. Note that 0 product terms is useful in cases wherea particular macrocell is unused or used as an input register.

Product Term SharingProduct term sharing is the process of using the same productterm among multiple macrocells. For example, if more thanone output has one or more product terms in its equation thatare common to other outputs, those product terms are onlyprogrammed once. The Ultra37000 product term allocatorallows sharing across groups of four output macrocells in a

variable fashion. The software automatically takes advantageof this capability—the user does not have to intervene. Note that neither product term sharing nor product termsteering have any effect on the speed of the product. Allworst-case steering and sharing configurations have beenincorporated in the timing specifications for the Ultra37000devices.

Ultra37000 MacrocellWithin each logic block there are 16 macrocells. Macrocellscan either be I/O Macrocells, which include an I/O Cell whichis associated with an I/O pin, or buried Macrocells, which donot connect to an I/O. The combination of I/O Macrocells andburied Macrocells varies from device to device.

Buried MacrocellFigure 2 displays the architecture of buried macrocells. Theburied macrocell features a register that can be configured ascombinatorial, a D flip-flop, a T flip-flop, or a level-triggeredlatch.The register can be asynchronously set or asynchronouslyreset at the logic block level with the separate set and resetproduct terms. Each of these product terms features program-mable polarity. This allows the registers to be set or resetbased on an AND expression or an OR expression.Clocking of the register is very flexible. Four globalsynchronous clocks and a product term clock are available toclock the register. Furthermore, each clock features program-mable polarity so that registers can be triggered on falling aswell as rising edges (see the Clocking section). Clock polarityis chosen at the logic block level.

Figure 1. Logic Block with 50% Buried Macrocells

I/OCELL

0

PRODUCTTERM

ALLOCATOR

I/OCELL

14

MACRO-CELL

0

MACRO-CELL

1

MACRO-CELL

14

0−16

PRODUCTTERMS

72 x 87PRODUCT TERM

ARRAY

8036

8

16

TOPIM

FROMPIM

7

3 2

MACRO-CELL

15

2

to cells2, 4, 6 8, 10, 12

0−16

PRODUCTTERMS

0−16

PRODUCTTERMS

0−16

PRODUCTTERMS



The buried macrocell also supports input register capability.The buried macrocell can be configured to act as an inputregister (D-type or latch) whose input comes from the I/O pinassociated with the neighboring macrocell. The output of allburied macrocells is sent directly to the PIM regardless of itsconfiguration.

I/O MacrocellFigure 2 illustrates the architecture of the I/O macrocell. TheI/O macrocell supports the same functions as the buriedmacrocell with the addition of I/O capability. At the output of themacrocell, a polarity control mux is available to select activeLOW or active HIGH signals. This has the added advantageof allowing significant logic reduction to occur in many appli-cations. The Ultra37000 macrocell features a feedback path to the PIMseparate from the I/O pin input path. This means that if themacrocell is buried (fed back internally only), the associatedI/O pin can still be used as an input.

Bus Hold Capabilities on all I/OsBus-hold, which is an improved version of the popular internalpull-up resistor, is a weak latch connected to the pin that doesnot degrade the device’s performance. As a latch, bus-holdmaintains the last state of a pin when the pin is placed in ahigh-impedance state, thus reducing system noise inbus-interface applications. Bus-hold additionally allowsunused device pins to remain unconnected on the board,which is particularly useful during prototyping as designers canroute new signals to the device without cutting trace connec-tions to VCC or GND. For more information, see the applicationnote Understanding Bus-Hold—A Feature of Cypress CPLDs.

Programmable Slew Rate ControlEach output has a programmable configuration bit, which setsthe output slew rate to fast or slow. For designs concerned withmeeting FCC emissions standards the slow edge provides forlower system noise. For designs requiring very high perfor-mance the fast edge rate provides maximum system perfor-mance.

C2 C3

DECODE

C2 C3

DECODE

0123

O

C6 C5

“0” “1”

0

1O

D/T/L Q

R

P

0123

O

C0

0

1

O

C4

FEEDBACK TO PIM

FEEDBACK TO PIM

BLOCK RESET

0−16

TERMS

I/O MACROCELL

I/O CELL

FROM PTM

0

1

O

D/T/L Q

R

P

FROM PTM

1O

C7

FEEDBACK TO PIM

BURIED MACROCELL

0

ASYNCHRONOUS

PRODUCT

0−16

TERMSPRODUCT

C1

4

0123

Q

4

C24

C0 C1 C24

C25

C25

4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)1 ASYNCHRONOUS CLOCK(PTCLK)BLOCK PRESET

ASYNCHRONOUS

FAST

SLOW

C26

SLEW

01

01

01

01

OE0 OE1

Figure 2. I/O and Buried Macrocells



ClockingEach I/O and buried macrocell has access to four synchronousclocks (CLK0, CLK1, CLK2 and CLK3) as well as anasynchronous product term clock PTCLK. Each inputmacrocell has access to all four synchronous clocks.

Dedicated Inputs/ClocksFive pins on each member of the Ultra37000 family are desig-nated as input-only. There are two types of dedicated inputson Ultra37000 devices: input pins and input/clock pins.Figure 3 illustrates the architecture for input pins. Four inputoptions are available for the user: combinatorial, registered,double-registered, or latched. If a registered or latched optionis selected, any one of the input clocks can be selected forcontrol. Figure 4 illustrates the architecture for the input/clock pins.Like the input pins, input/clock pins can be combinatorial,registered, double-registered, or latched. In addition, thesepins feed the clocking structures throughout the device. Theclock path at the input has user-configurable polarity.

Product Term ClockingIn addition to the four synchronous clocks, the Ultra37000family also has a product term clock for asynchronousclocking. Each logic block has an independent product termclock which is available to all 16 macrocells. Each product termclock also supports user configurable polarity selection.

Timing ModelOne of the most important features of the Ultra37000 family isthe simplicity of its timing. All delays are worst case andsystem performance is unaffected by the features used.Figure 5 illustrates the true timing model for the 167-MHzdevices in high speed mode. For combinatorial paths, anyinput to any output incurs a 6.5-ns worst-case delay regardlessof the amount of logic used. For synchronous systems, theinput set-up time to the output macrocells for any input is 3.5ns and the clock to output time is also 4.0 ns. These measure-ments are for any output and synchronous clock, regardlessof the logic used. The Ultra37000 features:• No fanout delays• No expander delays• No dedicated vs. I/O pin delays• No additional delay through PIM• No penalty for using 0–16 product terms• No added delay for steering product terms• No added delay for sharing product terms• No routing delays• No output bypass delays

The simple timing model of the Ultra37000 family eliminatesunexpected performance penalties.

Figure 3. Input Macrocell

0123

O

C12 C13

TO PIM

DQ

DQ

D Q

LE

INPUT PIN

012 O

C10

FROM CLOCKPOLARITY MUXES

3

C11

Figure 4. Input/Clock Macrocell

0123

O

C10C11

TO PIMD

QD

Q

D Q

LE

INPUT/CLOCK PIN

012 O

FROM CLOCK

CLOCK PINS

0

1O

C12

TO CLOCK MUX ONALL INPUT MACROCELLS

TO CLOCK MUX IN EACH

3

0

1

CLOCK POLARITY MUX ONE PER LOGIC BLOCKFOR EACH CLOCK INPUTPOLARITY INPUT

LOGIC BLOCK

C8 C9

C13, C14, C15 OR C16

O



JTAG and PCI StandardsPCI Compliance5V operation of the Ultra37000 is fully compliant with the PCILocal Bus Specification published by the PCI Special InterestGroup. The 3.3V products meet all PCI requirements exceptfor the output 3.3V clamp, which is in direct conflict with 5Vtolerance. The Ultra37000 family’s simple and predictabletiming model ensures compliance with the PCI AC specifica-tions independent of the design.

IEEE 1149.1-compliant JTAG The Ultra37000 family has an IEEE 1149.1 JTAG interface forboth Boundary Scan and ISR.

Boundary ScanThe Ultra37000 family supports Bypass, Sample/Preload,Extest, Idcode, and Usercode boundary scan instructions. TheJTAG interface is shown in Figure 6.

In-System Reprogramming (ISR)In-System Reprogramming is the combination of the capabilityto program or reprogram a device on-board, and the ability tosupport design changes without changing the system timingor device pinout. This combination means design changesduring debug or field upgrades do not cause board respins.The Ultra37000 family implements ISR by providing a JTAGcompliant interface for on-board programming, robust routing

resources for pinout flexibility, and a simple timing model forconsistent system performance.

Development Software SupportWarpWarp is a state-of-the-art compiler and complete CPLD designtool. For design entry, Warp provides an IEEE-STD-1076/1164VHDL text editor, an IEEE-STD-1364 Verilog text editor, and agraphical finite state machine editor. It provides optimizedsynthesis and fitting by replacing basic circuits with onespre-optimized for the target device, by implementing logic inunused memory and by perfect communication between fittingand synthesis. To facilitate design and debugging, Warpprovides graphical timing simulation and analysis.

Warp Professional™Warp Professional contains several additional features. Itprovides an extra method of design entry with its graphicalblock diagram editor. It allows up to 5 ms timing simulationinstead of only 2 ms. It allows comparison of waveforms beforeand after design changes.

Warp Enterprise™Warp Enterprise provides even more features. It providesunlimited timing simulation and source-level behavioralsimulation as well as a debugger. It has the ability to generategraphical HDL blocks from HDL text. It can even generatetestbenches.Warp is available for PC and UNIX platforms. Some featuresare not available in the UNIX version. For further informationsee the Warp for PC, Warp for UNIX, Warp Professional andWarp Enterprise data sheets on Cypress’s web site(www.cypress.com).

Third-Party SoftwareAlthough Warp is a complete CPLD development tool on itsown, it interfaces with nearly every third party EDA tool. Allmajor third-party software vendors provide support for theUltra37000 family of devices. Refer to the third-party softwaredata sheet or contact your local sales office for a list ofcurrently supported third-party vendors.

ProgrammingThere are four programming options available for Ultra37000devices. The first method is to use a PC with the 37000UltraISR programming cable and software. With this method,the ISR pins of the Ultra37000 devices are routed to aconnector at the edge of the printed circuit board. The 37000UltraISR programming cable is then connected between theparallel port of the PC and this connector. A simple configu-ration file instructs the ISR software of the programmingoperations to be performed on each of the Ultra37000 devicesin the system. The ISR software then automatically completesall of the necessary data manipulations required to accomplishthe programming, reading, verifying, and other ISR functions.For more information on the Cypress ISR Interface, see theISR Programming Kit data sheet (CY3700i).The second method for programming Ultra37000 devices is onautomatic test equipment (ATE). This is accomplished througha file created by the ISR software. Check the Cypress websitefor the latest ISR software download information.

Figure 5. Timing Model for CY37128

Figure 6. JTAG Interface

COMBINATORIAL SIGNAL

REGISTERED SIGNAL

D,T,L O

CLOCK

INPUT

INPUT

OUTPUT

OUTPUT

tS = 3.5 ns tCO = 4.5 ns

tPD = 6.5 ns

Instruction Register

Boundary Scan

idcode

Usercode

ISR Prog.

Bypass Reg.

Data Registers

JTAGTAP

CONTROLLER

TDOTDI

TMS

TCK



The third programming option for Ultra37000 devices is toutilize the embedded controller or processor that alreadyexists in the system. The Ultra37000 ISR software assists inthis method by converting the device JEDEC maps into theISR serial stream that contains the ISR instruction informationand the addresses and data of locations to be programmed.The embedded controller then simply directs this ISR streamto the chain of Ultra37000 devices to complete the desiredreconfiguring or diagnostic operations. Contact your localsales office for information on availability of this option.

The fourth method for programming Ultra37000 devices is touse the same programmer that is currently being used toprogram FLASH370i devices.For all pinout, electrical, and timing requirements, refer todevice data sheets. For ISR cable and software specifications,refer to the UltraISR kit data sheet (CY3700i).

Third-Party ProgrammersAs with development software, Cypress support is available ona wide variety of third-party programmers. All major third-partyprogrammers (including BP Micro, Data I/O, and SMS) supportthe Ultra37000 family.



Logic Block Diagrams

CY37032/CY37032V

LOGICBLOCK

B

LOGICBLOCK

A

36

16

36

16

InputClock/Input

16 I/Os 16 I/OsI/O0−I/O15 I/O16−I/O31

4

44

1616

TDITCKTMS

TDOJTAG TapController1

PIM

JTAGEN

LOGICBLOCK

D

LOGICBLOCK

C

LOGICBLOCK

A

LOGICBLOCK

B

36

16

36

16

36

16

36

16

Input

Clock/Input

16 I/Os

16 I/Os

16 I/Os

16 I/Os

I/O0-I/O15

I/O16-I/O31

I/O48-I/O63

I/O32-I/O47

4

44

3232

TDI

TCK

TMS

TDOJTAG Tap

Controller

1

PIM

CY37064/CY37064V



Logic Block Diagrams (continued)

TDI

TCK

TMS

TDOJTAG Tap

ControllerCY37128/CY37128V

PIM

INPUTMACROCELL

CLOCKINPUTS

4 4

36

16 1636

LOGICBLOCK 36

16 1636

16 I/Os

36 36

36

16 16

36

16 16

64 64

41INPUT/CLOCKMACROCELLS

I/O0–I/O15A

INPUTS

LOGICBLOCK

C

LOGICBLOCK

B

LOGICBLOCK

D

LOGICBLOCK

H

LOGICBLOCK

G

LOGICBLOCK

F

LOGICBLOCK

E

I/O16–I/O31

I/O32–I/O47

I/O28–I/O63

I/O112–I/O127

I/O96–I/O111

I/O80–I/O95

I/O64–I/O79

16 I/Os

16 I/Os

16 I/Os

16 I/Os

16 I/Os

16 I/Os

16 I/Os

JTAGEN

LOGICBLOCK

H

LOGICBLOCK

L

LOGICBLOCK

I

LOGICBLOCK

J

LOGICBLOCK

K

LOGICBLOCK

A

LOGICBLOCK

B

LOGICBLOCK

C

LOGICBLOCK

D

LOGICBLOCK

E

LOGICBLOCK

G

LOGICBLOCK

F

36

1636

16

36

16

36

16

36

16

36

16

3616

36

16

36

16

36

16

36

16

36

16

PIM

InputClock/Input

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

10 I/Os

I/O0–I/O9

I/O10–I/O19

I/O20–I/O29

I/O30–I/O39

I/O40–I/O49

I/O50–I/O59

I/O110–I/O119

I/O100–I/O109

I/O90–I/O99

I/O80–I/O89

I/O70–I/O79

I/O60–I/O69

4

44

6060TDITCKTMS

TDOJTAG TapController

1

CY37192/CY37192V




CY37256/CY37256V

LOGICBLOCK

G

LOGICBLOCK

H

LOGICBLOCK

I

LOGICBLOCK

J

LOGICBLOCK

L

LOGICBLOCK

P

LOGICBLOCK

M

LOGICBLOCK

N

LOGICBLOCK

O

LOGICBLOCK

A

LOGICBLOCK

B

LOGICBLOCK

C

LOGICBLOCK

D

LOGICBLOCK

E

LOGICBLOCK

K

LOGICBLOCK

F

36

1636

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

3616

36

16

36

16

36

16

36

16

36

16

PIM

InputClock/Input

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

I/O0−I/O11

I/O12−I/O23

I/O24−I/O35

I/O36−I/O47

I/O48−I/O59

I/O60−I/O71

I/O72−I/O83

I/O84−I/O95

I/O180−I/O191

I/O168−I/O179

I/O156−I/O167

I/O144−I/O155

I/O132−I/O143

I/O120−I/O131

I/O108−I/O119

I/O96−I/O107

4

44

9696TDITCKTMS


1




CY37384/CY37384V

LOGICBLOCK

AH

LOGICBLOCK

AI

LOGICBLOCK

BD

LOGICBLOCK

BE

LOGICBLOCK

BG

LOGICBLOCK

BL

LOGICBLOCK

BI

LOGICBLOCK

BJ

LOGICBLOCK

BK

LOGICBLOCK

AA

LOGICBLOCK

AB

LOGICBLOCK

AC

LOGICBLOCK

AD

LOGICBLOCK

AF

LOGICBLOCK

BF

LOGICBLOCK

AG

36

1636

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

36

16

PIM

InputClock/Input

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

I/O0−I/O11

I/O12−I/O23

I/O24−I/O35

I/O48−I/O59

I/O60−I/O71

I/O72−I/O83

I/O168−I/O191

I/O156−I/O179

I/O144−I/O167

I/O120−I/O143

I/O108−I/O131

4

44

9696TDITCKTMS


1

LOGICBLOCK

AJ

LOGICBLOCK

BC1616

12 I/OsI/O96−I/O119

LOGICBLOCK

AK

LOGICBLOCK

BB1616

12 I/OsI/O84−I/O95

LOGICBLOCK

AL

LOGICBLOCK

BA1616

12 I/OsI/O96−I/O107

LOGICBLOCK

AE

LOGICBLOCK

BH1616

12 I/Os

12 I/Os

I/O36−I/O47

I/O132−I/O155

36

36

36

36

36

36

36

36




CY37512/CY37512V

LOGICBLOCK

AG

LOGICBLOCK

AH

LOGICBLOCK

BI

LOGICBLOCK

BJ

LOGICBLOCK

BL

LOGICBLOCK

BP

LOGICBLOCK

BM

LOGICBLOCK

BN

LOGICBLOCK

BO

LOGICBLOCK

AA

LOGICBLOCK

AB

LOGICBLOCK

AC

LOGICBLOCK

AD

LOGICBLOCK

AE

LOGICBLOCK

BK

LOGICBLOCK

AF

36

1636

16

36

16

36

16

36

16

36

16

36

16

3636

36

16

3616

36

16

36

16

36

16

36

16

36

16

Input Clock/ Input

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

12 I/Os

I/O0−I/O11

I/O12−I/O23

I/O24−I/O35

I/O36−I/O47

I/O48−I/O59

I/O60−I/O71

I/O72−I/O83

I/O84−I/O95

I/O252−I/O263

I/O240−I/O251

I/O228−I/O239

I/O216−I/O227

I/O204−I/O215

4

44

TDITCKTMS


1

PIM16

3636

16

LOGICBLOCK

AI

LOGICBLOCK

BH

12 I/OsI/O96−I/O107

16

3636

16

LOGICBLOCK

AJ

LOGICBLOCK

BG

12 I/Os

12 I/Os

I/O108−I/O119

I/O192−I/O20316

3636

16

LOGICBLOCK

AK

LOGICBLOCK

BF

12 I/OsI/O120−I/O131

16

3636

16

LOGICBLOCK

AL

LOGICBLOCK

BE

12 I/OsI/O180−I/O19116

3636

16

LOGICBLOCK

AM

LOGICBLOCK

BD

12 I/OsI/O168−I/O17916

3636

16

LOGICBLOCK

AN

LOGICBLOCK

BC

12 I/OsI/O156−I/O16716

3636

16

LOGICBLOCK

AO

LOGICBLOCK

BB

12 I/OsI/O144−I/O15516

3636

16

LOGICBLOCK

AP

LOGICBLOCK

BA

12 I/OsI/O132−I/O14316

132132

16



5.0V Device CharacteristicsMaximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°CAmbient Temperature withPower Applied.............................................–55°C to +125°CSupply Voltage to Ground Potential ............... –0.5V to +7.0V

DC Voltage Applied to Outputsin High-Z State................................................–0.5V to +7.0VDC Input Voltage ............................................–0.5V to +7.0VDC Program Voltage............................................. 4.5 to 5.5VCurrent into Outputs .................................................... 16 mAStatic Discharge Voltage........................................... > 2001V(per MIL-STD-883, Method 3015)Latch-up Current..................................................... > 200 mA

Operating Range[2]

Range Ambient Temperature[2] Junction Temperature Output Condition VCC VCCOCommercial 0°C to +70°C 0°C to +90°C 5V 5V ± 0.25V 5V ± 0.25V

3.3V 5V ± 0.25V 3.3V ± 0.3VIndustrial –40°C to +85°C –40°C to +105°C 5V 5V ± 0.5V 5V ± 0.5V

3.3V 5V ± 0.5V 3.3V ± 0.3VMilitary[3] –55°C to +125°C –55°C to +130°C 5V 5V ± 0.5V 5V ± 0.5V

3.3V 5V ± 0.5V 3.3V ± 0.3V

5.0V Device Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. UnitVOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)[4] 2.4 V

IOH = –2.0 mA (Mil)[4] 2.4 VVOHZ Output HIGH Voltage with

Output Disabled[5]VCC = Max. IOH = 0 µA (Com’l)[6] 4.2 V

IOH = 0 µA (Ind/Mil)[6] 4.5 VIOH = –100 µA (Com’l)[6] 3.6 VIOH = –150 µA (Ind/Mil)[6] 3.6 V

VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)[4] 0.5 VIOL = 12 mA (Mil)[4] 0.5 V

VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs[7] 2.0 VCCmax VVIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs[7] –0.5 0.8 VIIX Input Load Current VI = GND OR VCC, Bus-Hold Disabled –10 10 µAIOZ Output Leakage Current VO = GND or VCC, Output Disabled, Bus-Hold Disabled –50 50 µAIOS Output Short Circuit Current[5, 8] VCC = Max., VOUT = 0.5V –30 –160 mAIBHL Input Bus-Hold LOW

Sustaining CurrentVCC = Min., VIL = 0.8V +75 µA

IBHH Input Bus-Hold HIGH Sustaining Current

VCC = Min., VIH = 2.0V –75 µA

IBHLO Input Bus-Hold LOW Overdrive Current

VCC = Max. +500 µA

IBHHO Input Bus-Hold HIGH Overdrive Current

VCC = Max. –500 µA

Notes: 2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the

Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”3. TA is the “Instant On” case temperature.4. IOH = –2 mA, IOL = 2 mA for TDO.5. Tested initially and after any design or process changes that may affect these parameters.6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled

during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test

problems caused by tester ground degradation.



3.3V Device CharacteristicsMaximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature .................................–65°C to +150°CAmbient Temperature withPower Applied.............................................–55°C to +125°CSupply Voltage to Ground Potential ............... –0.5V to +4.6V

DC Voltage Applied to Outputsin High-Z State................................................–0.5V to +7.0VDC Input Voltage ............................................–0.5V to +7.0VDC Program Voltage............................................. 3.0 to 3.6VCurrent into Outputs ...................................................... 8 mAStatic Discharge Voltage........................................... > 2001V(per MIL-STD-883, Method 3015)Latch-up Current..................................................... > 200 mA

Inductance[5]

Parameter Description Test Conditions44-LeadTQFP

44-LeadPLCC

44-LeadCLCC

84-LeadPLCC

84-LeadCLCC

100-LeadTQFP

160-LeadTQFP

208-LeadPQFP Unit

L Maximum Pin Inductance

VIN = 5.0V at f = 1 MHz

2 5 2 8 5 8 9 11 nH

Capacitance[5]

Parameter Description Test Conditions Max. UnitCI/O Input/Output Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 10 pFCCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 12 pFCDP Dual-Function Pins[9] VIN = 5.0V at f = 1 MHz at TA = 25°C 16 pF

Endurance Characteristics[5]

Parameter Description Test Conditions Min. Typ. UnitN Minimum Reprogramming Cycles Normal Programming Conditions[2] 1,000 10,000 Cycles

Operating Range[2]

Range Ambient Temperature[2] Junction Temperature VCC[10]

Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.3VIndustrial –40°C to +85°C –40°C to +105°C 3.3V ± 0.3VMilitary[3] –55°C to +125°C –55°C to +130°C 3.3V ± 0.3V

3.3V Device Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. UnitVOH Output HIGH Voltage VCC = Min. IOH = –4 mA (Com’l)[4] 2.4 V

IOH = –3 mA (Mil)[4]

VOL Output LOW Voltage VCC = Min. IOL = 8 mA (Com’l)[4] 0.5 VIOL = 6 mA (Mil)[4]

VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs[7]

2.0 5.5 V

VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs[7]

–0.5 0.8 V

IIX Input Load Current VI = GND OR VCC, Bus-Hold Disabled –10 10 µAIOZ Output Leakage Current VO = GND or VCC, Output Disabled,

Bus-Hold Disabled–50 50 µA

IOS Output Short Circuit Current[5, 8] VCC = Max., VOUT = 0.5V –30 –160 mAIBHL Input Bus-Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 µAIBHH Input Bus-Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V –75 µAIBHLO Input Bus-Hold LOW Overdrive Current VCC = Max. +500 µAIBHHO Input Bus-Hold HIGH Overdrive Current VCC = Max. –500 µANotes: 9. Dual pins are I/O with JTAG pins.10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: VCC is 3.3V± 0.16V.



Inductance[5]

Parameter Description Test Conditions

44- LeadTQFP

44- LeadPLCC

44- LeadCLCC

84- LeadPLCC

84- LeadCLCC

100- LeadTQFP

160- LeadTQFP

208- LeadPQFP Unit

L Maximum Pin Inductance

VIN = 3.3V at f = 1 MHz

2 5 2 8 5 8 9 11 nH

Capacitance[5]

Parameter Description Test Conditions Max. UnitCI/O Input/Output Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 8 pFCCLK Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 12 pFCDP Dual Functional Pins[9] VIN = 3.3V at f = 1 MHz at TA = 25°C 16 pF

Endurance Characteristics[5]

Parameter Description Test Conditions Min. Typ. UnitN Minimum Reprogramming Cycles Normal Programming Conditions[2] 1,000 10,000 Cycles

AC Characteristics5.0V AC Test Loads and Waveforms

3.3V AC Test Loads and Waveforms

90%10%

3.0V

GND

90%10%

ALL INPUT PULSES5V

OUTPUT

35 pF

INCLUDINGJIG ANDSCOPE

5V

OUTPUT

5 pF

INCLUDINGJIG ANDSCOPE(a) (b)

<2 ns

OUTPUT

238Ω (COM'L)319Ω (MIL)



Equivalent to: THÉVENIN EQUIVALENT

2.08V (COM'L)2.13V (MIL)



<2 ns

(c)

5 OR 35 pF

90%10%

3.0V

GND

90%10%

ALL INPUT PULSES3.3V

OUTPUT

35 pFINCLUDINGJIG ANDSCOPE

3.3V

OUTPUT

5 pFINCLUDINGJIG ANDSCOPE(a) (b)

<2 ns

OUTPUT



Equivalent to: THÉVENIN EQUIVALENT

1.77V (COM'L)1.77V (MIL)



<2 ns

(c)

270Ω (MIL)158Ω (COM’L)

5 OR 35 pF



Parameter[11] VX Output Waveform—Measurement LeveltER(–) 1.5V

tER(+) 2.6V

tEA(+) 1.5V

tEA(–) Vthe

(d) Test Waveforms

VOHVX0.5V

VOLVX0.5V

VXVOH0.5V

VXVOL0.5V

Switching Characteristics Over the Operating Range [12]

Parameter Description UnitCombinatorial Mode ParameterstPD

[13, 14, 15] Input to Combinatorial Output nstPDL

[13, 14, 15] Input to Output Through Transparent Input or Output Latch nstPDLL

[13, 14, 15] Input to Output Through Transparent Input and Output Latches nstEA

[13, 14, 15] Input to Output Enable nstER

[11, 13] Input to Output Disable nsInput Register ParameterstWL Clock or Latch Enable Input LOW Time[8] nstWH Clock or Latch Enable Input HIGH Time[8] nstIS Input Register or Latch Set-up Time nstIH Input Register or Latch Hold Time nstICO

[13, 14, 15] Input Register Clock or Latch Enable to Combinatorial Output nstICOL

[13, 14, 15] Input Register Clock or Latch Enable to Output Through Transparent Output Latch nsSynchronous Clocking ParameterstCO

[14, 15] Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output nstS[13] Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable nstH Register or Latch Data Hold Time nstCO2

[13, 14, 15] Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output Delay (Through Logic Array)

ns

tSCS[13] Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous

Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)ns

tSL[13] Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0

CLK1, CLK2, or CLK3) or Latch Enablens

tHL Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable

ns

Notes: 11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.13. Logic Blocks operating in Low-Power Mode, add tLP to this spec.14. Outputs using Slow Output Slew Rate, add tSLEW to this spec.15. When VCCO = 3.3V, add t3.3IO to this spec.



Product Term Clocking ParameterstCOPT

[13, 14, 15] Product Term Clock or Latch Enable (PTCLK) to Output nstSPT Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) nstHPT Register or Latch Data Hold Time nstISPT

[13] Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch Enable (PTCLK)

ns

tIHPT Buried Register Used as an Input Register or Latch Data Hold Time nstCO2PT

[13, 14, 15] Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) nsPipelined Mode ParameterstICS

[13] Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3)

ns

Operating Frequency ParametersfMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[5] MHzfMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),

1/(tS + tH), or 1/tCO)[5]MHz

fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[5] MHzfMAX4 Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),

or 1/tSCS)[5]MHz

Reset/Preset ParameterstRW Asynchronous Reset Width[5] nstRR

[13] Asynchronous Reset Recovery Time[5] nstRO

[13, 14, 15] Asynchronous Reset to Output nstPW Asynchronous Preset Width[5] nstPR

[13] Asynchronous Preset Recovery Time[5] nstPO

[13, 14, 15] Asynchronous Preset to Output nsUser Option ParameterstLP Low Power Adder nstSLEW Slow Output Slew Rate Adder nst3.3IO 3.3V I/O Mode Timing Adder[5] nsJTAG Timing Parameters

tS JTAG Set-up Time from TDI and TMS to TCK[5] nstH JTAG Hold Time on TDI and TMS[5] nstCO JTAG Falling Edge of TCK to TDO[5] nsfJTAG Maximum JTAG Tap Controller Frequency[5] ns

Switching Characteristics Over the Operating Range (continued)[12]

Parameter Description Unit



Switching Characteristics Over the Operating Range [12]

Parameter

200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz

UnitMin

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Combinatorial Mode ParameterstPD

[13, 14, 15] 6 6.5 7.5 8.5 10 12 15 20 nstPDL

[13, 14, 15] 11 12.5 14.5 16 16.5 17 19 22 nstPDLL

[13, 14, 15] 12 13.5 15.5 17 17.5 18 20 24 nstEA

[13, 14, 15] 8 8.5 11 13 14 16 19 24 nstER

[11, 13] 8 8.5 11 13 14 16 19 24 nsInput Register ParameterstWL 2.5 2.5 2.5 2.5 3 3 4 5 nstWH 2.5 2.5 2.5 2.5 3 3 4 5 nstIS 2 2 2 2 2 2.5 3 4 nstIH 2 2 2 2 2 2.5 3 4 nstICO

[13, 14, 15] 11 11 11 12.5 12.5 16 19 24 nstICOL

[13, 14, 15] 12 12 12 14 16 18 21 26 nsSynchronous Clocking ParameterstCO

[14, 15] 4 4 4.5 6 6.5[16] 6.5[17] 8[18] 10 nstS[13] 4 4 5 5 5.5[16] 6[17] 8[18] 10 nstH 0 0 0 0 0 0 0 0 nstCO2

[13, 14, 15] 9.5 10 11 12 14 16 19 24 nstSCS

[13] 5 6 6.5 7 8[16] 10 12 15 nstSL

[13] 7.5 7.5 8.5 9 10 12 15 15 nstHL 0 0 0 0 0 0 0 0 nsProduct Term Clocking ParameterstCOPT

[13, 14, 15] 7 10 10 13 13 13 15 20 nstSPT 2.5 2.5 2.5 3 5 5.5 6 7 nstHPT 2.5 2.5 2.5 3 5 5.5 6 7 nstISPT

[13] 0 0 0 0 0 0 0 0 nstIHPT 6 6.5 6.5 7.5 9 11 14 19 nstCO2PT

[13, 14, 15]

12 14 15 19 19 21 24 30 ns

Pipelined Mode ParameterstICS

[13] 5 6 6 7 8[16] 10 12 15 nsOperating Frequency ParametersfMAX1 200 167 154 143 125[16] 100 83 66 MHzfMAX2 200 200 200 167 154 153[17] 125[18] 100 MHzfMAX3 125 125 105 91 83 80[17] 62.5 50 MHzfMAX4 167 167 154 125 118 100 83 66 MHzReset/Preset ParameterstRW 8 8 8 8 10 12 15 20 nstRR

[13] 10 10 10 10 12 14 17 22 nsNotes: 16. The following values correspond to the CY37512 and CY37384 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz.17. The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz; and

for the CY37512 devices: tS = 7 ns.18. The following values correspond to the CY37512V and CY37384V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz.



tRO[13, 14, 15] 12 13 13 14 15 18 21 26 ns

tPW 8 8 8 8 10 12 15 20 nstPR

[13] 10 10 10 10 12 14 17 22 nstPO

[13, 14, 15] 12 13 13 14 15 18 21 26 nsUser Option ParameterstLP 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 nstSLEW 3 3 3 3 3 3 3 3 nst3.3IO

[19] 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns

JTAG Timing ParameterstS JTAG 0 0 0 0 0 0 0 0 nstH JTAG 20 20 20 20 20 20 20 20 nstCO JTAG 20 20 20 20 20 20 20 20 nsfJTAG 20 20 20 20 20 20 20 20 MHz

Switching Characteristics Over the Operating Range (continued)[12]

Parameter

200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz

UnitMin

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Min

.

Max

.

Switching WaveformsCombinatorial Output

Registered Output with Synchronous Clocking

Note: 19. Only applicable to the 5V devices.

tPD

INPUT

COMBINATORIALOUTPUT

tS

INPUT

SYNCHRONOUS

tCO

REGISTEREDOUTPUT

tH

SYNCHRONOUS

tWLtWH

tCO2

REGISTEREDOUTPUT

CLOCK

CLOCK



Registered Output with Product Term Clocking Input Going Through the Array

Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register

Latched Output

Switching Waveforms (continued)

tSPT

INPUT

PRODUCT TERM

tCOPT

REGISTEREDOUTPUT

tHPT

CLOCK

tISPT

INPUT

PRODUCT TERM

tCO2PT

REGISTEREDOUTPUT

tIHPT

CLOCK

tSL

INPUT

LATCH ENABLE

tCO

LATCHEDOUTPUT

tHL

tPDL



Registered Input

Clock to Clock

Latched Input


tIS

REGISTEREDINPUT

INPUT REGISTERCLOCK

tICO

COMBINATORIALOUTPUT

tIH

CLOCK

tWLtWH

INPUT REGISTERCLOCK

OUTPUTREGISTER CLOCK

tSCStICS

tIS

LATCHED INPUT

LATCH ENABLE

tICO

COMBINATORIALOUTPUT

tIH

tPDL

tWLtWH

LATCH ENABLE



Latched Input and Output

Asynchronous Reset

Asynchronous Preset

Output Enable/Disable


tICS

LATCHED INPUT

OUTPUT LATCHENABLE

LATCHEDOUTPUT

tPDLL

LATCH ENABLE

tWLtWH

tICOL

INPUT LATCHENABLE

tSLtHL

INPUT

tRO

REGISTEREDOUTPUT

CLOCK

tRR

tRW

INPUT

tPO

REGISTEREDOUTPUT

CLOCK

tPR

tPW

INPUT

tER

OUTPUTS

tEA



Power ConsumptionTypical 5.0V Power ConsumptionCY37032

CY37064

0

10

20

30

40

50

60

0 50 100 150 200 250

Frequency (M H z)

Icc

(mA

)

H igh S peed

Low P ow er

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.VCC = 5.0V, TA = Room Temperature


0

10

20

30

40

50

60

70

80

90

0 20 40 60 80 100 120 140 160 180

Frequency (M H z)

Icc

(mA

)

Low P ower

H igh S peed



CY37128

CY37192

Typical 5.0V Power Consumption (continued)

0

20

40

60

80

100

120

140

160

0 20 40 60 80 100 120 140 160 180

Frequency (M H z)

Icc

(mA

) Low P ow er

H igh S peed


0

50

100

150

200

250

300

0 20 40 60 80 100 120 140 160 180

Frequency (M H z)

Icc

(mA

)

Low P ow er

H igh S peed




CY37256

CY37384


0

50

100

150

200

250

300

0 20 40 60 80 100 120 140 160 180

Frequency (M H z)

Icc

(mA

)

Low P ow er

H igh S peed


0

50

100

150

200

250

300

350

400

450

500

0 20 40 60 80 100 120 140 160

Frequency (M Hz)

Icc

(mA

)

Low Power

H igh Speed




CY37512Typical 5.0V Power Consumption (continued)

0

100

200

300

400

500

600

0 20 40 60 80 100 120 140 160

Frequency (M H z)

Icc

(mA

)

Low P ow er

H igh S peed


Typical 3.3V Power ConsumptionCY37032V

0

5

10

15

20

25

30

0 20 40 60 80 100 120 140 160

Frequency (M Hz)

Icc

(mA

)

Low Power

High Speed




CY37064V

CY37128V


0

5

10

15

20

25

30

35

40

45

0 20 40 60 80 100 120 140

Frequency (M Hz)

Icc

(mA

)

Low Power

H igh Speed


0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0

F re q u e n c y (M H z)

Icc

(mA

)

L o w P o w e r

H ig h S p e e d




CY37192V

CY37256V


0

2 0

4 0

6 0

8 0

1 0 0

1 2 0

0 2 0 4 0 6 0 8 0 1 0 0 1 2 0

F re q u e n c y (M H z )

Icc

(mA

)

L o w P o w e r

H ig h S p e e d


0

2 0

4 0

6 0

8 0

1 0 0

1 2 0

1 4 0

0 2 0 4 0 6 0 8 0 1 0 0 1 2 0


Icc

(mA

)

L o w P o w e r

H ig h S p e e d




CY37384V

CY37512V


0

2 0

4 0

6 0

8 0

1 0 0

1 2 0

1 4 0

1 6 0

1 8 0

2 0 0

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0


Icc

(mA

)

L o w P o w e r

H ig h S p e e d


0

5 0

1 0 0

1 5 0

2 0 0

2 5 0

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0

F r e q u e n c y (M H z )

Icc

(mA

)

L o w P o w e r

H ig h S p e e d




Pin Configurations[20]

44-pin TQFP (A44)Top View

I/O2

GN

DV C

CO

I/O3

I/O4

I/O1

I/O0

I/O29

I/O30

I/O31

I/O28

I/O27/TDII/O26I/O25I/O24CLK1/I4GNDI3CLK3/I2I/O23I/O22I/O21

GN

D

I/O20

V CC

I/O18

I/O17

I/O16

I/O15

I/O14

I/O12

I/O5/TCKI/O6I/O7

CLK2/I0

GNDCLK0/I1

I/O8I/O9

I/O10I/O11

89

7

1011

34

2

56

1

18 19 20 222113 14 15 171612

313029

3233

262524

2728

23

44 43 42 4041 39 38 37 3536 34

I/O13

/TM

S

I/O19

/TD

O

JTAGEN

44-pin PLCC (J67) / CLCC (Y67)Top View

I/O27/TDII/O26I/O25I/O24CLK1/I4GNDI3CLK3/I2I/O23I/O22I/O21

I/O5/TCKI/O6I/O7

CLK2/I0JTAGEN

GNDCLK0/I1

I/O8I/O9

I/O10I/O11

GN

D

I/O20

I/O2

GN

DV C

CO

V CC

I/O3

I/O4

I/O1

I/O0

I/O29

I/O30

I/O31

I/O28

I/O19

I/O18

I/O17

I/O16

I/O15

I/O14

I/O13

I/O12

6 5 34 2

89

7

1011

44

18

1516

141312

17 19 20 2221 23 24 2726 2825

313029

323334

39

3738

3635

43 42 4041

/TM

S

/TD

O

1



Note: 20. For 3.3V versions (Ultra37000V), VCCO = VCC.

Note: 21. This pin is a N/C, but Cypress recommends that you connect it to VCC to ensure future compatibility.

Pin Configurations[20] (continued)

48-ball Fine-Pitch BGA (BA50)Top View

1 2 3 4 5 6 7 8

A I/O5 TCK

VCC I/O3 I/O1 I/O31 I/O30 VCC I/O27 TDI

B VCC I/O4 I/O2 I/O0 I/O29 I/O28 I/O26 CLK1/ I4

C CLK2/ I0 I/O7 I/O6 GND GND I/O25 I/O24 I3

D JTAGEN I/O8 I/O9 GND GND I/O22 I/O23 CLK3/ I2

E CLK0/ I1 I/O12 I/O11 I/O10 I/O16 I/O20 I/O21 VCC

F I/O13 TMS

VCC I/O14 I/O15 I/O17 I/O18 VCC I/O19 TDO

I/O

I/O14

I/O15 I/O 48

Top View84-lead PLCC (J83) / CLCC (Y84)

9 8 67 5

13

14

12

11

4948

58

59

60

23

24

26

25

27

15

16

4746

4 3

28

33

20

21

19

18

17

22

34 3736 38 4241 4340

66

65

63

64

62

61

67

68

69

74

72

73

71

70

84 8182 80 79

GND

I/O GN

D

I/O I/OI/O I/O I/O I/O I/OGN

D

I/O 55

I/O 54 /TDI

I/O 53

I/O 52

I/O 51

GND

I/O 49

CLK3/I 4

VCCO

CLK2/I 3

I/O 45

I/O 44

GN

D

I/O

I/O 8

I/O 9

I/O10 /TCK

I/O11

I/O12

I/O13

CLK0/I 0

VCCO

CLK1/I 1

I/O16

I/O17

I/O18

I/O19

I/O20

53525150

30

29

31

32

I/O I/O I/O I/O

54

55

56

57 I/O 43

I/O 42

I/O 41

I/O 40

7778 76 75

I/O21

I/O22

I/O23

GND

I/O

I/O 50

I/O 47

I/O 46

GND

24I/O

25

/TM

S

I/O27

I/O28

I/O29

I/O30

I/O31

VC

CO

VC

C I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

GN

D

I 2

7 6 5 4 3 2 1

VC

CO

I/O0

V CC 63

I/O62 61 60 59 58 57 56

JTA

GEN

I/O26

/TD

O10

35 39 44 45

832 1

[21]




Top View100-lead TQFP (A100)

100 9798 96

2

3

1

4241

59

60

61

12

13

15

14

16

4

5

4039

95 94

17

26

9

10

8

7

6

11

27 28 3029 31 32 3534 36 3833

67

66

64

65

6362

68

6970

75

73

74

72

71

89 88 8687 8593 92 84TDI

NC

VCCO

I/O 55

I/O 54

I/O 53

I/O 52

CLK 3 /I 4

I/O 50

I/O 48

GND

NC

I/O47

I/O 46

I/O 49

GN

D

TMS

TCKGND

I/O 8

I/O 9

I/O10

I/O11

I/O15

VCCO

GNDCLK1 /I 1

I/O16

I/O17

CLK0 /I 0

9091

I/O 51

VCCO

CLK 2 /I 3

I/O14

N/C

I/O12

I/O13

I/O 45

I/O 44I/O 43

I/O 42

I/O 41

I/O 40

GND

NC

GN

D

NC

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23VCCO

NC

18

19

20

21

22

23

24

25

83 82 81 80 79 78 77 76

58

57

56

55

54

53

52

51

43 44 45 46 48 49 50

GN

D

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

VC

CO

VC

C I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39I 2

NC

V CC

O

TDO

I/OI/O GN

D

I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/OI/O

7 6 5 4 3 2 1

VC

CO

I/O0

VC

C

NC

63I/O

62 61 60 59 58 57 56

VC

CO

N/C

99

37 47

[21]



Pin Configurations[20] (continued)100-ball Fine-Pitch BGA (BB100) for CY37064V

Top View

100-ball Fine-Pitch BGA (BB100) for CY37128VTop View

1 2 3 4 5 6 7 8 9 10

A NC NC I/O7 I/O5 I/O2 I/O62 I/O60 I/O58 I/O57 I/O56

B I/O9 I/O8 I/O6 I/O4 I/O1 I/O63 VCC I/O59 I/O55 NC

C I/O10 TCK VCC I/O3 NC NC I/O61 VCC TDI I/O54

D I/O11 NC I/O12 I/O13 I/O0 NC I/O51 I/O52 CLK3/ I4

I/O53

E I/O14 CLK0/ I0

I/O15 NC GND GND I/O48 I/O49 CLK2/ I3

I/O50

F I/O17 NC NC I/O16 GND GND NC NC I2 I/O47

G I/O22 CLK1/ I1

I/O21 I/O19 I/O18 I/O46 I/O45 I/O44 NC I/O43

H I/O23 TMS VCC I/O20 NC I/O32 I/O42 VCC TDO I/O41

J NC I/O26 I/O28 NC I/O31 I/O33 I/O35 I/O37 I/O39 I/O40

K I/O24 I/O25 I/O27 I/O29 I/O30 I/O34 I/O36 I/O38 NC NC

1 2 3 4 5 6 7 8 9 10

A NC I/O9 I/O8 I/O6 I/O3 I/O76 I/O74 I/O72 I/O71 I/O70

B I/O11 I/O10 I/O7 I/O5 I/O2 I/O77 VCC I/O73 I/O68 I/O69

C I/O12 I/O13TCK

VCC I/O4 I/O1 I/O78 I/O75 VCC I/O67TDI

I/O66

D I/O14 NC I/O15 I/O16 I/O0 I/O79 I/O63 I/O64 CLK3/ I4

I/O65

E I/O17 CLK0/ I0

I/O18 I/O19 GND GND I/O60 I/O61 CLK2/ I3

I/O62

F I/O22 JTAGEN

I/O21 I/O20 GND GND I/O59 I/O58 I2 I/O57

G I/O27 CLK1/ I1

I/O26 I/O24 I/O23 I/O56 I/O55 I/O54 NC I/O53

H I/O28 I/O33TMS

VCC I/O25 I/O39 I/O40 I/O52 VCC I/O47TDO

I/O51

J I/O29 I/O32 I/O35 VCC I/O38 I/O41 I/O43 I/O45 I/O48 I/O50

K I/O30 I/O31 I/O34 I/O36 I/O37 I/O42 I/O44 I/O46 I/O49 NC




I/O77

124

123

122

121

120119118117116115114113112111110109108107106105104103102101100

999897969594939291908988878685

43 44

160

45

159

46

158

47

157

48

156

49

155

50

154

51

153

52

152

53

151

54

150

55

149

56

148

57

147

58

146

59

145

60

144

61

143

62

142

63

141

64 65 66 67 68

140

69

139

70

138

71

137

72

136

73

135

74

134

75

133

76

132

77

131

78

130

79

129

80

128

81

127

82

126

160-Lead TQFP (A160) / CQFP (U162)

125

8483

42

GNDI/O16I/O17

I/O18I/O19

I/O20/TCKI/O21I/O22I/O23

I/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31



GND

CLK0/I0VCCOGND

CLK1/I1

GND

GN

D

GN

D

GN

D

GN

D

VCCO

I/O48

I/O49

I/O50

I/O51

I/O53

I/O54

I/O55

I/O56

I/O57

I/O58

I/O59

I/O60

I/O61

I/O62

I/O63 I 2

VC

CO

VC

CI/O

64I/O

65I/O

66I/O

67I/O

68I/O

69I/O

70I/O

71

I/O72

I/O73

I/O74

I/O75

I/O78

I/O79

VC

CO

GNDI/O80

I/O81

I/O82

I/O83

I/O84

I/O85

I/O86

I/O87

GNDI/O88

I/O89

I/O90

I/O91

I/O92

I/O93

I/O94

I/O95

I/O96

I/O97

I/O98

I/O99

I/O100

I/O101

I/O102

I/O103

GND

GND

CLK2/I3VCCO

CLK3/I4

I/O104

I/O105

I/O106

I/O107

I/O108/TDII/O109

I/O110

I/O111

VCCOG

ND

GN

DV

CC

GN

D

I/O11

2G

ND

VC

CO

VC

CO

I/O11

3

I/O11

4

I/O11

5

I/O11

6

I/O11

7

I/O11

8

I/O11

9

I/O12

0

I/O12

1

I/O12

2

I/O12

3

I/O12

4

I/O12

5

I/O12

6

I/O12

7

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

JTA

GEN

I/O52

/TM

S

I/O76

/TD

O

23456789

10111213141516171819202122232425262728293031323334353637383940

1

41

for CY37128(V) and CY37256(V)Top View




I/O72

124

123

122

121

120119118117116115114113112111110109108107106105104103102101100

999897969594939291908988878685

43 44

160

45

159

46

158

47

157

48

156

49

155

50

154

51

153

52

152

53

151

54

150

55

149

56

148

57

147

58

146

59

145

60

144

61

143

62

142

63

141

64 65 66 67 68

140

69

139

70

138

71

137

72

136

73

135

74

134

75

133

76

132

77

131

78

130

79

129

80

128

81

127

82

126

160-Lead TQFP (A160) for CY37192(V)

125

8483

42

GNDNC

I/O16

I/O17I/O18TCKI/O19I/O20I/O21




GND

CLK0/I0VCCOGND

CLK1/I1

GND

GN

D

GN

D

GN

D

GN

D

VCCO

NC

I/O46

I/O47

I/O48

I/O49

I/O50

I/O51

I/O52

I/O53

I/O54

I/O55

I/O56

I/O57

I/O58

I/O59 I 2

VC

CO

VC

CI/O

60I/O

61I/O

62I/O

63I/O

64I/O

65I/O

66I/O

67

I/O68

I/O69

I/O70

I/O71

I/O73

I/O74

VC

CO

GNDNCI/O75

I/O76

I/O77

I/O78

I/O79

I/O80

I/O81

GNDI/O82

I/O83

I/O84

I/O85

I/O86

I/O87

I/O88

I/O89

I/O90

I/O91

I/O92

I/O93

I/O94

I/O95

I/O96

I/O97

GND

GND

CLK2/I3VCCO

CLK3/I4

I/O98

I/O99

I/O100

I/O101

TDII/O102

I/O103

I/O104

VCCOG

ND

GN

DV

CC

GN

D

NC

GN

D

VC

CO

VC

CO

I/O10

5

I/O10

6

I/O10

7

I/O10

8

I/O10

9

I/O11

0

I/O11

1

I/O11

2

I/O11

3

I/O11

4

I/O11

5

I/O11

6

I/O11

7

I/O11

8

I/O11

9

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

NC

TMS

TDO

23456789

10111213141516171819202122232425262728293031323334353637383940

1

41

Top View




I/O15

2

I/O15

4I/O

153

2345678910111213141516171819202122232425262728293031323334353637383940

1

414243444546474849505152

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

208

167

166

165

164

163

162

161

160

159

158

157

54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 9153 92 93 94 95 96 97 98 99 100

101

102

103

154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116

155

115114113112111110109108107106105

156

104

207

208-Lead PQFP (N208) / CQFP (U208) Top View

I/O139I/O138I/O137I/O136I/O135TDII/O134I/O133I/O132I/O131I/O130GNDI/O129I/O128I/O127I/O126I/O125I/O124I/O123I/O122I/O121I/O120CLK3/I4VCCGNDVCCOGNDCLK2/I3I/O119I/O118I/O117I/O116I/O115NCI/O114I/O113I/O112I/O111I/O110

VCCO

GNDI/O109I/O108I/O107I/O106I/O105I/O104I/O103I/O102I/O101I/O100GND

I/O61

I/O62

I/O63

I/O64

TMS

I/O65

I/O66

I/O67

I/O68

I/O69

GN

DI/O

70I/O

71I/O

72I/O

73I/O

74 NC

I/O75

I/O76

I/O77

I/O78

I/O79 I 2

VC

C0

GN

DV

CC

I/O80

I/O81

I/O82

I/O83

I/O84

I/O85

I/O86

I/O87

I/O88

I/O89

GN

DI/O

90I/O

91

GN

D

I/O92

I/O93

I/O94

GN

DTD

OI/O

95I/O

96I/O

97I/O

98I/O

99V

CC

0

I/O60

I/O21I/O22I/O23I/O24TCKI/O25I/O26I/O27I/O28I/O29GNDI/O30I/O31I/O32I/O33I/O34

NCI/O35I/O36I/O37I/O38I/O39

CLK0/I0VCCOGND

NCCLK1/I1

I/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O47I/O48I/O49GNDI/O50

I/O20

I/O51I/O52I/O53I/O54

NCI/O55I/O56I/O57I/O58I/O59VCC0

GND

VC

C0

I/O19

I/O18

I/O17

I/O16

I/O15

NC

I/O14

I/O13

I/O12

I/O11

I/O10

GN

DI/O

9I/O

8I/O

7I/O

6I/O

5I/O

4I/O

3I/O

2I/O

1I/O

0V

CC

0G

ND

VC

CN

CI/O

159

I/O15

8I/O

157

I/O15

6I/O

155

NC

I/O15

1I/O

150

VC

C

GN

DI/O

149

I/O14

8I/O

147

I/O14

6I/O

145

I/O14

4I/O

143

I/O14

2I/O

141

I/O14

0N

CG

ND




292-Ball PBGA (BG292)Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A GND I/O21 NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 A

B I/O23 I/O20 I/O19 I/O18 I/O15 I/O11 I/O8 I/O5 I/O1 I/O191 I/O187 I/O185 I/O181 NC NC I/O174 I/O171 I/O170 NC I/O166 B

C NC NC I/O22 NC I/O17 I/O14 I/O10 I/O6 I/O2 NC I/O188 I/O184 I/O180 I/O179 I/O176 I/O173 I/O172 I/O167 I/O165 I/O162 C

D I/O24 NC NC GND NC VCCO I/O13 GND I/O3 NC VCC I/O183 GND I/O177 VCCO NC GND I/O164 TDI I/O160 D

E I/O27 I/O26 I/O25 NC I/O163 I/O161 I/O159 I/O156 E

F I/O30 TCK I/O28 VCCO VCCO I/O158 NC I/O154 F

G I/O33 I/O32 I/O31 I/O29 I/O157 I/O155 I/O153 I/O152 G

H I/O35 NC I/O34 GND GND GND GND GND GND GND GND I/O151 I/O150 I/O149 H

J I/O39 I/O38 I/O37 I/O36 GND GND GND GND GND GND I/O148 I/O147 I/O146 I/O145 J

K I/O42 I/O40 I/O41 VCC GND GND GND GND GND GND I/O144 CLK3/I4 NC NC K

L I/O43 I/O44 I/O45 I/O46 GND GND GND GND GND GND VCC CLK2/I3 I/O143 NC L

M I/O47 CLK0/I0 CLK1/I1 I/O48 GND GND GND GND GND GND I/O139 I/O140 I/O141 I/O142 M

N I/O49 I/O50 I/O51 GND GND GND GND GND GND GND GND I/O136 I/O137 I/O138 N

P I/O52 I/O53 I/O55 I/O58 I/O131 I/O133 I/O134 I/O135 P

R I/O54 I/O56 I/O59 VCCO VCCO I/O130 NC I/O132 R

T I/O57 I/O60 I/O62 I/O65 I/O124 I/O127 I/O128 I/O129 T

U I/O61 I/O63 I/O66 GND I/O76 VCCO I/O82 GND I/O91 VCC I/O98 I/O102 GND I/O112 VCCO NC GND I/O123 I/O122 I/O126 U

V I/O64 I/O67 I/O69 I/O75 I/O78 I/O81 I/O85 I/O88 I/O92 I2 I/O97 I/O101 I/O105 I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V

W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 I/O95 I/O96 I/O100 I/O104 I/O107 I/O110 NC NC I/O115 I/O118 I/O120 W

Y I/O71 I/O73 I/O77 TMS I/O80 I/O84 I/O87 I/O90 I/O94 NC NC I/O99 I/O103 I/O106 I/O108 I/O111 NC NC I/O116 I/O119 Y

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20




256-Ball Fine-Pitch BGA (BB256)Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A GND GND I/O26 I/O24 I/O20 VCC I/O11 GND GND I/O186 VCC I/O177 I/O172 I/O167 GND GND

B GND I/O27 I/O25 I/O23 I/O19 I/O15 I/O10 GND GND I/O185 I/O181 I/O176 I/O171 I/O166 I/O165 GND

C I/O29 I/O28 NC I/O22 I/O18 I/O14 I/O9 I/O4 I/O191 I/O184 I/O180 I/O175 I/O170 NC I/O163 I/O164

D I/O32 I/O31 I/O30 NC I/O17 I/O13 I/O8 I/O3 I/O190 I/O183 I/O179 I/O174 I/O169 I/O160 I/O161 I/O162

E I/O35 I/O34 I/O33 I/O21 I/O16 I/O12 I/O7 I/O2 I/O189 VCC I/O178 I/O173 I/O168 I/O157 I/O158 I/O159

F VCC I/O38 I/O37 I/O36 TCK VCC I/O6 I/O1 I/O188 I/O182 VCC TDI I/O154 I/O155 I/O156 VCC

G I/O43 I/O42 I/O41 I/O40 VCC I/O39 I/O5 I/O0 I/O187 I/O148 I/O149 CLK3 /I4

I/O150 I/O151 I/O152 I/O153

H GND GND I/O47 I/O46 CLK0 /I0

I/O45 I/O44 GND GND I/O144 I/O145 CLK2 /I3

I/O146 I/O147 GND GND

J GND GND I/O51 I/O50 NC I/O49 I/O48 GND GND I/O140 I/O141 I2 I/O142 I/O143 GND GND

K I/O57 I/O56 I/O55 I/O54 CLK1 /I1

I/O53 I/O52 I/O91 I/O96 I/O101 I/O135 VCC I/O136 I/O137 I/O138 I/O139

L VCC I/O60 I/O59 I/O58 TMS VCC I/O86 I/O92 I/O97 I/O102 VCC TDO I/O132 I/O133 I/O134 VCC

M I/O63 I/O62 I/O61 I/O72 I/O77 I/O82 VCC I/O93 I/O98 I/O103 I/O108 I/O112 I/O117 I/O129 I/O130 I/O131

N I/O66 I/O65 I/O64 I/O73 I/O78 I/O83 I/O87 I/O94 I/O99 I/O104 I/O109 I/O113 NC I/O126 I/O127 I/O128

P I/O68 I/O67 NC I/O74 I/O79 I/O84 I/O88 I/O95 I/O100 I/O105 I/O110 I/O114 I/O118 NC I/O124 I/O125

R GND I/O69 I/O70 I/O75 I/O80 I/O85 I/O89 GND GND I/O106 I/O111 I/O115 I/O119 I/O121 I/O123 GND

T GND GND I/O71 I/O76 I/O81 VCC I/O90 GND GND I/O107 VCC I/O116 I/O120 I/O122 GND GND



Pin Configurations[20] (continued)388-Lead PBGA (BG388)

Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

A GND GND I/O19 I/O15 I/O13 I/O34 I/O31 I/O28 I/O25 I/O10 I/O7 I/O4 I/O1 I/O263 I/O260 I/O257 I/O254 I/O239 I/O237 I/O232 I/O229 I/O250 I/O248 I/O244 GND GND

B GND NC I/O18 I/O17 I/O14 I/O35 I/O32 I/O29 I/O26 I/O11 I/O8 I/O5 I/O2 VCC I/O261 I/O258 I/O255 I/O252 I/O234 I/O231 I/O228 I/O249 I/O246 I/O245 I/O240 GND

C I/O23 I/O38 I/O37 I/O16 I/O12 I/O33 I/O30 I/O27 I/O24 I/O9 I/O6 I/O3 I/O0 I/O262 I/O259 I/O256 I/O253 I/O238 I/O235 I/O233 I/O230 I/O251 I/O247 I/O225 I/O224 I/O227

D I/O39 I/O40 I/O36 NC NC I/O21 I/O20 VCCO VCCO NC GND GND VCCO VCCO GND GND NC VCCO VCCO I/O236 I/O243 NC NC I/O226 I/O222 I/O223

E I/O42 TCK I/O41 NC NC TDI I/O221 I/O220

F I/O45 I/O44 I/O43 I/O22 I/O242 I/O219 I/O218 I/O217

G I/O48 I/O47 I/O46 I/O63 I/O241 I/O216 I/O215 I/O214

H I/O49 I/O50 I/O51 VCCO VCCO I/O211 I/O212 I/O213

J I/O52 I/O53 I/O54 VCCO VCCO I/O208 I/O209 I/O210

K I/O55 I/O56 I/O57 NC NC I/O205 I/O206 I/O207

L I0 I/O59 I/O58 GND GND GND GND GND GND GND GND I/O204 I4 I/O197

M I/O61 I/O60 I1 GND GND GND GND GND GND GND GND I3 I/O203 I/O202

N I/O64 VCC I/O62 VCCO GND GND GND GND GND GND VCCO I/O201 I/O200 I/O199

P I/O65 I/O66 I/O67 VCCO GND GND GND GND GND GND VCCO I/O196 VCC I/O198

R I/O68 I/O69 I/O70 GND GND GND GND GND GND GND GND I/O193 I/O194 I/O195

T I/O71 I/O84 I/O85 GND GND GND GND GND GND GND GND I/O178 I/O179 I/O192

U I/O88 I/O87 I/O86 NC NC I/O177 I/O176 I/O175

V I/O91 I/O90 I/O89 VCCO VCCO I/O174 I/O173 I/O172

W I/O94 I/O93 I/O92 VCCO VCCO I/O171 I/O170 I/O169

Y I/O95 I/O72 I/O73 I/O110 I/O153 I/O190 I/O191 I/O168

AA I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I/O188 I/O189

AB I/O77 I/O78 I/O79 N/C NC I/O184 I/O185 I/O186

AC I/O81 I/O80 I/O108 N/C NC I/O112 I/O113 VCCO VCCO NC GND GND VCCO VCCO GND GND NC VCCO VCCO I/O150 I/O151 NC NC I/O155 I/O183 I/O182

AD I/O109 I/O82 I/O83 I/O117 I/O97 I/O100 I/O102 I/O105 I/O120 I/O123 I/O126 I/O129 I2 I/O133 I/O136 I/O139 I/O142 I/O157 I/O159 I/O161 I/O163 I/O166 I/O146 I/O180 I/O181 I/O154

AE GND NC I/O115 I/O116 I/O119 I/O98 I/O101 I/O103 I/O106 I/O121 I/O124 I/O127 VCC I/O130 I/O134 I/O137 I/O140 I/O143 I/O160 I/O162 I/O165 I/O144 I/O147 I/O148 NC GND

AF GND GND I/O114 I/O118 I/O96 I/O99 TMS I/O104 I/O107 I/O122 I/O125 I/O128 I/O131 I/O132 I/O135 I/O138 I/O141 I/O156 I/O158 TDO I/O164 I/O167 I/O145 I/O149 GND GND




400-Ball Fine-Pitch BGA (BB400)Top View

A GND GND NC I/O17 I/O16 I/O14 I/O29 VCC I/O11 GND GND I/O257 VCC I/O239 I/O233 I/O232 I/O230 NC GND GND

B GND GND GND NC I/O15 I/O13 I/O28 VCC I/O10 GND GND I/O256 VCC I/O238 I/O231 I/O229 NC GND GND GND

C NC GND GND GND I/O20 I/O12 I/O27 VCC I/O9 GND GND I/O255 VCC I/O237 I/O228 I/O245 GND GND GND NC

D I/O44 NC GND I/O21 I/O19 I/O18 I/O26 I/O25 I/O8 GND GND I/O254 I/O235 I/O236 I/O251 I/O244 I/O243 GND NC I/O227

E I/O46 I/O43 I/O23 I/O22 NC I/O35 I/O34 I/O24 I/O7 I/O4 I/O263 I/O253 I/O234 I/O250 I/O248 NC I/O241 I/O242 I/O225 I/O226

F I/O47 I/O45 I/O42 I/O41 I/O40 NC I/O33 I/O32 I/O6 I/O3 I/O262 I/O252 I/O249 I/O247 I/O220 I/O221 I/O240 I/O222 I/O223 I/O224

G I/O53 I/O52 I/O51 I/O50 I/O39 I/O38 I/O37 I/O31 I/O5 I/O2 I/O261 VCC I/O246 I/O217 I/O218 I/O219 I/O212 I/O213 I/O214 I/O215

H VCC VCC VCC I/O49 I/O48 I/O36 TCK VCC I/O30 I/O1 I/O259 I/O260 VCC TDI I/O216 I/O210 I/O211 VCC VCC VCC

J I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 VCC I/O62 I/O60 I/O0 I/O258 I/O202 I/O203 CLK3 /I4

I/O204 I/O205 I/O206 I/O207 I/O208 I/O209

K GND GND GND GND I/O65 I/O64 CLK0 /I0

I/O63 I/O61 GND GND I/O198 I/O199 CLK2 /I3

I/O200 I/O201 GND GND GND GND

L GND GND GND GND I/O69 I/O68 NC I/O67 I/O66 GND GND I/O193 I/O195 I2 I/O196 I/O197 GND GND GND GND

M I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 CLK1 /I1

I/O71 I/O70 I/O126 I/O132 I/O192 I/O194 VCC I/O174 I/O175 I/O176 I/O177 I/O178 I/O179

N VCC VCC VCC I/O91 I/O90 I/O72 TMS VCC I/O128 I/O127 I/O133 I/O162 VCC TDO I/O180 I/O168 I/O169 VCC VCC VCC

P I/O95 I/O94 I/O93 I/O92 I/O75 I/O74 I/O73 I/O114 VCC I/O129 I/O134 I/O137 I/O163 I/O181 I/O182 I/O183 I/O170 I/O171 I/O172 I/O173

R I/O80 I/O79 I/O78 I/O108 I/O77 I/O76 I/O115 I/O117 I/O120 I/O130 I/O135 I/O138 I/O164 I/O165 NC I/O184 I/O185 I/O186 I/O189 I/O191

T I/O82 I/O81 I/O110 I/O109 NC I/O116 I/O118 I/O102 I/O121 I/O131 I/O136 I/O139 I/O156 I/O166 I/O167 NC I/O154 I/O155 I/O187 I/O190

U I/O83 NC GND I/O111 I/O112 I/O119 I/O104 I/O103 I/O122 GND GND I/O140 I/O157 I/O158 I/O150 I/O151 I/O153 GND NC I/O188

V NC GND GND GND I/O113 I/O96 I/O105 VCC I/O123 GND GND I/O141 VCC I/O159 I/O144

I/O152 GND GND GND NC

W GND GND GND NC I/O97 I/O99 I/O106 VCC I/O124 GND GND I/O142 VCC I/O160 I/O145 I/O147 NC GND GND GND

Y GND GND NC I/O98 I/O100 I/O101 I/O107 VCC I/O125 GND GND I/O143 VCC I/O161 I/O146 I/O148 I/O149 NC GND GND



Ordering Information

5.0V Ordering Information

Macrocells Speed(MHz) Ordering Code

PackageName Package Type

OperatingRange

32 200 CY37032P44-200AC A44 44-Lead Thin Quad Flat Pack CommercialCY37032P44-200AXC A44 44-Lead Lead Free Thin Quad Flat PackCY37032P44-200JC J67 44-Lead Plastic Leaded Chip CarrierCY37032P44-200JXC J67 44-Lead Lead Free Plastic Leaded Chip Carrier

154 CY37032P44-154AC A44 44-Lead Thin Quad Flat Pack CommercialCY37032P44-154JC J67 44-Lead Plastic Leaded Chip CarrierCY37032P44-154AI A44 44-Lead Thin Quad Flat Pack IndustrialCY37032P44-154AXI A44 44-Lead Lead Free Thin Quad Flat PackCY37032P44-154JI J67 44-Lead Plastic Leaded Chip CarrierCY37032P44-154JXI J67 44-Lead Lead Free Plastic Leaded Chip Carrier

125 CY37032P44-125AC A44 44-Lead Thin Quad Flat Pack CommercialCY37032P44-125AXC A44 44-Lead Lead Free Thin Quad Flat PackCY37032P44-125JC J67 44-Lead Plastic Leaded Chip CarrierCY37032P44-125JXC J67 44-Lead Lead Free Plastic Leaded Chip CarrierCY37032P44-125AI A44 44-Lead Thin Quad Flat Pack IndustrialCY37032P44-125JI J67 44-Lead Plastic Leaded Chip Carrier

64 200 CY37064P44-200AC A44 44-Lead Thin Quad Flat Pack CommercialCY37064P44-200AXC A44 44-Lead Lead Free Thin Quad Flat PackCY37064P44-200JC J67 44-Lead Plastic Leaded Chip CarrierCY37064P44-200JXC J67 44-Lead Lead Free Plastic Leaded Chip CarrierCY37064P84-200JC J83 84-Lead Plastic Leaded Chip CarrierCY37064P100-200AC A100 100-Lead Thin Quad Flat PackCY37064P100-200AXC A100 100-Lead Lead Free Thin Quad Flat Pack

C Y 3 7 5 1 2 V P 4 0 0 - 8 3 B B X C

Cypress Semiconductor ID

Family Type37 = Ultra37000 Family

Macrocell Density 32 = 32 Macrocells 256 = 256 Macrocells 64 = 64 Macrocells 384 = 384 Macrocells128 = 128 Macrocells 512 = 512Macrocells192 = 192 Macrocells

Speed125 = 125 MHz

200 = 200 MHz 100 = 100 MHz167 = 167 MHz 83 = 83 MHz154 = 154 MHz 66 = 66 MHz143 = 143 MHz

Package TypeA = Thin Quad Flat Pack (TQFP)U = Ceramic Quad Flat Pack (CQFP)N = Plastic Quad Flat Pack (PQFP)NT = Thermally Enhanced Plastic Quad Flat Pack (EQFP)J = Plastic Leaded Chip Carrier (PLCC)Y = Ceramic Leaded Chip Carrier (CLCC)BG = Plastic Ball Grid Array (PBGA)BA = Fine-Pitch Ball Grid Array (FBGA) 0.8mm Lead PitchBB = Fine-Pitch Ball Grid Array (FBGA) 1.0mm Lead Pitch

Operating ConditionsCommercial 0°C to +70°CIndustrial -40°C to +85°CMilitary -55°C to +125°C

Operating Reference VoltageV = 3.3V Supply Voltage(5.0V if not specified)

Pin CountP44 = 44 LeadsP48 = 48 LeadsP84 = 84 LeadsP100 = 100 LeadsP160 = 160 LeadsP208 = 208 LeadsP256 = 256 LeadsP352 = 352 LeadsP400 = 400 Leads

Lead FreeX Lead Free



64 154 CY37064P44-154AC A44 44-Lead Thin Quad Flat Pack CommercialCY37064P44-154JC J67 44-Lead Plastic Leaded Chip CarrierCY37064P84-154JC J83 84-Lead Plastic Leaded Chip CarrierCY37064P100-154AC A100 100-Lead Thin Quad Flat PackCY37064P44-154AI A44 44-Lead Thin Quad Flat Pack IndustrialCY37064P44-154AXI A44 44-Lead Lead Free Thin Quad Flat PackCY37064P44-154JI J67 44-Lead Plastic Leaded Chip CarrierCY37064P44-154JXI J67 44-Lead Lead Free Plastic Leaded Chip CarrierCY37064P84-154JI J83 84-Lead Plastic Leaded Chip CarrierCY37064P100-154AI A100 100-Lead Thin Quad Flat Pack5962-9951902QYA Y67 44-Lead Ceramic Leadless Chip Carrier Military

125 CY37064P44-125AC A44 44-Lead Thin Quad Flat Pack CommercialCY37064P44-125AXC A44 44-Lead Lead Free Thin Quad Flat PackCY37064P44-125JC J67 44-Lead Plastic Leaded Chip CarrierCY37064P44-125JXC J67 44-Lead Lead Free Plastic Leaded Chip CarrierCY37064P84-125JC J83 84-Lead Plastic Leaded Chip CarrierCY37064P100-125AC A100 100-Lead Thin Quad Flat PackCY37064P100-125AXC A100 100-Lead Lead Free Thin Quad Flat PackCY37064P44-125AI A44 44-Lead Thin Quad Flat Pack IndustrialCY37064P44-125AXI A44 44-Lead Lead Free Thin Quad Flat PackCY37064P44-125JI J67 44-Lead Plastic Leaded Chip CarrierCY37064P84-125JI J83 84-Lead Plastic Leaded Chip CarrierCY37064P100-125AI A100 100-Lead Thin Quad Flat PackCY37064P100-125AXI A100 100-Lead Lead Free Thin Quad Flat Pack5962-9951901QYA Y67 44-Lead Ceramic Leadless Chip Carrier Military

5.0V Ordering Information (continued)



OperatingRange



128 167 CY37128P84-167JC J83 84-Lead Plastic Leaded Chip Carrier CommercialCY37128P84-167JXC J83 84-Lead Lead Free Plastic Leaded Chip CarrierCY37128P100-167AC A100 100-Lead Thin Quad Flat PackCY37128P100-167AXC A100 100-Lead Lead Free Thin Quad Flat PackCY37128P160-167AC A160 160-Lead Thin Quad Flat PackCY37128P160-167AXC A160 160-Lead Lead Free Thin Quad Flat Pack

125 CY37128P84-125JC J83 84-Lead Plastic Leaded Chip Carrier CommercialCY37128P84-125JXC J83 84-Lead Lead Free Plastic Leaded Chip CarrierCY37128P100-125AC A100 100-Lead Thin Quad Flat PackCY37128P100-125AXC A100 100-Lead Lead Free Thin Quad Flat PackCY37128P160-125AC A160 160-Lead Thin Quad Flat PackCY37128P160-125AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37128P84-125JI J83 84-Lead Plastic Leaded Chip Carrier IndustrialCY37128P84-125JXI J83 84-Lead Lead Free Plastic Leaded Chip CarrierCY37128P100-125AI A100 100-Lead Thin Quad Flat PackCY37128P100-125AXI A100 100-Lead Lead Free Thin Quad Flat PackCY37128P160-125AI A160 160-Lead Thin Quad Flat PackCY37128P160-125AXI A160 160-Lead Lead Free Thin Quad Flat Pack5962-9952102QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military

100 CY37128P84-100JC J83 84-Lead Plastic Leaded Chip Carrier CommercialCY37128P84-100JXC J83 84-Lead Lead Free Plastic Leaded Chip CarrierCY37128P100-100AC A100 100-Lead Thin Quad Flat PackCY37128P100-100AXC A100 100-Lead Lead Free Thin Quad Flat PackCY37128P160-100AC A160 160-Lead Thin Quad Flat PackCY37128P160-100AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37128P84-100JI J83 84-Lead Plastic Leaded Chip Carrier IndustrialCY37128P100-100AI A100 100-Lead Thin Quad Flat PackCY37128P100-100AXI A100 100-Lead Lead Free Thin Quad Flat PackCY37128P160-100AI A160 160-Lead Thin Quad Flat Pack5962-9952101QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military

192 154 CY37192P160-154AC A160 160-Lead Thin Quad Flat Pack CommercialCY37192P160-154AXC A160 160-Lead Lead Free Thin Quad Flat Pack

125 CY37192P160-125AC A160 160-Lead Thin Quad Flat Pack CommercialCY37192P160-125AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37192P160-125AI A160 160-Lead Thin Quad Flat Pack IndustrialCY37192P160-125AXI A160 160-Lead Lead Free Thin Quad Flat Pack

83 CY37192P160-83AC A160 160-Lead Thin Quad Flat Pack CommercialCY37192P160-83AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37192P160-83AI A160 160-Lead Thin Quad Flat Pack IndustrialCY37192P160-83AXI A160 160-Lead Lead Free Thin Quad Flat Pack




OperatingRange



256 154 CY37256P160-154AC A160 160-Lead Thin Quad Flat Pack CommercialCY37256P160-154AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37256P208-154NC N208 208-Lead Plastic Quad Flat PackCY37256P256-154BGC BG292 292-Ball Plastic Ball Grid Array

125 CY37256P160-125AC A160 160-Lead Thin Quad Flat Pack CommercialCY37256P160-125AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37256P208-125NC N208 208-Lead Plastic Quad Flat PackCY37256P256-125BGC BG292 292-Ball Plastic Ball Grid Array CY37256P160-125AI A160 160-Lead Thin Quad Flat Pack IndustrialCY37256P160-125AXI A160 160-Lead Lead Free Thin Quad Flat PackCY37256P208-125NI N208 208-Lead Plastic Quad Flat PackCY37256P256-125BGI BG292 292-Ball Plastic Ball Grid Array5962-9952302QZC U162 160-Lead Ceramic Quad Flat Pack Military

83 CY37256P160-83AC A160 160-Lead Thin Quad Flat Pack CommercialCY37256P160-83AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37256P208-83NC N208 208-Lead Plastic Quad Flat PackCY37256P256-83BGC BG292 292-Ball Plastic Ball Grid Array CY37256P160-83AI A160 160-Lead Thin Quad Flat Pack IndustrialCY37256P160-83AXI A160 160-Lead Lead Free Thin Quad Flat PackCY37256P208-83NI N208 208-Lead Plastic Quad Flat PackCY37256P256-83BGI BG292 292-Ball Plastic Ball Grid Array 5962-9952301QZC U162 160-Lead Ceramic Quad Flat Pack Military

384 125 CY37384P208-125NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37384P256-125BGC BG292 292-Ball Plastic Ball Grid Array

83 CY37384P208-83NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37384P256-83BGC BG292 292-Ball Plastic Ball Grid Array CY37384P208-83NI N208 208-Lead Plastic Quad Flat Pack IndustrialCY37384P256-83BGI BG292 292-Ball Plastic Ball Grid Array




OperatingRange



512 125 CY37512P208-125NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37512P256-125BGC BG292 292-Ball Plastic Ball Grid ArrayCY37512P352-125BGC BG388 388-Ball Plastic Ball Grid Array

100 CY37512P208-100NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37512P256-100BGC BG292 292-Ball Plastic Ball Grid Array CY37512P352-100BGC BG388 388-Ball Plastic Ball Grid Array CY37512P208-100NI N208 208-Lead Plastic Quad Flat Pack IndustrialCY37512P256-100BGI BG292 292-Ball Plastic Ball Grid Array CY37512P352-100BGI BG388 388-Ball Plastic Ball Grid Array 5962-9952502QZC U208 208-Lead Ceramic Quad Flat Pack Military

83 CY37512P208-83NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37512P256-83BGC BG292 292-Ball Plastic Ball Grid Array CY37512P352-83BGC BG388 388-Ball Plastic Ball Grid Array CY37512P208-83NI N208 208-Lead Plastic Quad Flat Pack IndustrialCY37512P256-83BGI BG292 292-Ball Plastic Ball Grid Array CY37512P352-83BGI BG388 388-Ball Plastic Ball Grid Array 5962-9952501QZC U208 208-Lead Ceramic Quad Flat Pack Military




OperatingRange

3.3V Ordering Information

MacrocellsSpeed(MHz) Ordering Code

Package Name Package Type

OperatingRange

32 143 CY37032VP44-143AC A44 44-Lead Thin Quad Flat Pack CommercialCY37032VP44-143AXC A44 44-Lead Lead Free Thin Quad Flat PackCY37032VP48-143BAC BA50 48-Ball Fine Pitch Ball Grid Array

100 CY37032VP44-100AC A44 44-Lead Thin Quad Flat Pack CommercialCY37032VP44-100AXC A44 44-Lead Lead Free Thin Quad Flat PackCY37032VP48-100BAC BA50 48-Ball Fine Pitch Ball Grid ArrayCY37032VP44-100AI A44 44-Lead Thin Quad Flat Pack IndustrialCY37032VP44-100AXI A44 44-Lead Lead Free Thin Quad Flat PackCY37032VP48-100BAI BA50 48-Ball Fine Pitch Ball Grid ArrayCY37032VP44-100JI J67 44-Lead Plastic Leaded Chip CarrierCY37032VP44-100JXI J67 44-Lead Lead Free Plastic Leaded Chip Carrier



64 143 CY37064VP44-143AC A44 44-Lead Thin Quad Flatpack CommercialCY37064VP44-143AXC A44 44-Lead Lead Free Thin Quad FlatpackCY37064VP48-143BAC BA50 48-Ball Fine-Pitch Ball Grid ArrayCY37064VP100-143AC A100 100-Lead Thin Quad FlatpackCY37064VP100-143AXC A100 100-Lead Lead Free Thin Quad FlatpackCY37064VP100-143BBC BB100 100-Ball Fine-Pitch Ball Grid Array

100 CY37064VP44-100AC A44 44-Lead Thin Quad Flatpack CommercialCY37064VP44-100AXC A44 44-Lead Lead Free Thin Quad FlatpackCY37064VP48-100BAC BA50 48-Ball Fine-Pitch Ball Grid ArrayCY37064VP100-100AC A100 100-Lead Thin Quad FlatpackCY37064VP100-100AXC A100 100-Lead Lead Free Thin Quad FlatpackCY37064VP100-100BBC BB100 100-Ball Fine-Pitch Ball Grid ArrayCY37064VP44-100AI A44 44-Lead Thin Quad Flatpack IndustrialCY37064VP44-100AXI A44 44-Lead Lead Free Thin Quad FlatpackCY37064VP48-100BAI BA50 48-Ball Fine-Pitch Ball Grid ArrayCY37064VP100-100BBI BB100 100-Ball Fine-Pitch Ball Grid ArrayCY37064VP100-100AI A100 100-Lead Thin Quad FlatpackCY37064VP100-100AXI A100 100-Lead Lead Free Thin Quad Flatpack5962-9952001QYA Y67 44-Lead Ceramic Leaded Chip Carrier Military

128 125 CY37128VP100-125AC A100 100-Lead Thin Quad Flat Pack CommercialCY37128VP100-125AXC A100 100-Lead Lead Free Thin Quad Flat PackCY37128VP100-125BBC BB100 100-Ball Fine-Pitch Ball Grid ArrayCY37128VP160-125AC A160 160-Lead Thin Quad Flat PackCY37128VP160-125AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37128VP160-125AI A160 160-Lead Thin Quad Flat Pack IndustrialCY37128VP160-125AXI A160 160-Lead Lead Free Thin Quad Flat Pack

83 CY37128VP100-83AC A100 100-Lead Thin Quad Flat Pack CommercialCY37128VP100-83AXC A100 100-Lead Lead Free Thin Quad Flat PackCY37128VP100-83BBC BB100 100-Ball Fine-Pitch Ball Grid ArrayCY37128VP160-83AC A160 160-Lead Thin Quad Flat PackCY37128VP160-83AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37128VP100-83AI A100 100-Lead Thin Quad Flat Pack IndustrialCY37128VP100-83AXI A100 100-Lead Lead Free Thin Quad Flat PackCY37128VP100-83BBI BB100 100-Ball Fine-Pitch Ball Grid ArrayCY37128VP160-83AI A160 160-Lead Thin Quad Flat PackCY37128VP160-83AXI A160 160-Lead Lead Free Thin Quad Flat Pack5962-9952201QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military

192 100 CY37192VP160-100AC A160 160-Lead Thin Quad Flat Pack CommercialCY37192VP160-100AXC A160 160-Lead Lead Free Thin Quad Flat Pack

66 CY37192VP160-66AC A160 160-Lead Thin Quad Flat Pack CommercialCY37192VP160-66AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37192VP160-66AI A160 160-Lead Thin Quad Flat Pack Industrial




OperatingRange



256 100 CY37256VP160-100AC A160 160-Lead Thin Quad Flat Pack CommercialCY37256VP160-100AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37256VP208-100NC N208 208-Lead Plastic Quad Flat PackCY37256VP256-100BGC BG292 292-Ball Plastic Ball Grid Array CY37256VP256-100BBC BB256 256-Ball Fine-Pitch Ball Grid ArrayCY37256VP160-100AI A160 160-Lead Thin Quad Flat Pack IndustrialCY37256VP160-100AXI A160 160-Lead Lead Free Thin Quad Flat Pack

66 CY37256VP160-66AC A160 160-Lead Thin Quad Flat Pack CommercialCY37256VP160-66AXC A160 160-Lead Lead Free Thin Quad Flat PackCY37256VP208-66NC N208 208-Lead Plastic Quad Flat PackCY37256VP256-66BGC BG292 292-Ball Plastic Ball Grid ArrayCY37256VP256-66BBC BB256 256-Ball Fine-Pitch Ball Grid ArrayCY37256VP160-66AI A160 160-Lead Thin Quad Flat Pack IndustrialCY37256VP256-66BGI BG292 292-Ball Plastic Ball Grid Array CY37256VP256-66BBI BB256 256-Ball Fine-Pitch Ball Grid Array5962-9952401QZC U162 160-Lead Ceramic Quad Flat Pack Military

384 83 CY37384VP208-83NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37384VP256-83BGC BG292 292-Ball Plastic Ball Grid Array

66 CY37384VP208-66NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37384VP256-66BGC BG292 292-Ball Plastic Ball Grid Array CY37384VP208-66NI N208 208-Lead Plastic Quad Flat Pack IndustrialCY37384VP256-66BGI BG292 292-Ball Plastic Ball Grid Array

512 83 CY37512VP208-83NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37512VP256-83BGC BG292 292-Ball Plastic Ball Grid Array CY37512VP352-83BGC BG388 388-Ball Plastic Ball Grid Array CY37512VP400-83BBC BB400 400-Ball Fine-Pitch Ball Grid Array

66 CY37512VP208-66NC N208 208-Lead Plastic Quad Flat Pack CommercialCY37512VP256-66BGC BG292 292-Ball Plastic Ball Grid Array CY37512VP352-66BGC BG388 388-Ball Plastic Ball Grid Array CY37512VP400-66BBC BB400 400-Ball Fine-Pitch Ball Grid ArrayCY37512VP208-66NI N208 208-Lead Plastic Quad Flat Pack IndustrialCY37512VP256-66BGI BG292 292-Ball Plastic Ball Grid Array CY37512VP352-66BGI BG388 388-Ball Plastic Ball Grid Array CY37512VP400-66BBI BB400 400-Ball Fine-Pitch Ball Grid Array5962-9952601QZC U208 208-Lead Ceramic Quad Flat Pack Military




OperatingRange



Package Diagrams

51-85064-*B

44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44

51-85003-*A

44-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J67



Package Diagrams (continued)

44-Lead Ceramic Leaded Chip Carrier Y67

51-80014-**




48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D

51-85109-*C

51-85006-*A

84-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J83




84-Lead Ceramic Leaded Chip Carrier Y84

51-80095-*A




51-85048-*B

100-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100




100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100

51-85107-*B




51-85049-*B

160-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160




SEATING PLANE

DIMENSION IN MM (INCH)

2.79(.110)2.03(.080)

0.500(.020)0.050(.002)

(.020 ±.008)0.51 ±0.20

(.006 ±.001)0.15 ±0.02

TYP.0.300(.012)

TYP.0.650(.0256)

(1.228 ±.010)31.20 ±0.25

(1.102 ±.004)28.00 ±0.10

SQ.

SQ.

PIN 1

25.35±0.10(.998±.004)

TYP.

SEE DETAIL A

(.008 MIN.)

0°-7°

0.20 MIN.

DETAIL A

REFERENCE JEDEC: N/APKG. WEIGHT: 6-7gms

0° MIN.

R 0.13(.005)MIN.

160-Lead Ceramic Quad Flatpack (Cavity Up) U162

51-80106-*A




208-Lead Plastic Quad Flatpack N208

51-85069-*B




SEATING PLANE

DIMENSIONS IN MM (INCH)

0.500(.020)0.050(.002)

3.94(.155)3.43(.135)

(.006 ±.001)0.15 ±0.02

(.020 ±.008)0.51 ±0.20

(1.229 ±.010)31.22 ±0.25

(1.102 ±.008)28.00 ±0.10

TYP.0.50(.0197)

TYP.0.20(.008)

SQ.

SQ.

PIN 1

SEE DETAIL A

(.008 MIN.)

0°-7°

0.20 MIN.

DETAIL A

REFERENCE JEDEC: N/A

PKG. WEIGHT: 6-7gms

0° MIN.

R 0.13(.005)MIN.

51-80105-*B

208-Lead Ceramic Quad Flatpack (Cavity Up) U208




BOTTOM VIEWTOP VIEW

10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

PIN 1 CORNERPIN 1 CORNER

0.20(4X)

Ø0.25 M C A B

Ø0.05 M C

Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K)

0.25

C

0.70

±0.

05

C

SEATING PLANE

0.15

C

16 15 14 13 12 11

T

R

P

M

N

L

N

T

R

P

M

L

K

J

F

G

H

E

D

A

C

B

161513 141210 1192 8765431

A

B

Ø0.50 (256X)-ALL OTHER DEVICES+0.10-0.05

A1 0.36 0.56

A 1.40 MAX. 1.70 MAX.

REFERENCE JEDEC MO-192

15.00

1.00

0.35

A

17.00±0.10

7.50

7.50

15.0

0

17.0

0±0.

10

1.00

A1

-0.0

5+

0.10

256-Ball FBGA (17 x 17 mm) BB256

51-85108-*F




292-Ball Plastic Ball Grid Array PBGA (27 x 27 x 2.33 mm) BG292

51-85097-*B




51-85103-*C

388-Ball Plastic Ball Grid Array PBGA (35 x 35 x 2.33 mm) BG388



ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Warp isa registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37000 are trade-marks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarksof their respective holders.


400-Ball FBGA (21 x 21 x 1.4 mm) BB400

51-85111-*A

Document #: 38-03007 Rev. *E of 64© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to beused for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize itsproducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypressproducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.


Addendum

3.3V Operating Range (CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC)

Range Ambient Temperature[2] Junction Temperature VCC

Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.16V



Document History Page

Document Title: Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDsDocument Number: 38-03007

REV. ECN NO.Issue Date

Orig. of Change Description of Change

** 106272 04/18/01 SZV Change from Spec number: 38-00475 to 38-03007*A 124942 03/21/03 OOR Updated 3.3V VCC requirements for –144 speeds

Added an Addendum*B 126262 05/09/03 TEH Changed pinout for CY37128V BB100 package*C 128125 07/16/03 HOM Obsoleted following 3.3V PLCC packaged devices:

CY37032VP44-143JCCY37032VP44-100JCCY37032VP44-100JICY37064VP44-143JCCY37064VP84-143JCCY37064VP44-100JCCY37064VP84-100JCCY37064VP44-100JICY37064VP84-100JICY37128VP84-125JCCY37128VP84-83JCCY37128VP84-83JI

*D 282709 See ECN YDT Changed package diagrams and labels for consistencyAdded Lead (Pb)-free logo on first page, as well as a note in FeaturesAdded Lead (Pb)-free package diagram labelsAdded Lead-free Parts to Ordering InformationCY37032P44-200AXC, CY37032P44-200JXC, CY37032P44-154AXI, CY37032P44-154JXI, CY37032P44-125AXC, CY37032P44-125JXC, CY37064P44-200AXC, CY37064P44-200JXC, CY37064P100-200AXC, CY37064P44-154AXI, CY37064P44-154JXI, CY37064P44-125AXC, CY37064P44-125JXC, CY37064P100-125AXC, CY37064P44-125AXI, CY37064P100-125AXI, CY37128P84-167JXC, CY37128P100-167AXC, CY37128P160-167AXC, CY37128P84-125JXC, CY37128P100-125AXC, CY37128P160-125AXC, CY37128P84-125JXI, CY37128P100-125AXI, CY37128P160-125AXI, CY37128P84-100JXC, CY37128P100-100AXC, CY37128P160-100AXC, CY37128P100-100AXI, CY37192P160-154AXC, CY37192P160-125AXC, CY37192P160-125AXI, CY37192P160-83AXC, CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC, CY37256P160-125AXI, CY37256P160-83AXC, CY37256P160-83AXI, CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI, CY37032VP44-100JXI, CY37064VP44-143AXC, CY37064VP100-143AXC, CY37064VP44-100AXC, CY37064VP100-100AXC, CY37064VP44-100AXI, CY37064VP100-100AXI, CY37128VP100-125AXC, CY37128VP160-125AXC, CY37128VP160-125AXI, CY37128VP100-83AXC, CY37128VP160-83AXC, CY37128VP100-83AXI, CY37128VP160-83AXI, CY37192VP160-100AXC, CY37192VP160-66AXC, CY37256VP160-100AXC, CY37256VP160-100AXI, CY37256VP160-66AXC

*E 321635 See ECN PCX Added Package Diagram BG292Updated all PBGA package type information (BG292 & BG388)


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