4 Combination

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    ENEL 111

    NAND gates and Duality

    Adders

    Multiplexers

    A NAND gate:

    Y = A.B = A + B

    is the same as an OR gate with two NOT gates

    Similarly a NOR gate is the same as an AND gatewith two inverters

    Y = A + B = A.Bnot the individual terms

    change the sign

    not the lot

    not the individual inputs

    change the gatenot the output

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    NAND Gate

    Representation

    It is possible toimplement anyboolean expressionusing only NANDgates

    XX

    NOT

    ANDA

    B

    A.B

    A.B

    OR

    A + B = A.B

    A

    A+B

    B

    NAND Gate representation

    Implement the following circuit using only NAND gates

    x3

    x2

    x4

    De Morgan can also be represented visually:

    Dual the gates, remember two nots together canbe removed.

    x3

    x2

    x4

    A

    B

    A.B

    A.B

    A

    A+B

    B

    AND feeding OR

    Implement NOT, AND and OR using NOR gates

    Example AND gate dual circuit:

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    Similar pattern to using NAND gates (not surprising)

    NOT

    AND

    OR

    XX

    A

    B

    A.B

    A.B

    A

    A+B

    B

    XX

    A

    B

    A.B

    A+B

    A

    A.B

    B

    NOR Gate representation

    It is also possible to implement any booleanexpression using only NOR gates

    Implement the following circuit using only NOR gates

    X4

    X3

    X2

    Two NOR gates in sequence acting as NOTs can beeliminated:

    X4

    X3

    X2

    The half adder

    The half adder is a circuit for adding twosingle bit numbers

    Develop a truth table and Booleanexpressions for the half adder

    S and C are the Sum and Carry

    11

    01

    10

    00

    CSBA

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    The sum is XOR operation and the carry an AND:

    1011

    0101

    0110

    0000

    CSBA A

    B

    C

    S

    The full adder

    Develop a truth table and Boolean expressions for thefull adder, this circuit also includes a carry in.

    Cin A B S C

    0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

    fulladder

    A

    B

    Cin

    Sum

    Cout

    10110

    01001

    10101

    10011

    1

    0

    0

    0

    Cin

    1111

    0101

    0110

    0000

    CoutSBA

    Exercise:

    Complete theKarnaugh maps for

    the Sum and theCarry out columns

    111

    110

    10110100AB

    Cin

    1111

    10

    10110100AB

    Cin

    Sum 1 when odd number of inputsis 1 = XOR gate

    Carry out - simplifies to 3 pairs

    Sum = Cin xor A xor B Cout = A.B + A.Cin + B.Cin

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    A

    B

    Cin

    Cout

    Sum

    Sum = Cin xor A xor B Cout = A.B + A.Cin + B.Cin

    The MultiplexerSelects one of 2n inputs and copies it to a singleoutput

    The selected line is determined from the bitcombination (address) on the n selection lines

    e.g. 1 from 2 mutiplexer

    0 0 0

    0 0 1

    0 1 0

    0 1 1

    1 0 0

    1 0 1

    1 1 0

    1 1 1

    sel a b out

    selab 00 01 11 10

    0

    1

    out =

    a

    b

    sel

    out

    n = 1

    0

    1

    11110011

    1101

    0001

    1110

    1010

    0100

    0000

    outbasel

    11?1

    00?1

    1?10

    0?00

    outbasel

    if a is selected, dont

    care about b.

    111

    11010110100

    AB

    sel

    111

    110

    10110100

    AB

    sel output = sel.a + sel.b

    Principal can be extended to

    4:1 2 select lines and 4 data lines

    8:1 3 select lines and 8 data lines

    and so on

    data

    sel

    out

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    Change circuits using one set of gates (eg AND, OR,NOT) to their equivalent using NAND or NOR gates only(and vice versa).

    Be familiar with half-, full- adders and multiplexer circuits.

    Be able to construct and interpret Karnaugh maps with upto 4 input variables.

    (if you need practice, come to the tutorial)