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Chapter 3 Switch Level

3.1 Syntax List

3.1.1 MOS Switch nmos n1(out , data , control ) ; pmos p1(out , data , control ) ; Two types of MOS switches, nmos is used to model NMOS transistor, pmos is used to model PMOS transistors. The symbols for NMOS and PMOS switches are shown below.

3.1.2 CMOS Switch cmos c1(out , data , ncontrol , pcontrol ) ; CMOS switches are declared with the keyword cmos. A CMOS device can be modeled with a NMOS and PMOS devices. The symbol for a CMOS switch is shown below.

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3.1.3 Bidirection Switch tran t1( inout1, inout2 ) ; tranif0 t2 (inout1, inout2 , control ) ; tranif1 t3 (inout1, inout2 , control ) ; The tran switch acts as a buffer between the two signals inout1 and in-out2. Either inout1, or inout2 can be driver signal. The tranif0 switch connects the two signals inout1 and inout2 only if the control signal is logic 0. If the control signal is a logic 1, the nondriver signal gets a high impedance value z. The driver signal retains value from its driver. The tranif1 switch conducts if the control signal is a logic 1.

The symbols for these switches are shown below.

3.1.4 Resistive Switch rnmos n2(out , data , control ) ; rpmos p2(out , data , control ) ; rcmos c2(out , data , control ) ; rtran t4(inout1 , inout2 ) ; rtranif0 t5(inout1 , inout2 , control ) ; rtranif1 t6(inout1 , inout2 , control ) ;

Resistive switches have a higher source to drain impedance than regular switches and reduce the strength of signals when the signal passes through them. Resistive switches have the same syntax as regular switches.

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module my_nor(out, A, B); output out; input A, B; wire c; supply1 pwr; //pwr is connected to Vdd supply0 gnd; //gnd is connected to Vss(ground) pmos (c, pwr, B); pmos (out, c, A); nmos (out, gnd, A); nmos (out, gnd, B); endmodule

3.2 Basic Design Example There are four examples to describe the gate level design. Each example will contain (1) transistor circuit (2) verilog code (3) test stimulus code (4)simulation result (5)simulation waveform

3.2.1 CMOS NOR Gate Design We design our own nor gate, using CMOS switches. the gate and the switch level circuit diagram for the nor gate is show below .

Verilog Code Using the switch primitives discussed first, the verilog description of the circuit is shown below.

Pwr is connected to vdd

Gnd is connected to vss

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module stimulus; reg A, B; wire OUT; my_nor n1(OUT, A, B); initial begin A = 1'b0; B = 1'b0; #10 A = 1'b0; B = 1'b1; #10 A = 1'b1; B = 1'b0; #10 A = 1'b1; B = 1'b1; #10 A = 1'b0; B = 1'b0; end initial $monitor($time, " OUT = %b, A = %b, B = %b", OUT, A, B); endmodule

Test Stimulus Code Now, we can test our_nor gate, using the stimulus is shown below.

Simulation Result The output of the simulation is shown below.

Call my_nor module

Test all possible combinations

Show result

Simulation result

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Simulation Waveform According truth table, when input contains 1, then output is 0.

3.2.2 1-Bit Full Adder Design Using the CMOS design the 1-bit full adder, the logic diagram is shown below.

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module my_not(out,in); //Define output input output out; input in; //Define power and gound supply1 pwr; supply0 gnd; //Instantiate the CMOS switches pmos (out,pwr,in); nmos (out,gnd,in); endmodule

module my_xor(out,a,b); output out; input a,b; wire c; my_not nt(c,a); //Instantiate the CMOS switches cmos (out,b,c,a); pmos (out,a,b); nmos (out,c,b); endmodule

Verilog Code We are now ready to write the verilog description for a full adder. First, we need to design our own inverter my_not and my_xor by using switches. We can write the verilog module description for the CMOS inverter from the switch-level circuit diagram.

We need to design our xor module by using switches, too. We can write the verilog module description for CMOS xor form the switch-level circuit diagram.

Built my_not module

Call my_not module previous

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//Define a CMOS Adder module adder(sum,cout,a,b,cin); //Define input output and internal wire output sum,cout; input a,b,cin; wire d,e,f,g my_xor n1(f,a,b); my_not n2(d,f); my_not n3(e,cin); my_not n4(g,b); my_not n5(sum,h); my_not n6(cout,i); //Define instantiate CMOS switches cmos (h,e,d,f); cmos (h,cin,f,d); cmos (i,g,d,f); cmos (i,e,f,d); endmodule

Now, the 1-bit full adder can be defined using the CMOS switch and my_not inverter. The verilog description for a 1-bit full adder is shown below.

Call my_not module previous

Call my_xor module previous

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//Define stimulus module module stimulus; //Define input output reg a,b,cin; wire sum,cout; adder n1(sum,cout,a,b,cin); initial $monitor($time," sum=%b cout=%b a=%b b=%b cin=%b",sum,cout,a,b,cin); initial begin #5 a=1'b0; b=1'b0; cin=1'b0; #5 a=1'b0; b=1'b0; cin=1'b1; #5 a=1'b0; b=1'b1; cin=1'b0; #5 a=1'b0; b=1'b1; cin=1'b1; #5 a=1'b1; b=1'b0; cin=1'b0; #5 a=1'b1; b=1'b0; cin=1'b1; #5 a=1'b1; b=1'b1; cin=1'b0; #5 a=1'b1; b=1'b1; cin=1'b1; end endmodule

Test Stimulus Code We will test 1-bit full adder, using the stimulus is shown below.

Call adder module

Show result

Test all possible combinations

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Simulation Result Simulation result is shown below.

Simulation Waveform According to mathematical equation, we can get waveform is shown below.

All possible combinations

s u m = ( a ? b ? c in )

c o u t = ( a b ) + c in ( a ? b )

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module my_mux (out, s, i0, i1); output out; input s, i0, i1; wire sbar ; my_nor nt(sbar, s, s); cmos (out, i0, sbar, s); cmos (out, i1, s, sbar); endmodule

3.2.3 2 to 1 Multiplexer Design The 2 to 1 multiplexer can be defined with CMOS switches. We will use the my_nor gate declared before. The circuit diagram for the multiplexer is show below.

Verilog Code The 2 to 1 multiplexer passes the input I0 to output if S=0 and passes I1 to OUT if S =1. The switch level description for the 2 to 1 multiplexer is shown below.

Complement of s

Equivalent to a not gate

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module stimulus; reg S, I0, I1; wire OUT; my_mux m1(OUT, S, I0, I1); initial begin I0 = 1'b1; I1 = 1'b0; S = 1'b0; #5 S = 1'b1; #5 I0 = 1'b0; I1 = 1'b1; S = 1'b0; #5 S = 1'b1; end //check results initial $monitor($time," OUT= %b, S= %b I0= %b, I1= %b",OUT,S,I0,I1); endmodule

Test Stimulus Code We will check 2 to 1 multiplexer as shown below.

Simulation Result When S=0, then OUT=I0, otherwise, when S=1, then OUT= I1.

First combination

Second combination

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Simulation waveform The simulation is used to waveform check 2 to 1 multiplexer correctly.

Ouput I0 Output I1 Output I0

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module dff ( q, qbar, d, clk); output q, qbar; input d, clk; wire e; wire nclk; my_not nt(nclk, clk); cmos (e, d, clk, nclk); cmos (e, q, nclk, clk); my_not nt1(qbar, e); my_not nt2(q, qbar); endmodule

3.2.4 Simple CMOS D-Flip-Flop Design The diagram for a D Flip-Flop is show below. The switche C1 and C2 are CMOS switches. Switch C1 is open if clk =1, and switch C2 is open if clk=0. Complement of the clk is fed to the ncontrol input of C2.

Verilog Code We are now ready to write the verilog description for the CMOS Flip-Flop. We will use my_not module previous example.

Call my_not module

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module stimulus; reg D, CLK; wire Q, QBAR; //instantiate the CMOS flipflop dff c1(Q, QBAR, D, CLK); //test load and store using stimulus initial begin //sequence 1 CLK = 1'b0; D = 1'b1; #5 CLK = 1'b1; #5 CLK = 1'b0; //sequence 2 #5 D = 1'b0; #5 CLK = 1'b1; #5 D=1'b1;CLK = 1'b0; end //check output initial begin $monitor($time," CLK = %b, D = %b, Q = %b, QBAR = %b ", CLK, D, Q, QBAR); end endmodule

Test Stimulus Code The design is checked by the stimulus as shown below. The module stimulus stimulates the D-Flip-Flop by applying a few input combinations and monitors the result.

Flip-flop will load data

Flip-flop will load data

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Simulation Result When clk =0, output keep previous value. Otherwise, clk=1 input value is loaded.

Simulation Waveform When clk =1, output is changed.