3DD 1e SyCers

ERSA ‘06ERSA ‘06

SyCERSa SystemC Design Exploration

Framework for SoC Reconfigurable Architecture

Monte Carlo Resort, Lav Vegas - NevadaMonte Carlo Resort, Lav Vegas - NevadaJune 29th, 2006June 29th, 2006

Carlo Amicucci: [email protected] Ferrandi: [email protected]

Marco D. Santambrogio: [email protected]

Donatella Sciuto: [email protected]

DRESD ProjectDRESD Project

OutlineOutline

IntroductionProblem definitionSyCERS: objectivesState of the ArtSystemC

ReasonsTLM

SyCERSMethodologyStructure

Reconfiguration Control InterfacesA reconfigurable component using SystemCSyCERS behavior

Case StudyThe Caronte ArchitectureThe SyCERS Caronte modelApplication

Canny Edge DetectorAdaptive Filter

SyCERS Performances

Concluding Remarks


OutlineOutline


ReasonsTLM





SyCERS Performances


The problemThe problem

Increasing the complexity of the design provides to the designers much more flexibility in their decisions but imply that the time to market of the final solution is also dramatically increasing.

The possibility of testing dynamic reconfigurable architectures and of validating dynamic reconfigurable systems build on top of these architectures becomes more relevant

The “problem” can be formulated in many ways:Given an architecture, maximize the system throughputGiven the system throughput find, the “correct” architecture

Or under the reconfiguration point of view: Minimizing the number of reconfigurationsMinimizing the reconfiguration overhead

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


SyCERS - ObjectivesSyCERS - Objectives

Define a novel model to describe reconfigurable systems

Based on know HDL (no new languages)To be used in the early first stage of the project; to consider the reconfiguration at the system level

Propose a complete framework for the simulation and the design of reconfigurable systems

Providing system specification that can be simulatedAllowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time Taking into account the software side of the final system

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


SoASoA

J. Stockwood and P. Lysaght. A simulation tool for dynamically reconfigurable field programmable gate arrays. In IEEE Transactions on VLSI systems, Vol. 4, No. 3, September 1996

I. Robertson and J. Irvine. A design flow for partially reconfigurable hardware. In ACM Transactions on Embedded Computing Systems, Vol. 3, No. 2, May 2004G. Habay P. Butel and A. Rachet. Managing partial dynamic reconfiguration in virtex-II Pro FPGAs. In Xilinx Xcell Journal, Fall 2004 – RECONF2 European Project

Brad Hutchings, Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, and Mike Rytting. A cad suite for high-performance FPGA design. In FCCM '99, pag. 12, Washington, DC, USA, 1999K. Masselos A. Pelkonen. System-level modelling of dynamically reconfigurable hardware with SystemC. In The 10th Reconfigurable Architectures Workshop, Nice, France, April 22, 2003Tero Rissa, Adam Donlin, and Wayne Luk. Evaluation of SystemC modelling of reconfigurable embedded systems. In DATE '05, pages 253--258, Washington, DC, USA, 2005

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


SystemC class librarySystemC class library

We can create a simulation model for both the hardware and the software components

SystemC is just a C++ class library we can still exploit all the language features:

Function pointersDynamic object instantiation…

Using master-slave communication library, complex system models can be built as an interconnection of sequentially communicating functional blocks where unnecessary implementation detail is abstracted.

A system description is basically a C/C++ program

The execution of a program, basically correspond to the system behavior simulation

SystemC Model

Simulation

Refinement

Synthesis

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


TLM e SystemCTLM e SystemC

In TLM the system is first described at an high level of abstraction where communication details are hiddenThe key concept of TLM is the separation of functionality definitions from communication details

to achieve this TLM uses through the concept of channelDEF.: SystemC channel is a class that implements one or more SystemC interface classes. A channel implements all the methods of the inherited interface classes. DEF.: A SystemC port is a class template with and inheriting from a SystemC interface. Ports allow access of channels across module boundaries. DEF.: A SystemC interface is an abstract class that provides only pure virtual declarations of methods referenced by SystemC channels and ports.

SystemC, starting from the 2.0 version, support TLM using the following structures:

write()read()

write()read()

module Amodule A

pA->write(v)pA->write(v)

module Bmodule B

v=pB->read()v=pB->read()

channel

pA pB

sc_interface

sc_port

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


OutlineOutline


ReasonsTLM





SyCERS Performances


The SyCERS methodologyThe SyCERS methodology

SpecificationModel

SpecificationModel

ComponentAssembly

Model

ComponentAssembly

Model

BusFunctional

Model

BusFunctional

Model

Define the system functionalityNo information regarding the final implementation

Solution space explorationProvides the functionalities implementation detailsNo information regarding the communication

Computed solution validation via the simulation

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


Reconfiguration Control InterfacesReconfiguration Control Interfaces

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


A reconfigurable component using A reconfigurable component using SystemCSystemC

It’s not possible to instantiate an sc_module during the simulation phaseIt’s possible to modify the SC_THREAD and the SC_METHOD via:

function pointersc_mutex

ConfigurationCombined with the reconfiguration time

ElaborationProvided with the elaboration time

*g()

Reconfigurable Component(sc_module)

Configuration(function pointer)

mutex

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


Reconfigurable component Reconfigurable component behaviorbehavior

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


OutlineOutline


ReasonsTLM





SyCERS Performances


Caronte - Caronte - ObjectivesObjectives

Propose a novel embedded partial reconfigurable architecture (RSoC)Define a complete methodology to port a generic application on the proposed architecture

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod-

> Aps

> SyCERS perf.

.:: Conclusions


Caronte ModelsCaronte Models

Control Code(SystemC)

Control Code(SystemC)

CompilerGCC

CompilerGCC

ConfigurationsBlackBox(SystemC)

ConfigurationConfiguration

Control Process

Control Process

Schedulerand Controller

Schedulerand Controller

MemoryModel

MemoryModel

ModelloMemoria

BlackBoxes

ModelCoreConnect

ModelCoreConnect

PowerPCISS

PowerPCISS

Open SystemC PowerPC core models

Cross Compiler GCC

Cross Compiler GCC

Control Code(C/C++)

Control Code(C/C++)

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


Caronte Functional ViewCaronte Functional View

«sc_module»PowerPC

«sc_module»IPCM

«sc_module»BlackBox

«sc_module»OPB Bus

«sc_module»PLB Bus

«sc_module»Bridge

«sc_module»Memory

«sc_module»Interrupt Controller

*1

1

*

1

*

«funzione»Configuration

*

1

Logger11

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


Canny Edge DetectorCanny Edge Detector

Caronte Component assemblySystem characterized by 4 functionalitiesSystem evaluation according to:

# BlackBoxesReconfiguration Time

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


Adaptive FilterAdaptive Filter

Caronte Component assemblySystem characterized by 5 functionalitiesSystem evaluation according to:

Reconfiguration TimeScheduling Policy

BB1

BB1

BB1

BB1

BB1

PE

time

F1

F2

F3

F4

F5

Reconfiguration Time

Elaboration DATA1

Elaboration DATA2

BB1

BB2

BB1

BB2

BB1

F1

PE

time

F2

F3

F4

F5

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


SyCERS PerformancesSyCERS Performances

Memory usage for the model150 KB for each reconfigurable components

The increment of the number of reconfigurable components does not affect the performances

0,00

50,00

100,00

150,00

200,00

250,00

300,00

1 2 3 4

# BlackBoxes

Tim

e (s

ec)

Optimized Version

Debugging Version

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


Concluding RemarksConcluding Remarks

ConclusionPreliminary results show that the SyCERS framework enables the exploitation of all benefits of a reconfigurable architecture

Future WorksFully support for the master-slave communication libraryFrom UML to SyCERSAutomatic generation of the SyCERS simulation model starting from a C/C++ specificationBus Functional Model, i.e. MP4FREE, GRAPESSyCERS V2 – completely documented for a free distribution

Status:

.:: Intro

> Problem

> Objectives

> SoA

> SystemC

.:: SyCERS

> Methodology

> Structure

.:: Case Study

> Caronte

> SyCERS mod.

> Aps

> SyCERS perf.

.:: Conclusions


QuestionsQuestions

3DD 1e SyCers

Technology

Transcript of 3DD 1e SyCers