3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step- Down ...For pricing, delivery, and ordering...

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

General DescriptionThe MAX1536 constant-off-time, pulse-width-modulated(PWM) step-down DC-to-DC converter is ideal for use in+5.0V and +3.3V to low voltages for notebook and sub-notebook computers. The MAX1536 features an internalPMOS power switch and internal synchronous rectifica-tion for high efficiency and reduced component count. Noexternal Schottky diode is required across the internalsynchronous rectifier switch. The internal 54mΩ PMOSpower switch and 47mΩ NMOS synchronous-rectifierswitch easily deliver continuous load currents up to 3.6A.The MAX1536 produces dynamically adjustable outputvoltages for chipsets and graphics processor cores usinga logic-level control signal. The MAX1536 achieves effi-ciencies as high as 96%.The MAX1536 uses a unique current-mode, constant-off-time, PWM control scheme. It has selectable IdleModeTM to maintain high efficiency during light-loadoperation, or fixed-PWM mode for low output ripple. Theprogrammable constant-off-time architecture allows awide range of switching frequencies up to 1.4MHz, opti-mizing performance trade-offs between efficiency, outputswitching noise, component size, and cost. TheMAX1536 features a digital soft-start to limit surge cur-rents during startup, a 100% duty-cycle mode for low-dropout operation, and a low-power shutdown mode thatdisconnects the input from the output and reduces supplycurrent below 1µA. The MAX1536 is available in a 28-pinthin QFN package with an exposed backside pad.

________________________Applications

Features♦ Dynamically Selectable Output Voltage from

+0.7V to VIN♦ Internal PMOS/NMOS Switches

54mΩ/47mΩ On-Resistance at VIN = +4.5V63mΩ/53mΩ On-Resistance at VIN = +3.0V

♦ +3.0V to +5.5V Input Voltage Range♦ 1.4MHz Maximum Switching Frequency♦ 2V ±0.75% Reference Output♦ Constant-Off-Time PWM Operation♦ Selectable Idle Mode/PWM Operation at Light

Loads♦ 100% Duty Factor in Dropout♦ Digital Soft-Start Inrush Current Limiting♦ <1µA Typical Shutdown Supply Current♦ <750µA Quiescent Supply Current♦ Thermal Shutdown♦ 1% VOUT Accuracy Over Line and Load♦ External Reference Input♦ Power-Good Window Comparator♦ Selectable Power-Good Blanking Time During

Output-Voltage Transition

19-2729; Rev 1; 8/05M

AX

15

36

3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-Down Regulator with Dynamic Output Voltage Control

________________________________________________________________ Maxim Integrated Products 1

Minimal Operating Circuit

Ordering Information

Idle Mode is a trademark of Maxim Integrated Products, Inc.

PART TEMP RANGE PIN-PACKAGE

MAX1536ETI -40oC to +85oC 28 Thin QFN 5mm x 5mm

MAX1536ETI+ -40oC to +85oC 28 Thin QFN 5mm x 5mm

MAX1536

IN

VCC

SKIP

TOFF

PGOOD

SHDN

COMP

LX

FB

PGND

AGND

REF

REFIN

VIN+3.0V TO +5.5V

VOUT+0.7V TO VIN

Pin Configuration

INLX IN

SHDN SKIP FB

COM

P

LX IN IN PGOO

D

FBLA

NK

V CC

AGND

PGND

LX

N.C.

LX

PGND

PGND REF

REFIN

OD

OD

GATE

TOFF

N.C.

TOP VIEW

THIN QFN

PGND

28

27

26

25

24

23

22

8

9

10

11

12

13

14

15161718192021

7654321

MAX1536

EXPOSED PADDLE

A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.

Chipset/Graphics Coreswith Dual-Supply Voltages

Active Termination Buses

Notebook Computers

DDR Memory Termination

EVALUATION KIT

AVAILABLE

+Denotes lead-free package.

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = 0°C to +85°C, unless otherwise noted. Typicalvalues are at TA = +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

VCC, IN, SHDN, SKIP to AGND ................................-0.3V to +6VOD, OD, GATE, PGOOD to AGND...........................-0.3V to +6VCOMP, FB, REF to AGND.........................................-0.3V to +6VTOFF, REFIN, FBLANK to AGND .............................-0.3V to +6VIN to VCC ...............................................................-0.3V to +0.3VPGND to AGND.................................................... -0.3V to +0.3VLX to PGND ................................................ -0.3V to (VIN + 0.3V)LX Current (Note 1).............................................................±5.7AREF Short Circuit to AGND.........................................Continuous

Continuous Power Dissipation (TA = +70°C)28-Pin Thin QFN (derated 20.8mW/°C above +70°C;part mounted on 1in2 of 1oz copper) .........................1667mW

Operating Temperature Range ...........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-65°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PWM CONTROLLER

Input Voltage VIN, VCC 3.0 5.5 V

Output Adjust Range VOUT VREFIN VIN V

TA = +25°C to +85°C -3 0 +3Feedback Voltage Accuracy

VFB -VREFIN

VCC = VIN = +3.0V to+5.5V, ILOAD = 0 TA = 0°C to +85°C -4 0 +4

mV

Feedback Load RegulationILOAD = 0 to 3.5A, VCC = VIN = +3.0V to +5.5V,SKIP = VCC

0.3 %

FB Input Bias Current IFB VFB = 1.01 × VREFIN -50 +50 nA

Dropout VDO VCC = VIN = +3.0V, ILOAD = 3A, FB = AGND 189 330 mV

VCC = VIN = +4.5V, ILOAD = 0.5A 54 90PMOS Switch On-Resistance RPMOS

VCC = VIN = +3.0V, ILOAD = 0.5A 63 110mΩ

VCC = VIN = +4.5V, ILOAD = 0.5A 47 80NMOS Switch On-Resistance RNMOS

VCC = VIN = +3.0V, ILOAD = 0.5A 53 90mΩ

Maximum Output Current IOU T ( R M S ) (Note 2) 3.6 A

Current-Limit Threshold ILIMIT (Note 3) 4.0 4.8 5.5 A

Idle Mode Current Threshold SKIP = AGND 0.21 0.60 1.00 A

Zero-Cross Current Threshold SKIP = AGND 200 mA

Switching Frequency fSW (Note 2) 1.4 MHz

RTOFF = 30.1kΩ 0.24 0.30 0.37

RTOFF = 110kΩ 0.85 1.00 1.15Off-Time tOFF VFB ≥ 0.3 × VREFIN

RTOFF = 499kΩ 3.8 4.5 5.2

µs

Extended Off-Time VFB < 0.3 × VREFIN 4 × tOFF µs

On-Time tON (Note 2) 0.3 µs

Soft-Start Time (Note 3) 3 × 256 Cycles

Quiescent Supply Current ICC + IIN SKIP = AGND, VFB = 1.01 × VREFIN 350 750 µA

Note 1: LX has clamp diodes to PGND and IN. Thermal limits dictate the maximum continuous current through these diodes.

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_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = 0°C to +85°C, unless otherwise noted. Typicalvalues are at TA = +25°C.)


ICC + IINSHDN = AGND; current into VCC and IN;LX = 0 or +3.3V

0.2 20

IIN SHDN = AGND; current into IN; LX = 0 0.2 20Shutdown Supply Currents

ILX SHDN = AGND; current into LX; LX = +3.3V 0.1 20

µA

REFERENCE

REF Voltage VREF VCC = VIN = +3.0V to +5.5V 1.985 2.000 2.015 V

REF Load Regulation IREF = -1µA to +50µA 10 mV

REFIN Input Voltage Range VREFIN V C C = V IN = + 3.0V to + 5.5V , V C C > V RE F IN + 1.35V 0.7 2.0 V

REFIN Input Bias Current IREFIN VREFIN = 1.5V, VFB = 1.01 × VREFIN -50 +50 nA

FAULT DETECTION

Thermal Shutdown TSHDN Rising, hysteresis = 15°C 165 °C

VCC and VIN rising, hysteresis 60mV typical 2.4 2.6 2.8

VCC - VREFIN, VCC rising, hysteresis 60mV typical 0.9 1.35Undervoltage LockoutThreshold

VCC - VFB, VCC rising, hysteresis 60mV typical 0.9 1.35

V

PGOOD Lower Trip Threshold No load, falling edge, hysteresis = 1% (Note 4) -12.5 -10 -8.0 %

PGOOD Upper Trip Threshold No load, rising edge, hysteresis = 1% (Note 4) +8.0 +10 +12.5 %

PGOOD Propagation Delay tPGOOD FB forced 2% beyond PGOOD trip threshold 5 µs

PGOOD Output Low Voltage ISINK = 1mA 0.1 V

PGOOD Leakage Current High-impedance state, forced to +5.5V 1 µA

FBLANK = VCC 112 150 188

FBLANK = open or AGND 75 100 125Fault Blanking Time tFBLANK

FBLANK = REF 37 50 63

µs

INPUTS AND OUTPUTS

SHDN, SKIP, GATE, VIN = VCC = +3.3V,rising edge, hysteresis = 100mV

0.9 1.3 1.6

Logic Input ThresholdV SHDN,V SKIP,VGATE SHDN, SKIP, GATE, VIN = VCC = +5.0V,

rising edge, hysteresis = 100mV1.15 1.55 1.95

V

Logic Input Current SHDN, SKIP, GATE -0.5 +0.5 µA

FBLANK = VCC VCC - 0.2

FBLANK = REF 1.8 2.2

FBLANK = open 0.8 1.2FBLANK Logic Thresholds VFBLANK

FBLANK = AGND 0.2

V

FBLANK Input Current IFBLANK FBLANK forced to AGND or VCC -5 +5 µA

OD On-Resistance ROD GATE = VCC 10 25 ΩOD Leakage Current GATE = AGND, VOD = +5.5V -50 +50 nA

OD On-Resistance R OD GATE = AGND 10 25 ΩOD Leakage Current GATE = VCC, V OD = +5.5V -50 +50 nA

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4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)


PWM CONTROLLER

Input Voltage VIN, VCC 3.0 5.5 V

Feedback Voltage AccuracyVFB -

VREFINVCC = VIN = +3.0V to +5.5V, ILOAD = 0 -4 +4 mV

FB Input Bias Current IFB VFB = 1.01 × VREFIN -50 +50 nA

Dropout VDO VCC = VIN = +3.0V, ILOAD = 3A, FB = AGND 330 mV

VCC = VIN = +4.5V, ILOAD = 0.5A 90PMOS Switch On-Resistance RPMOS

VCC = VIN = +3.0V, ILOAD = 0.5A 110mΩ

VCC = VIN = +4.5V, ILOAD = 0.5A 80NMOS Switch On-Resistance RNMOS

VCC = VIN = +3.0V, ILOAD = 0.5A 90mΩ

Maximum Output Current IOU T ( R M S ) (Note 2) 3.6 A

Current-Limit Threshold ILIMIT (Note 3) 4.0 5.7 A

Idle Mode Current Threshold SKIP = AGND 0.21 1.00 A

Switching Frequency fSW (Note 2) 1.4 MHz

RTOFF = 30.1kΩ 0.24 0.37

RTOFF = 110kΩ 0.85 1.15Off-Time tOFF VFB ≥ 0.3 × VREFIN

RTOFF = 499kΩ 3.8 5.2

µs

On-Time tON (Note 2) 0.3 µs

Quiescent Supply Current ICC + IIN SKIP = AGND, VFB = 1.01 × VREFIN 750 µA

ICC + IINSHDN = AGND; current into VCC and IN;LX = 0 or +3.3V

20

IIN SHDN = AGND; current into IN; LX = 0 20Shutdown Supply Currents

ILX SHDN = AGND; current into LX; LX = +3.3V 20

µA

REFERENCE

REF Voltage VREF VCC = VIN = +3.0V to +5.5V 1.98 2.02 V

REFIN Input Voltage Range VREFINVCC = VIN = +3.0V to +5.5V,VCC > VREFIN + 1.35V

0.7 2.0 V

FAULT DETECTION

PGOOD Lower Trip Threshold No load, falling edge, hysteresis = 1% (Note 4) -12.5 -8 %

PGOOD Upper Trip Threshold No load, rising edge, hysteresis = 1% (Note 4) +8 +12.5 %

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_______________________________________________________________________________________ 5

Note 2: Guaranteed by design and not production tested.Note 3: To limit input surge currents, the current-limit threshold is set to 25% of its final value (25% x 4.8A = 1.2A) when the

MAX1536 is enabled or powered up. The current-limit threshold is increased by 25% every 256 LX cycles. The current-limitthreshold is at its final level of 4.8A after 768 LX cycles. See the Internal Soft-Start Circuit section.

Note 4: The upper and lower PGOOD thresholds are expressed as a ratio of VFB with respect to VREFIN.

Note 5: Specifications to -40°C are guaranteed by design and are not production tested.

V VV

xFB REFIN

REFIN

-100%

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)


INPUTS AND OUTPUTS

SHDN, SKIP, GATE, VIN = VCC = +3.3V,rising edge, hysteresis = 100mV

0.9 1.6

Logic Input ThresholdV S HDN,V S KIP,V GATE SHDN, SKIP, GATE, VIN = VCC = +5.0V,

rising edge, hysteresis = 100mV1.15 1.95

V

FBLANK = VCC VCC - 0.2

FBLANK = REF 1.8 2.2

FBLANK = open 0.8 1.2FBLANK Logic Thresholds VFBLANK

FBLANK = AGND 0.2

V

OD On-Resistance ROD GATE = VCC 25 ΩOD On-Resistance R O D GATE = AGND 25 Ω

100

00.001 0.01 0.1 1 10

EFFICIENCY vs. OUTPUT CURRENT(VIN = 5V, L = 1.5µH)

20

MAX

1536

toc0

1

OUTPUT CURRENT (A)

EFFI

CIEN

CY (%

)

40

60

80

70

50

30

10

90

VOUT = 0.7VRTOFF = 200kΩ

VOUT = 1.8VRTOFF = 93.1kΩ


PWM MODEIDLE MODE

1.806

1.7940.001 0.1 10.01 10

OUTPUT VOLTAGE vs. OUTPUT CURRENT(VIN = 5V, L = 1.5µH)

MAX

1536

toc0

2

OUTPUT CURRENT (A)

OUTP

UT V

OLTA

GE (V

)

1.796

1.798

1.800

1.802

1.804

RTOFF = 93.1kΩ

PWM MODEIDLE MODE

100

00.001 0.01 0.1 1 10

EFFICIENCY vs. OUTPUT CURRENT(VIN = 3.3V, L = 1.2µH)

20

MAX

1536

toc0

3

OUTPUT CURRENT (A)

EFFI

CIEN

CY (%

)

40

60

80

70

50

30

10

90




PWM MODEIDLE MODE

Typical Operating Characteristics(MAX1536 Circuit of Figure 1, TA = +25°C, unless otherwise noted.)

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6 _______________________________________________________________________________________

1.806

1.7940.001 0.1 10.01 10

OUTPUT VOLTAGE vs. OUTPUT CURRENT(VIN = 3.3V, L = 1.2µH)

MAX

1536

toc0

4

OUTPUT CURRENT (A)

OUTP

UT V

OLTA

GE (V

)

1.796

1.798

1.800

1.802

1.804

RTOFF = 75kΩ

PWM MODEIDLE MODE

100

00.001 0.01 0.1 1 10

EFFICIENCY vs. OUTPUT CURRENT(VOUT = 1.8V, fSW = 300kHz)

20

MAX

1536

toc0

5

OUTPUT CURRENT (A)EF

FICI

ENCY

(%)

40

60

80

70

50

30

10

90

VIN = 5VL = 3.3µHRTOFF = 221kΩ

VIN = 3.3VL = 2.2µHRTOFF = 147kΩ

PWM MODEIDLE MODE

100

00.001 0.01 0.1 1 10

EFFICIENCY vs. OUTPUT CURRENT(VIN = 3.3V, VOUT = 1.8V)

20

MAX

1536

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6

OUTPUT CURRENT (A)

EFFI

CIEN

CY (%

)

40

60

80

70

50

30

10

90

L = 3.3µHRTOFF = 178kΩfSW ≈ 250kHz

L = 1.5µHRTOFF = 85kΩfSW ≈ 500kHz

PWM MODEIDLE MODE

L = 0.8µHRTOFF = 41.2kΩfSW ≈ 1000kHz

SWITCHING FREQUENCY vs. OUTPUT CURRENT

MAX

1536

toc0

7

OUTPUT CURRENT (A)

f SW

(kHz

)

4321

100

200

300

400

500

600

700

800

900

1000

00 5

PWM MODEIDLE MODE

VIN = 5.0V

VIN = 3.3V

VOUT = 1.8V

NO-LOAD SUPPLY CURRENTvs. INPUT VOLTAGE (PWM MODE)

MAX1536 toc08

INPUT VOLTAGE (V)

I IN (m

A)

I CC

(mA)

4.54.03.5

5

10

15

20

25

0

0.2

0.4

0.6

0.8

1.0

03.0 5.0

VOUT = 1.8VIIN

ICC

NO-LOAD SUPPLY CURRENTvs. INPUT VOLTAGE (IDLE MODE)

MAX1536 toc09

INPUT VOLTAGE (V)

I IN (µ

A)

I CC

(µA)

4.54.03.5

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

0.95

305

310

315

320

325

330

335

340

345

350

3003.0 5.0

VOUT = 1.8V

IIN

ICC

Typical Operating Characteristics (continued)(MAX1536 Circuit of Figure 1, TA = +25°C, unless otherwise noted.)

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_______________________________________________________________________________________ 7

Typical Operating Characteristics (continued)(MAX1536 Circuit of Figure 1, TA = +25°C, unless otherwise noted.)

STARTUP AND SHUTDOWN(HEAVY LOAD)

MAX1536 toc10

400µs/div

VSHDN5V/divVPGOOD5V/div

ILX2A/div

VOUT1V/div

VIN = 3.3V, VOUT = 1.8V, RLOAD = 0.5Ω

STARTUP AND SHUTDOWN(LIGHT LOAD)

MAX1536 toc11

400µs/div

VSHDN5V/divVPGOOD5V/div

ILX1A/div

VOUT1V/div

VIN = 3.3V, VOUT = 1.8V, RLOAD = 3Ω

LOAD-TRANSIENT RESPONSE(PWM MODE)

MAX1536 toc12

20µs/div

IOUT2A/div

ILX2A/div

VOUT50mV/div

VLX5V/div

VIN = 3.3V, VOUT = 1.8V, IOUT = 0.1A TO 3A TO 0.1A

LOAD-TRANSIENT RESPONSE(IDLE MODE)

MAX1536 toc13

20µs/div

IOUT2A/div

ILX2A/div

VOUT50mV/div

VLX5V/div

VIN = 3.3V, VOUT = 1.8V, IOUT = 0.1A TO 3A TO 0.1A

DYNAMIC OUTPUT-VOLTAGE TRANSITION(IDLE MODE)

MAX1536 toc14

20µs/div

VGATE5V/div

VLX5V/div

VOUT200mV/div

VREFIN200mV/div

ILX5A/div

0

VIN = 3.3V, VOUT = 1.5V TO 1.8V TO 1.5V, FBLANK = REF, ILOAD = 0.1A

REFERENCE VOLTAGE vs. TEMPERATURE

MAX

1536

toc1

5

TEMPERATURE (°C)

V REF

(V)

603510-15

1.997

1.998

1.999

2.000

2.001

2.002

1.996-40 85

VIN = 3.3V IREF = 0

IREF = 50µA

IREF = 25µA

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8 _______________________________________________________________________________________

Pin DescriptionPIN NAME FUNCTION

1, 21,24, 26

LXInductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifierswitch. Connect all LX pins together.

2, 3,19, 20

IN Power Input. Power input for the internal PMOS switch. Connect all IN pins together.

4 SHDNShutdown Control Input. Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs.Drive SHDN high or connect to VCC for normal operation.

5 SKIPPulse-Skipping Control Input. Connect SKIP to VCC for low-noise, forced-PWM mode. Connect SKIP to AGNDfor high-efficiency Idle Mode.

6 FB Feedback Input. The voltage at REFIN sets the feedback regulation voltage (VFB = VREFIN).

7 COMPIntegrator Compensation. Connect a 470pF capacitor from COMP to VCC for integrator compensation.See the Integrator Amplifier section.

8, 25 N.C. No Connection. Not internally connected. Connecting pin 25 to LX eases PC board layout.

9 TOFFOff-Time Select Input. Sets the PMOS power switch off-time during constant off-time operation. Connect aresistor from TOFF to AGND to adjust the PMOS switch off-time. See the Programming the No-Load SwitchingFrequency and Off-Time section.

10 GATEBuffered OD and OD Control Input. A logic low on GATE forces OD low and OD high impedance. A logic highon GATE forces OD high impedance and OD low.

11 OD Open-Drain Output. A logic low on GATE forces OD high impedance. A logic high on GATE forces OD low.

12 ODInverted Open-Drain Output. A logic low on GATE forces OD low. A logic high on GATE forces OD highimpedance.

13 REFIN External Reference Input. The voltage at REFIN sets the feedback regulation voltage (VFB = VREFIN).

14 REF+2.0V Reference Voltage Output. Bypass REF to AGND with a minimum capacitance of 0.22µF. REF suppliesup to 50µA for external loads. The internal reference turns off in shutdown.

15 AGND Analog Ground. Connect backside pad to AGND.

16 VCCAnalog Power Input. Power input to the internal analog circuitry. Bypass VCC with a 10Ω and 2.2µF (min)lowpass filter (Figure 1).

17 FBLANK

Fault-Blanking Control Input. FBLANK is a four-level logic input that enables or disables fault blanking, and setsthe minimum forced-PWM operation time (tFBLANK). Enabling fault blanking forces PGOOD high for the selectedtime period after a transition is detected on GATE. Additionally, the controller enters forced-PWM mode for theduration of tFBLANK anytime GATE changes states. Connect FBLANK to the following pins to select tFBLANK andfault blanking:VCC = 150µs (typ), fault blanking enabledOpen = 100µs (typ), fault blanking enabledREF = 50µs (typ), fault blanking enabledAGND = 100µs (typ), fault blanking disabled

18 PGOOD

Open-Drain Power-Good Output. PGOOD is low during soft-start, in shutdown, and when the output voltage ismore than 10% (typ) above or below the normal regulation point. After the soft-start, PGOOD becomes highimpedance if the output is in regulation. PGOOD is blanked—forced into a high-impedance state—whenFBLANK is enabled and a transition is detected on GATE.

22, 23,27, 28

PGNDPower Ground. Internally connected to the source of the internal NMOS synchronous-rectifier switch.Connect all PGND pins together.

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_______________________________________________________________________________________ 9

Standard Application CircuitThe MAX1536 standard application circuit (Figure 1)generates a dynamically adjustable output voltage typicalof graphic processor core requirements. See Table 1for component selections. Table 2 lists the componentmanufacturers.

Detailed DescriptionThe MAX1536 synchronous, current-mode, constant-off-time, PWM DC-to-DC converter steps down an inputvoltage (VIN) from +3.0V to +5.5V to an output voltagefrom +0.7V to VIN. The MAX1536 output delivers up to3.6A of continuous current. An internal 54mΩ PMOSpower switch and an internal 47mΩ NMOS synchro-nous rectifier switch improve efficiency, reduce compo-nent count, and eliminate the need for an externalSchottky diode (Figure 2).

Modes of OperationThe MAX1536 has two modes of operation: constant-off-time PWM mode, and pulse-skipping Idle Mode.The logic level on the SKIP input and the currentthrough the PMOS switch determine the MAX1536mode of operation.

Forced-PWM mode keeps the switching frequency rel-atively constant and is desirable in applications thatmust always keep the frequency of conducted andradiated emissions in a narrow band. Visit Maxim’swebsite at www.maxim-ic.com for more information onhow to control electromagnetic interference (EMI).Pulse-skipping Idle Mode has a dynamic switching fre-quency under light loads and is desirable in applica-tions that require high efficiency at light loads.

Forced-PWM Mode (SKIP = VCC)Connect SKIP to VCC to force the MAX1536 to operatein low-noise, constant-off-time PWM mode. Constant-off-time PWM architecture provides a relatively con-stant switching frequency (see the Frequency Variationwith Output Current section). A single resistor (RTOFF)sets the PMOS power switch off-time that results in aswitching frequency up to 1.4MHz optimizing perfor-mance trade-offs in efficiency, switching noise, compo-nent size, and cost.

PWM mode regulates the output voltage by increasingthe PMOS switch on-time to increase the amount of energytransferred to the load per cycle. At the end of each off-time, the PMOS switch turns on and remains on until theoutput is in regulation or the current through the switchincreases to the 4.8A current limit. When the PMOSswitch turns off, it remains off for the programmed off-time (tOFF), and the NMOS synchronous switch turns on.

The NMOS switch remains on until the end of tOFF. Sinceeither the NMOS or the PMOS switch is always on inPWM mode, the inductor current is continuous.

Idle Mode (SKIP = AGND)Connect SKIP to AGND to allow the MAX1536 to auto-matically switch between high-efficiency Idle Modeunder light loads and PWM mode under heavy loads.The transition from PWM mode to Idle Mode occurswhen the load current is half the Idle Mode currentthreshold (600mA typ).

In Idle Mode operation, the switching frequency isreduced to increase efficiency. The inductor current isdiscontinuous in this mode and the MAX1536 only initi-ates an LX switching cycle when VFB < VREFIN. WhenVFB falls below VREFIN, the PMOS switch turns on andremains on until output is in regulation and the currentthrough the switch increases to the Idle Mode currentthreshold (600mA typ). When the PMOS switch turnsoff, the NMOS synchronous switch turns on and remainson until the current through the switch decreases to thezero-cross-current threshold of 200mA.

100% Duty-Cycle OperationWhen the input voltage drops near the output voltage,the LX duty cycle increases until the PMOS switch is oncontinuously. The dropout voltage in 100% duty cycleis the output current multiplied by the on-resistance ofthe internal PMOS switch and parasitic resistance inthe inductor. The PMOS switch remains on continuouslyas long as the current limit is not reached.

Internal Soft-Start CircuitSoft-start allows a gradual increase of the current-limitlevel at startup to reduce input surge currents. Whenthe MAX1536 is enabled or powered up, its current-limit threshold is set to 25% of its final value (25% of4.8A = 1.2A). The current-limit threshold is increasedby 25% every 256 LX cycles. The current-limit thresh-old reaches its final level of 4.8A after 768 LX cycles orwhen the output voltage is in regulation, whicheveroccurs first. Additionally, when VFB < 0.3 × VREFIN, thePMOS switch remains off for the extended off-time of 4 ×tOFF. As a result of this soft-start feature, the main outputcapacitor charges up relatively slowly. The exact time ofthe output rise depends on the nominal switching fre-quency, output capacitance, and the load current. Seethe startup waveforms in the Typical OperatingCharacteristics.

Short-Circuit/Overload ProtectionThe MAX1536 can sustain a constant short circuit oroverload. Under a short-circuit or overload condition,when VFB < 0.3 × VREFIN, the MAX1536 uses an

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10 ______________________________________________________________________________________

LX

FB

PGND

AGND

REF

REFIN

OD

OD

GATE

IN

FBLANK

VCC

SKIP

TOFF

PGOOD

SHDN

COMP

MAX1536

OFF

IDLE MODE

RTOFF75kΩ

POWER GOOD

PWM MODE

100kΩ

10Ω

2.2µF

CIN2 X 10µF+6.3V X5R

CCOMP470pF

VIN+3.0V TO +5.5V

VFB(HIGH)

ON

VFB(LOW)

R1

R2

R3

RA

RB

CREF0.22µF

CREFIN470pF

L11.2µH, SUMIDA

CDR7D28MN-1R2

COUT100µF, +6.3VPOSCAP

VOUT+0.7V TO VIN

VOUT = VFB (1 + RA)

RB

VFB(HIGH) = VREF ( R2 + R3 ) R1 + R2 + R3

VFB(LOW) = VREF ( R2 ) R1 + R2

Table 1. Recommended Component Values (IOUT = 3.6A)

VIN (V) VOUT (V)FULL-LOAD SWITCHING

FREQUENCYfPWM (kHz)

L (µH) R TOF F ( k Ω) R1 (kΩ) R2 (kΩ) R3 (kΩ) RA (kΩ) RB (kΩ)

5 3.3* 1020 1.2 30.1 Short Open Open 6.49 10

5 2.5* 1020 1.2 47.5 Short Open Open 2.49 10

5 1.8/1.5** 820/900 1.2 78.7 20 60.4 121 Short Open

5 0.7* 450 1.2 200 130 69.8 Short Short Open

3.3 2.5* 640 1.0 30.1 Short Open Open 2.49 10

3.3 1.8/1.5** 840/1030 1.0 49.9 20 60.4 121 Short Open

3.3 0.7* 660 1.0 121 130 69.8 Short Short Open

*In single-output voltage applications, OD, OD, and GATE are general-purpose gates. If OD and OD are not used, connect GATE toAGND and leave OD and OD open.

**The output voltage changes between two set points depending on VGATE. See the Setting Dynamic Output Voltages with REFIN section.

Figure 1. MAX1536 Standard Application Circuit

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______________________________________________________________________________________ 11

extended off-time to control the current. Operation dur-ing a short-circuit or overload is similar to forced-PWMmode except the off-time is 4 × tOFF. At the end of eachoff-time, the PMOS switch turns on and remains on untilthe output is in regulation or the current through theswitch increases to the 4.8A current limit. When thePMOS switch turns off, it remains off for four times theprogrammed off-time (tOFF), and the NMOS synchro-

nous switch turns on. Since either the NMOS or thePMOS switch is always on, the inductor current is con-tinuous. The RMS inductor current during a short circuitremains below the 4.8A current-limit threshold. TheMAX1536 operates using the extended off-time until theshort-circuit or overload is removed and VFB > 0.3 ×VREFIN. Prolonged short circuit or overload can result inthermal shutdown.

Table 2. Component ManufacturersSUPPLIER COMPONENT PHONE WEBSITE

Coilcraft Inductors 800-322-2645 (USA) www.coilcraft.com

Coiltronics Inductors 561-752-5000 (USA) www.coiltronics.com

Kemet Capacitors 408-986-0424 (USA) www.kemet.com

Sanyo Capacitors 818-998-7322 (USA) www.sanyo.com

Sumida Inductors 408-982-9660 (USA) www.sumida.com

Taiyo Yuden Capacitors03-3667-3408 (Japan),408-573-4150 (USA)

www.t-yuden.com

TDK Capacitors847-803-6100 (USA),

81-3-5201-7241 (Japan)www.component.tdk.com

TOKO Inductors 858-675-8013 (USA) www.toko.com

Figure 2. MAX1536 Functional Diagram

PGOODCOMPARATOR

Gm

MAX1536

FBLANKDECODE AND

TIMER

2.0VREF

TIMER

CURRENTSENSE

PWM LOGICAND

DRIVERS

CURRENTSENSE PGND

LXL

COUT

VOUT+0.7V TO VIN

IN

CIN

VIN

VIN+3.0V TO +5.5V

*FB

SHDN VCC

VCC

COMPPGOOD

REF

REFIN

OD

OD

GATE

FBLANK REF AGND TOFF SKIP

FB

SUMMINGCOMPARATOR

*FOR VOUT > 2.0V, USE AN FB RESISTIVE DIVIDER*FROM VOUT TO AGND.

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12 ______________________________________________________________________________________

NONSYNCHRONOUS STEP-DOWN SWITCHING REGULATOR

VIN

VOUT

CIN

COUT

L

SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR

VIN

VOUT

CIN

COUT

L

SYNCHRONOUSRECTIFIER

Figure 3. Step-Down Switching Regulator

Shutdown (SHDN)Drive SHDN low to disable the MAX1536 and reducethe supply current to less than 1µA. In shutdown, all cir-cuitry and internal MOSFETs turn off, and the LX nodebecomes high impedance. Drive SHDN high or con-nect to VCC for normal operation.

Summing ComparatorThree signals are added together at the input of thesumming comparator (Figure 2): an output-voltageerror signal relative to the reference voltage, an inte-grated output-voltage error signal, and the sensedPMOS switch current. The transconductance amplifierwith an external capacitor between COMP and VCCprovides an integrated error signal. This integrator pro-vides high DC accuracy without the need for a high-gain amplifier (see the Integrator Amplifier section).

Power-Good Output (PGOOD)PGOOD is an open-drain output that indicates if theoutput voltage is in regulation. PGOOD is actively heldlow in shutdown and during soft-start. After the soft-start terminates, PGOOD becomes high impedance aslong as the output voltage is within ±10% of the nominalregulation voltage.

Once the MAX1536 has started, PGOOD pulls low whenthe output voltage drops 10% below or rises 10% abovethe nominal regulation voltage. PGOOD returns to highimpedance when the output voltage regains regulation.For logic-level output voltages, connect a 100kΩ externalpullup resistor between PGOOD and VCC.

PGOOD is forced high impedance during the transitionperiod selected by FBLANK (see the Fault Blankingsection).

Fault Blanking (FBLANK)The MAX1536 automatically enters forced-PWM opera-tion for a predefined period following any GATE transi-tion. The FBLANK control input determines how long theMAX1536 maintains forced-PWM operation (Table 3).

When fault blanking is enabled (FBLANK = VCC, open,or REF), the MAX1536 forces PGOOD to a high-imped-ance state during the transition period selected byFBLANK (Table 3). This prevents the PGOOD signalfrom going low when the output-voltage change(∆VOUT) cannot occur as fast as the change in REFINvoltage (∆VREFIN).

Synchronous RectificationIn a nonsynchronous step-down regulator, an externalSchottky diode provides a path for current to flow whenthe inductor is discharging. The MAX1536 synchronousrectifier replaces the external Schottky diode with aninternal low-resistance NMOS switch reducing conduc-tion losses and improving efficiency (Figure 3). There istypically 40ns of delay between MOSFET transitions,thus preventing cross conduction or “shoot through.”

FBLANK FAULT BLANKINGTYPICAL FORCED-PWM

DURATION (µs)

VCC Enabled 150

Open Enabled 100

REF Enabled 50

AGND Disabled 100

Table 3. FBLANK Configuration Table

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______________________________________________________________________________________ 13

Thermal ShutdownThe MAX1536 features a thermal fault-protection circuit.When the junction temperature rises above +165°C, athermal sensor shuts down the MAX1536 regardless ofV SHDN. The MAX1536 is reactivated after the junctiontemperature cools to +150°C.

Thermal ResistanceJunction-to-ambient thermal resistance, θJA, is highlydependent on the amount of copper area connected tothe exposed backside pad. Airflow over the board sig-nificantly reduces θJA. For heat-sinking purposes, even-ly distribute the copper area connected at the IC amongthe high-current pins. Refer to the Maxim website(www.maxim-ic.com) for QFN thermal considerations.

Power DissipationPower dissipation in the MAX1536 is dominated byconduction losses in the two internal power switches.Power dissipation due to supply current in the controlsection and average current used to charge and dis-charge the gate capacitance of the internal switches(i.e., switching losses—PSL) is approximately:

PSL = C x VIN2 x fSW

where:

C = 5nF.

fSW = switching frequency.

The combined conduction losses (PCL) in the twopower switches are approximated by:

PCL = IOUT2 x RPMOS

where:

IOUT = load current.

RPMOS = PMOS switch on-resistance.

The junction-to-ambient thermal resistance required todissipate this amount of power is calculated by:

where:

θJA = junction-to-ambient thermal resistance.

TJ(MAX) = maximum junction temperature = +150°C.

TA(MAX) = maximum ambient temperature.

Design ProcedureFor typical applications, use the recommended compo-nent values in Table 1. For other applications, take thefollowing steps:

1) Select the desired PWM-mode switching frequency.See Figure 4 for maximum operating frequency.

2) Select the constant off-time as a function of inputvoltage, output voltage, and switching frequency.

3) Select RTOFF as a function of off-time.

4) Select the inductor as a function of output voltage,off-time, and peak-to-peak inductor current.

Setting the Output VoltageSetting VOUT with a Resistive Voltage-Divider at FB

The MAX1536 output voltage (VOUT) is set using FBand REFIN (Figure 5). The MAX1536 regulates VFB tobe equal to VREFIN. Connect FB to a resistive voltage-divider between VOUT and AGND to adjust VOUT from+0.7V to VIN. Select an RB from 10kΩ to 100kΩ, thencalculate RA based on the desired VOUT:

θJAJ MAX A MAX

SL CL

T TP P

≤+

( ) ( )-

MAX1536

LX

PGND

FB

AGND

REF

REFIN

RB10kΩ

RA2.49kΩ

VOUT = VFB (1 + RA)

RB

VREF = +2.0V

CREF 0.22µF

VOUT = +2.5V

VFB = VREFIN

Figure 5. Setting VOUT with a Resistive Voltage-Divider at FB

VIN (V)

FREQ

UENC

Y (k

Hz)

5.04.54.03.5

200

400

600

800

1000

1200

1400

1600

1800

03.0 5.5

VOUT = 1.5VVOUT = 1.8V

VOUT = 2.5V

VOUT = 3.3V

VOUT = 1.0V

NO LOAD

Figure 4. Maximum Recommended Operating Frequency vs.Input Voltage

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14 ______________________________________________________________________________________

where VFB = VREFIN.

Setting Dynamic Output Voltages with REFINThe MAX1536 regulates VFB to be equal to VREFIN.Changing VREFIN allows for a dynamic output voltagethat changes between two set points (see theMultioutput Voltage Settings section for information onthree or more output-voltage set points). Figure 1 showsa dynamically adjustable resistive voltage-divider net-work at REFIN. Keep VREFIN between 0.7V and 2V.Keep VREFIN below VCC - 1.35V to avoid an undervolt-age lockout condition. Toggling GATE switches in andout the resistor connected between OD and AGNDchanging VREFIN. A logic high on GATE turns on theinternal N-channel MOSFET, forcing OD to a low-imped-ance state. A low logic on GATE turns off the internal N-channel MOSFET, making OD high impedance. Theoutput voltage is determined by the following equations:

The MAX1536 automatically enters forced-PWM opera-tion on the rising and falling edges of GATE, andremains in forced-PWM mode for a minimum timeselected by FBLANK (Table 3). Forced-PWM operationis required to ensure fast, accurate negative voltagetransitions when REFIN is lowered. Since forced-PWMoperation disables the zero-crossing comparator, theinductor current can reverse under light loads, quicklydischarging the output capacitors. The MAX1536 alsoforces PGOOD to a high-impedance state for the peri-od selected by FBLANK (Table 3).

For a step-voltage change at REFIN, the rate of changeof the output voltage is limited by the inductor currentramp, the total output capacitance, the current limit,and the load during the transition. The voltage acrossthe inductor and the inductance limits the inductor cur-rent ramp. The total output capacitance determineshow much current is needed to change the output volt-age. Additional load current slows down the output volt-age change during a positive REFIN voltage change,

and speeds up the output voltage change during anegative REFIN voltage change.

Adding a capacitor across REFIN and AGND filtersnoise and controls the rate of change of the REFIN volt-age during dynamic transitions. With the additionalcapacitance, the REFIN voltage slews between the twoset points with a time constant given by the equivalentparallel resistance seen by the slew capacitor CREFIN.As shown in Figure 1, the time constant for a positiveREFIN voltage transition is:

and the time constant for a negative REFIN voltagetransition is:

During a negative REFIN voltage transition, the MAX1536sinks current to discharge the output capacitor and bringthe output voltage down to the new set point. TheMAX1536 does not have a negative current limit, soτNEG must be set long enough to keep the sinking cur-rent within the maximum current capability of the IC:

Programming the No-Load SwitchingFrequency and Off-Time

The MAX1536 features a programmable PWM modeswitching frequency, which is set by the input and out-put voltage and the value of RTOFF. RTOFF sets thePMOS power switch off-time in PWM mode. Use the fol-lowing equation to select the off-time according to thedesired no-load switching frequency in PWM mode:

where:

tOFF = the programmed off-time.

VIN = the input voltage.

VOUT = the output voltage.

fPWM = no-load switching frequency, PWM mode.

Select RTOFF according to the formula:

tV Vf x V

OFFIN OUT

PWM IN=

-

τNEGOUT OUT

SINKSINK LIMIT

C x VI

and I I≥ ≤∆

τNEG REFINR x RR R

C=+

1 21 2

τPOS REFINR x R R

R R RC=

+( )+ +

1 2 3

1 2 3

V VRR

V VR

R R

V VR R

R R R

OUT FBA

B

FB LOW REF

FB HIGH REF

= +

=+

=+

+ +

1

21 2

2 31 2 3

( )

( )

R RVV

A BOUT

FB=

-1

14 ______________________________________________________________________________________

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______________________________________________________________________________________ 15

VTOFF is typically 1.1V and the recommended valuesfor RTOFF range from 30.1kΩ to 499kΩ for off-times of0.3µs to 4.5µs.

Frequency Variation with Output CurrentThe operating frequency of the MAX1536 in PWM modeis determined primarily by tOFF (set by RTOFF), VIN, andVOUT as shown in the following formula:

where:

VPMOS = the voltage drop across the internal PMOSpower switch, IOUT × RPMOS.

VNMOS = the voltage drop across the internal NMOSsynchronous-rectifier switch, IOUT × RNMOS.

As the output current increases, VNMOS and VPMOSincrease and the voltage across the inductor decreas-es. This causes the frequency to drop. Approximate thechange in frequency with the following formula:

where RPMOS is the resistance of the internal MOSFETs(54mΩ, typ).

Inductor SelectionThe key inductor parameters must be specified: induc-tor value (L) and peak current (IPEAK). The followingequation includes a constant, denoted as LIR, which isthe ratio of peak-to-peak inductor AC ripple current tomaximum DC load current. A higher value of LIR allowssmaller inductance but results in higher losses and rip-ple. A good compromise between size and losses isfound at approximately a 25% ripple-current to load-current ratio (LIR = 0.25), which corresponds to a peak-inductor current 1.125 times the DC load current:

where:

IOUT = maximum DC load current.

LIR = ratio of peak-to-peak AC inductor current to DCload current, typically 0.25.

The peak-inductor current at full load is 1.125 × IOUT ifthe above equation is used; otherwise, the peak currentis calculated by:

Choose an inductor with a saturation current at least ashigh as the peak-inductor current. The inductor select-ed should exhibit low losses at the chosen operatingfrequency.

Capacitor SelectionThe input-filter capacitor reduces peak currents andnoise at the voltage source. Use a low-ESR and low-ESL capacitor located no further than 5mm from IN.Select the input capacitor according to the RMS inputripple-current requirements and voltage rating:

where IRIPPLE = input RMS current ripple.

The output-filter capacitor affects the output-voltageripple, output load-transient response, and feedback-loop stability. For stable operation, the MAX1536requires a minimum output ripple voltage of VRIPPLE ≥1% × VOUT.

The minimum ESR of the output capacitor is calculated by:

Stable operation requires the correct output-filter capaci-tor. When choosing the output capacitor, ensure that:

Integrator AmplifierAn internal transconductance amplifier fine tunes theoutput DC accuracy. A capacitor, CCOMP, from COMPto VCC compensates the transconductance amplifier.For stability, choose CCOMP = 470pF. A larger capaci-tor value maintains a constant average output voltage,but slows the loop response to changes in output volt-age. A smaller capacitor value speeds up the loopresponse to changes in output voltage but decreasesstability.

CtV

xF x V

sOUT

OFF

OUT≥

µµ

79 11

ESR xL

tOFF>1%

I IV V V

VRIPPLE LOAD

OUT IN OUT

IN=

( )-

I IV x t

x LPEAK OUT

OUT OFF= +2

LV x tI x LIROUT OFF

OUT=

∆fI x R

V x tPWM

OUT PMOS

IN OFF= -

fV V V

t V V VPWM

IN OUT PMOS

OFF IN PMOS NMOS=

+- --( )

R t sk

sTOFF OFF= − µ Ω

µ( . )

.0 07

1101 00

Applications InformationMultioutput Voltage Settings

The MAX1536 is optimized to work in applications thatrequire two dynamic output voltages; however, discretelogic or a DAC connected to REFIN allows three ormore dynamic output voltages.

Figure 6 shows an application circuit providing fourvoltage levels using discrete logic. Switching resistorsin and out of the resistor network changes the voltageat REFIN. An edge-detection circuit is added to triggera 1µs pulse on GATE to start the fault-blanking andforced-PWM operation. GATE requires a minimumpulse width of 500ns. The edge-detection circuit is notrequired if the MAX1536 is always in PWM mode (SKIP= VCC) and fault blanking is not necessary.

Active Bus TerminationActive bus termination power supplies generate a volt-age rail that tracks a set reference. Active bus termina-tion power supplies are unique because they sourceand sink current. DDR memory architecture requiresactive bus termination. In DDR memory architecture,the termination voltage is set at exactly half the memorysupply voltage. Configure the MAX1536 to generate thetermination voltage using a resistor-divider at REFIN.Force the MAX1536 to operate in PWM mode (SKIP =VCC) to source and sink current. Figure 7 shows theMAX1536 configured as a DDR termination regulator.Connect GATE and FBLANK to AGND when unused.

Circuit Layout and GroundingGood layout is necessary to achieve the intended out-put power level, high efficiency, and low noise. Goodlayout includes the use of a ground plane, careful com-ponent placement, and correct routing of traces usingappropriate trace widths. Refer to the MAX1536 EV Kitfor layout reference.

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Figure 6. Multioutput Voltage Settings

MAX1536

GATE

AGND

REFIN

REF

OD

OD

B

A

1.5kΩ

1.5kΩ

1000pF

1000pF

C1 R2

R3

R4

R1

Figure 8. Source/Sink Waveforms

0

10µs/divVIN = 3.3V, VOUT = 1.25V, IOUT = -1A TO +1A TO -1A

ILX2A/div

VLX5V/div

VOUT50mV/div

0

Figure 7. Active Bus Termination

MAX1536

REFIN

AGND

OD

GATE

FBLANK

10kΩ

10kΩ

1000pF

1000pF

VDDQ

VCC

IN

FB

LX

PGND

COUT

CIN

VIN

L

OD

SKIP

VDDQ = DDR MEMORY SUPPLY VOLTAGEVTT = TERMINATION SUPPLY VOLTAGE

VTT = VDDQ

2

The following points are in order of decreasing importance:

1) Minimize switched-current and high-current groundloops. Connect the input capacitor’s ground, the out-put capacitor’s ground, and PGND at a single point.Connect the resulting island to AGND at only one point.

2) Connect the input filter capacitor less than 5mmaway from IN. The connecting copper trace carrieslarge currents and must be at least 1mm wide,preferably 2.5mm.

3) Place the LX node components as close togetherand as near to the device as possible. This reducesnoise, resistive losses, and switching losses.

4) A ground plane is essential for optimal performance.In most applications, the circuit is located on a multi-layer board, and full use of the four or more layers isrecommended. Use the top and bottom layers forinterconnections and the inner layers for an uninter-rupted ground plane. Avoid large AC currentsthrough the ground plane.

Chip InformationTRANSISTOR COUNT: 4305PROCESS: BiCMOS

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18 ______________________________________________________________________________________

D

PIN # 1 I.D.

(NE-1) X e

E/2

E

DETAIL A

D/2

LL1

e

XXXXXMARKING

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

D

PIN # 1 I.D.

(NE-1) X e

E/2

E

DETAIL A

D/2

LL1

e

XXXXXMARKING

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