ABSTRACT

The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design. It has been found that the power consumed during test mode operation is often much higher than during normal mode operation. This is because most of the consumed power results from the switching activity in the nodes of the circuit under test (CUT), which is much higher during test mode than during normal mode operation. BIST is a design technique that allows a circuit to test itself. In this, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit.

The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production. BIST technique uses linear feedback shift register (LFSR) for generating test pattern. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 1 multiplexer. When used to generate test patterns for check-based built-in self-tests, it reduces the number of transitions that occur at the check-chain input during check shift operation by 50% when compared to those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. The BS-LFSR is combined with a check-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (check and capture) in the test cycle or while checking out a response to a signature analyzer. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time.

LIST OF ACRONYMS

BIST Built In Self Test LFSR

Linear Feedback Shift Register

CUT Circuit under Test

VLSI Very Large Scale Integration

McM Multi Chip Modules

TPG Test Pattern Generation

PRPGs Pseudo Random Pattern Generators

PRBS Pseudo Random Bit Sequences

DFG Data Flow Graph

BER Bit Error Rate

ASIC Application Specific Integrated Circuit

CONTENTSAbstract

i

List of Acronyms

ii

List of Figures

vList of Tables

vi

CHAPTER 1: INTRODUCTION1.1. Introduction

11.2. Previous Work

11.3. Proposed Work

2

CHAPTER 2: Built-In-Self-Test & LFSR

2.1. Introduction to BIST

32.1.1. Test Pattern Generation for BIST

42.2. LFSR

62.2.1. LFSR Applications

72.3. Bit-Swapping

72.4. Proposed Algorithm

82.4.1. Cell-Reordering Algorithm

9

CHAPTER 3: Bit-Swapping LFSR3.1. BIT SWAPPING LFSR

113.2. Check-Chain Ordering

143.3. Fault Insertion Methodology

163.4. Determination of chain-order of the check cells

173.5. Identification of check-in and check-out cells

183.6. Advantages and Disadvantages

193.7. Applications

203.8. Circuit For Testing

21CHAPTER 4: VHDL INTRODUCTION4.1. VHDL Introduction

224.2. ASIC Migration

234.3. VHDL Description

234.3.1. Entities and Architectures

244.3.2. Sequential Processing

254.3.3. Subprograms

314.3.4. Packages

324.3.5. Data Objects

334.4. XILINX Introduction

34CHAPTER 5: RESULTS & DISCUSSIONS5.1. Results and Discussion

375.1.1. Normal LFSR

375.1.2. Bit-Swapping LFSR

385.1.3. Cell re-ordering Algorithm

395.1.4. Combination of BS-LFSR and cell re-ordering Algorithm Result

405.1.5. Fault analysis waveforms with and with out fault

415.2. Synthesis Report

445.3. Design summary

58CHAPTER 6: CONCLUSION & FUTURE SCOPE6.1. Conclusion

596.2. Future Enhancement

59REFERENCES

60PUBLICATION

64LIST OF FIGURES

Fig No: Title Page NoFig 2.1 Architecture of BIST

4

Fig 2.2 Swapping arrangement for an LFSR

5Fig 2.3

LFSR Bit pattern

7

Fig 2.4 External L.F.S.R with bit-swapping

8

Fig 3.1

B.S-L.F.S.R can be used to generate exhaustive patterns13

Fig 3.2 Example test sequence and weight graph

17

Fig 3.3

Oriented cycle graph

18

Fig 3.4

Example set of test vectors and their response

19Fig 3.5

Circuit for testing

21Fig.5.1

Output wave form for normal LFSR

37Fig 5.2

Output waveform for bit-swapping LFSR

38Fig 5.3

Waveform for cell-reordering algorithm

39Fig 5.4

Waveform for BS-LFSR and cell re-ordering Algorithm Result

40Fig 5.5 (a) Fault analysis waveform with fault

41Fig 5.5 (b) Fault analysis waveform without fault

41Fig 5.6 Graph between time vs flip counter 43Fig 5.7 Graph between power reduction vs flip counter 43LIST OF TABLESTable No. Title Page NoTable 3.1 Bit-Swapping LFSR

11

Table 5.1 Comparative table 42Table 5.2 Design Summary

58iv