2/9/2007EECS150 Lab Lecture #41 Debugging EECS150 Spring2007 – Lab Lecture #4 Laura Pelton Greg...
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Transcript of 2/9/2007EECS150 Lab Lecture #41 Debugging EECS150 Spring2007 – Lab Lecture #4 Laura Pelton Greg...
2/9/2007 EECS150 Lab Lecture #4 1
Debugging
EECS150 Spring2007 – Lab Lecture #4
Laura PeltonGreg Gibeling
2/9/2007 EECS150 Lab Lecture #4 2
Today (1)
Simulation vs. Hardware Debugging
Algorithm Goals Tips
Administrative Info
2/9/2007 EECS150 Lab Lecture #4 3
Today (2)
Lab #4 Bottom Up Testing (Peak Detector) Designing Test Hardware (Broken
Adder) Exhaustive FSM Testing (Broken FSM)
2/9/2007 EECS150 Lab Lecture #4 4
Simulation vs. Hardware (1) Debugging in Simulation
Slow Running Time Fast Debugging
Waveforms Text messages
Full Visibility Can examine any signal
Easy to Fix A few minutes to compile and resimulate
Modelsim assumes no gate delay
2/9/2007 EECS150 Lab Lecture #4 5
Simulation vs. Hardware (2)
Debugging in Hardware Fast Running Time
Full speed in fact Slow Debugging
Synthesis can take hours Little or No Visibility
Very hard to probe signals
2/9/2007 EECS150 Lab Lecture #4 6
Simulation vs. Hardware (3) Simulation
Functional Testing & Verification Test everything at least minimally Fully Verify what you can
This will save you many sleepless nights
Hardware Debugging
Treat this as a last resort It is painful
2/9/2007 EECS150 Lab Lecture #4 7
Simulation vs. Hardware (4)
What does this do in Simulation? Out = Out + In
In Hardware?
2/9/2007 EECS150 Lab Lecture #4 8
Debugging (1)
Debugging Algorithm Hypothesis: What’s broken? Control: Give it controlled test inputs Expected Output: What SHOULD it
do? Observe: Did it work right? If it broke: THAT’S GREAT!
If we can’t break anything like this then the project must be working…
2/9/2007 EECS150 Lab Lecture #4 9
Debugging (2)
Don’t debug randomly Just changing things at random often
makes things look fixed It won’t really help Debug systematically Your first design may be the best “1000 CS150 students at a 1000
typewriters…” What can you do?
2/9/2007 EECS150 Lab Lecture #4 10
Debugging (3)
High Level Debugging Localize the problem
SDRAM? Video? Test Patterns
Lets you easily isolate the broken component
If you know exactly what’s going in you can check what’s coming out
2/9/2007 EECS150 Lab Lecture #4 11
Debugging (4)
Simulate the broken component(s) Writing test benches takes less time
than sitting around wondering why its broken
Everyone hates writing testbenches (Even me) Get used to it
2/9/2007 EECS150 Lab Lecture #4 12
Debugging (5) Your best debugging tool is logic
If 3 out of 4 components work, what’s broken?
Question all your assumptions! Just because you think its true doesn’t
mean it is 90% of debugging time is wasted
debugging the wrong problem otherwise
Given solutions and modules may not work the way you expect!
2/9/2007 EECS150 Lab Lecture #4 13
Debugging (6)
Before you change anything Understand exactly what the problem is Find an efficient solution Evaluate alternative solutions
After the change Fixes may make things worse
sometimes May uncover a second bug May be an incorrect fix
Repeat the debugging process
2/9/2007 EECS150 Lab Lecture #4 14
Debugging (7)
Ask around Someone else may have had the same
bug They’ll probably at least know about
where the problem is Different bugs may produce the same
results TAs
The TAs know common problems We’re here to help, not solve it for you
2/9/2007 EECS150 Lab Lecture #4 15
Administrative Info Midterm I
Thursday 2/15, 2-3:30pm, Room 125 Cory Reviews sessions are:
Tuesday 2/13, 8-10pm, 125 Cory Wednesday 2/14, 8-10pm, 125 Cory
Partners You MUST have one for this week
Try someone other than your best friend Restrictions
You can change partners until the project starts You must be checked off in the same lab
Project in 2 weeks!!!
2/9/2007 EECS150 Lab Lecture #4 16
Lab #4 - Debugging
Part 1: Bottom Up Testing Part 2: Hardware Testing Part 3: FSM Testing
2/9/2007 EECS150 Lab Lecture #4 17
Part1: Bottom Up Testing (1)
What if EqualOut = 1’b0 and GreaterOut = 1’b0?
Lab5Comp1
EqualIn i+1
GreaterIni+1
Ai
Bi
EqualOut i
GreaterOuti
A=B
A<B
Lab4Comp1
2/9/2007 EECS150 Lab Lecture #4 18
Part1: Bottom Up Testing (2) Exhaustive Testing
Ideal Testing Method Circuit is 100% tested!
Requires us to test a LOT! Can we do it here? (24 possible inputs)
Method Make a truth table Have the testbench generate all inputs Make sure outputs match truth table
2/9/2007 EECS150 Lab Lecture #4 19
Part1: Bottom Up Testing (3)
EqualOut[3]
GreaterOut[3]
EqualOut[2]
GreaterOut[2]
EqualOut[1]
GreaterOut[1]
A[0] B[0]
GreaterEqual
Lab5Comp4
Lab5Comp1Lab5Comp1Lab5Comp1Lab5Comp1
A[1] B[1]A[2] B[2]A[3] B[3]
Lab4Comp1 Lab4Comp1 Lab4Comp1 Lab4Comp1
Lab4Comp4
2/9/2007 EECS150 Lab Lecture #4 20
Part1: Bottom Up Testing (4)
Exhaustive Testing? 28 = 256 Possible Inputs
Method Use a for loop to generate all inputs
Loops allowed only in testbenches They will not synthesize
Compare against a “>=“ Print a message if they differ
2/9/2007 EECS150 Lab Lecture #4 21
Part1: Bottom Up Testing (5)
Register
Lab5PeakDetector
In
Clock
Out
Reset
≥4
4
4
4
Lab4PeakDetector
2/9/2007 EECS150 Lab Lecture #4 22
Part1: Bottom Up Testing (6)
Exhaustive Testing? 24 = 16 Possible Inputs 24 = 16 Possible States 16*16 = 256 combinations We could do it in this case
Can’t exhaustively test FSMs Too many state/input combinations Must rely on directed testing
2/9/2007 EECS150 Lab Lecture #4 23
initial begin
end
Part1: Bottom Up Testing (7)
integer i;
reg [3:0] TestValues[1:16];
$readmemh("TestValues.txt", TestValues);
for(i = 1; i <= 16; i = i + 1) begin#(`Cycle);In = TestValues[i]; $display("In = %d, Peak = %d", In, Peak);
end
2/9/2007 EECS150 Lab Lecture #4 24
Part1: Bottom Up Testing (8) Read Test Vectors from a File Designing Test Vectors
Make sure to cover most cases We want 95%+ coverage
Designing test vectors is a “black art” “$” Processes
Not synthesizeable More information in IEEE Verilog Reference
2/9/2007 EECS150 Lab Lecture #4 25
Part2: Test Hardware (1)
Lab5 Part2 Adder
Test
Control
ABSum
A
B
Sum
Error
Running
Go
Reset
Lab5Part2Tester
Lab4 Part2
Lab4Part2Tester
FailMode
FailMode
2/9/2007 EECS150 Lab Lecture #4 26
Part2: Test Hardware (2)
Test Procedure Hit Reset (SW1) Hit Go (SW2) Record an error
DD1-8 show {A, B} SW10[1] selects the sum on DD4-8
Hit Go Repeat until the tester stops
2/9/2007 EECS150 Lab Lecture #4 27
Part2: Test Hardware (3)
The Broken Adder 16bit Adder
232 ≈4 Billion Test Vectors Can’t simulate this much 2:40 to test this at 27MHz
Fail Modes 0: No Errors 2: Will claim 1 + 1 = 3 1-3: Can have anywhere from 0 to 4 errors
2/9/2007 EECS150 Lab Lecture #4 28
Part3: FSM Testing (1)
Exhaustive Testing Again! Check every arc Check every output
You don’t need to correct this one… We’re not giving you the source code
Boring (and Easy) You will have FSM bugs Get used to debugging them
2/9/2007 EECS150 Lab Lecture #4 29
Part3: FSM Testing (2)
S0
S1 S4
S2 S5
1 1 0
S3[Output 1'b1]
S6
0 1
1
0
0
0 1
0 1
X