2/3/2006EECS150 Lab Lecture #31 Implementation of FSMs EECS150 Spring 2006 Lab Lecture #3 Guang...
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Transcript of 2/3/2006EECS150 Lab Lecture #31 Implementation of FSMs EECS150 Spring 2006 Lab Lecture #3 Guang...
2/3/2006 EECS150 Lab Lecture #3 1
Implementation of FSMsEECS150 Spring 2006 – Lab Lecture
#3Guang Yang
Greg Gibeling
2/3/2006 EECS150 Lab Lecture #3 2
Today Designing Digital System Efficient Hardware Design HDL Simulation Blocking vs. Non-Blocking Administrative Info Lab #3: The Combo Lock FSMs in Verilog
2/3/2006 EECS150 Lab Lecture #3 3
Designing Digital System (1) High Level Design
Top-Down Design Partitioning & Interfaces
Implementing the Partitioned Digital Logic Start with the formal description Identify Inputs Determine State Generate Outputs
2/3/2006 EECS150 Lab Lecture #3 4
Designing Digital System (2) Formal descriptions
Mathematical Logic Data Flow Model Petri Net Finite State Machine …
2/3/2006 EECS150 Lab Lecture #3 5
Designing Digital System (3)
Init
OK1 BAD1
OK2[Open]
Prog1[Prog1]
Prog2[Prog2]
BAD2[Error]
Code1 &Enter
~Code1 &Enter
Code2 & Enter
Enter
Enter
Enter
~Code2 &Enter
Enter
<S, S0, I, O, T>S: StatesS0: Initial StateI: InputsO: OutputsT: Transition Function
Example: Finite State Machine
2/3/2006 EECS150 Lab Lecture #3 6
Designing Digital System (4) Identify Inputs
What are they? Possible Values and Don’t Cares Timing
Process Them Raw inputs are often not what you need Might need delay/timing change Might look for a specific value/range
2/3/2006 EECS150 Lab Lecture #3 7
Designing Digital System (5) Determine States
What does the module need to remember?
Has it seen a particular input? How many cycles have passed?
Design Memory for State Standard D Register Counter Shift Register
2/3/2006 EECS150 Lab Lecture #3 8
Designing Digital System (6) Generate Outputs
What are they? Possible Values Timing
Create the outputs They’re always there Compute them from state (and inputs)
Learn to think in Boolean equations assign is helpful
2/3/2006 EECS150 Lab Lecture #3 9
Designing Digital System (7) Mealy Machines
Output based on input and current state
Can have major timing problems
Moore Machines Output based on
current state Easier to work with Slightly harder to
build
Mealy Machine
Moore Machine
2/3/2006 EECS150 Lab Lecture #3 10
Efficient Hardware Design (1)
C
a
B
1
A
01
Z
aA01
aux
Z
B Calways @ (a or A or B or C) begin
if (a) aux =B;else aux = C;Z = A + aux;
end
always @ (a or A or B or C) beginif (a) Z = A + B;else Z = A + C;
end
2/3/2006 EECS150 Lab Lecture #3 11
Efficient Hardware Design (2)
B
Z
A
<<
A
Z
n+1 bit adder
assign B = 3;assign Z = A * B;
assign Z = A + (2 * A);
assign Z = A + (A << 1);
assign Z = A + {A, 1’b0};
2/3/2006 EECS150 Lab Lecture #3 12
Efficient Hardware Design (3)
aux
A[n-1:1]
Z
n bit adder
A
A[0]
assign aux = A + {1’b0, A[n-1:1]};assign Z = {aux, A[0]};
2/3/2006 EECS150 Lab Lecture #3 13
HDL Simulation (1) Software Based Simulation
Simple and accurate Allows for simulation at any precision Easy to see any signal - perfect Visibility
Drawbacks Slow Simulator Dependant Deadlocks are Possible!
Simulation != Synthesis
2/3/2006 EECS150 Lab Lecture #3 14
HDL Simulation (2) Event Driven Simulation
Virtual time axis Maintain a queue of events Pull next event off the queue Determine its consequences Add more events to the queue
Implications Verilog is not executed!
Things don’t necessarily happen in order Verilog is SIMULATED
2/3/2006 EECS150 Lab Lecture #3 15
Blocking vs. Non-Blocking (1)
always @ (a) beginb = a;c = b;
end
always @ (posedge Clock) begin
b <= a;c <= b;
end
C = B = A
B = AC = Old B
Verilog Fragment Result Hardware
CBA
B
D Q
C
D QA
Clock
2/3/2006 EECS150 Lab Lecture #3 16
Blocking vs. Non-Blocking (2) Use Non-Blocking for FlipFlop Inference
posedge/negedge require Non-Blocking Else simulation and synthesis wont match
Use #1 to show causality
always @ (posedge Clock) beginb <= #1 a;c <= #1 b;
end
2/3/2006 EECS150 Lab Lecture #3 17
Administrative Info You could get checked off during
your lab or during any lab TA’s office hours, though the TA would give higher priority to his own students
Or in the first 10 minutes in your next lab session
Try NOT to get checked off in other labs. As the lab gets busier, you may not be checked off at all
2/3/2006 EECS150 Lab Lecture #3 18
Administrative Info (2) Cardkey forms distributed on 2/2
lecture See the office in Cory 253 or Soda 390
To download files from course website, cs150-temp no longer works
If you cs150-xx does not work either, please email David
2/3/2006 EECS150 Lab Lecture #3 19
Administrative Info (3) Partners
You MUST have one for Lab4 and later…
Try to keep the same one for the project You must have one in your lab section
If you do not have a partner: See a TA right after this lab lecture Post to the newsgroup
2/3/2006 EECS150 Lab Lecture #3 20
Lab #3: The Combo Lock (1)
Used to control entry to a locked room2bit, 2 digit combo (By Default 11, 01)Set code to 11, Press EnterSet code to 01, Press EnterLock Opens (Open = 1)
Lab3Top(Lab3Lock)
0101
Lab3CompareOpen
Error
Prog1
Prog2
ResetCombo
Reset
Enter
Code[0]Code[1]
DIPSwitches
ButtonsOutputs
Your Verilog
2/3/2006 EECS150 Lab Lecture #3 21
Lab #3: The Combo Lock (2)Signal Width Dir DescriptionCode 2 I Code from the dipswitchesEnter 1 I Enter button (examine the code)ResetCombo 1 I Reset to the default combinationClock 1 I System ClockReset 1 I System Reset, doesn’t affect the
comboOpen 1 O Indicates the lock is openError 1 O Indicates a bad combinationProg1 1 O Reprogramming the first digitProg2 1 O Reprogramming the second digitLED 8 O Use these for debugging
2/3/2006 EECS150 Lab Lecture #3 22
Lab #3: The Combo Lock (3) Example 1:
1: Press ResetCombo, Combo: 2’b11, 2’b01
2: Set 2’b11, Press Enter 3: Set 2’b01, Press Enter, LEDs: “OPEN” 4: Press Enter, LEDs: “Prog1” 5: Set 2’b00, Press Enter, LEDs: “Prog2” 6: Set 2’b10, Press Enter, LEDs: “OPEN” 7: Combo: 2’b00, 2’b10
2/3/2006 EECS150 Lab Lecture #3 23
Lab #3: The Combo Lock (4) Example 2:
1: Press ResetCombo, Combo: 2’b11, 2’b01
2: Set 2’b01, Press Enter 3: Set 2’b01, Press Enter, LEDs:
“Error” Why doesn’t “Error” show until
step 3?
2/3/2006 EECS150 Lab Lecture #3 24
Lab #3: The Combo Lock (5)
Init
OK1 BAD1
OK2[Open]
Prog1[Prog1]
Prog2[Prog2]
BAD2[Error]
Code1 &Enter
~Code1 &Enter
Code2 & Enter
Enter
Enter
Enter
~Code2 &Enter
Enter
2/3/2006 EECS150 Lab Lecture #3 25
Lab #3: The Combo Lock (6)
Code1Reg
==
Code2Reg
== Lab3
Com
pare
Decode2Decode1
CodeEnter
Pro
g1/P
rog2
Init
OK1 BAD1
OK2[Open]
Prog1[Prog1]
Prog2[Prog2]
BAD2[Error]
Code1 &Enter
~Code1 &Enter
Code2 & Enter
Enter
Enter
Enter
~Code2 &Enter
Enter
Open
Error
Prog1
Prog2
Outputs
Code
Enter
Enter
Prog1
Prog2
Decode1 Decode2
0101Code[0]Code[1]
DIPSwitches
Enter
Lab3
Lock
Lab3
Top
ResetCombo
Reset
ResetCombo
2b
2b 2b
2b2b
2b 2b
2/3/2006 EECS150 Lab Lecture #3 26
Lab #3: The Combo Lock (7) Debugging with LEDs
A powerful way to debug Easy to understand Lower overhead than other debugging tools A great way to see NextState/CurrentState
Drawbacks Slow, can’t see fast events No timing information, no waveform Limited number
Dipswitches!
2/3/2006 EECS150 Lab Lecture #3 27
FSMs in Verilog (1) Mealy Machines
Output based on input and current state
Can have major timing problems
Moore Machines Output based on
current state Easier to work with Slightly harder to
build
Mealy Machine
Moore Machine
2/3/2006 EECS150 Lab Lecture #3 28
FSMs in Verilog (2) Two or Three always blocks
1st: CurrentState Register Clocked Handles Reset
2nd: Generates NextState (+ Outputs in Mealy)
Uses CurrentState and Inputs Combinational
3rd: Generates Outputs (Optional) Uses CurrentState only (for Moore Machines) Might be replaced with a few assigns
2/3/2006 EECS150 Lab Lecture #3 29
FSMs in Verilog (3)
always @ (posedge Clock) beginif (Reset) CurrentState <= STATE_Idle;else CurrentState <=
NextState;end
module MyFSM(In, Out, Clock, Reset);input In, Clock, Reset;output Out;
parameter STATE_Idle = 1’b0,STATE_Run = 1’b1;STATE_X = 1’bx;
reg CurrentState, NextState, Out;
…
2/3/2006 EECS150 Lab Lecture #3 30
FSMs in Verilog (4)
// The case block goes here// Its on the next slide…
endendmodule
…always @ (CurrentState or In) begin
NextState = CurrentState;Out = 1’b0;
2/3/2006 EECS150 Lab Lecture #3 31
FSMs in Verilog (5)case (CurrentState)
STATE_Idle: beginif (In) NextState = STATE_Run;Out = 1’b0;
endSTATE_Run: begin
if (In) NextState = STATE_Idle;Out = 1’b1;
enddefault: begin
NextState = STATE_X;Out = 1’bX;
endendcase