28nm FDSOI Digital Design Flow Tutorial · Digital Design Flow : Logic Synthesis Design Compiler...
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CMP annual users’ meeting - 07-Feb.-19 - PARIS From layout to chips 28nm FDSOI D igital D esign F low T utorial
Transcript of 28nm FDSOI Digital Design Flow Tutorial · Digital Design Flow : Logic Synthesis Design Compiler...
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
28nm FDSOI Digital Design Flow
Tutorial
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
Contents :
a walkthrough user guide,
the RTL code of a basic synchronous and sequential
circuit,
the complete environment, including scripts and
test-benches
Based on CMOS28FDSOI technology from
STMicroelectronics
Supports 7 different tools from common CAD vendors:
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A plug and play tutorial
Digital design flow
clk
reset
load
in[15:0]
eq
out[15:0]
TOP_FIR
RTL netlist
GDS layout
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
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Digital Design Flow : Logic Synthesis
Design CompilerVersion N-2017.09
Genusv. 17.12-000.isr2
Clock frequency : 250MHz
About 100K gates synthesized
Representing 0.15mm²
Verilog RTL
Gate-level Verilog netlist
Logic Synthesis OR
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
Verilog RTL
Gate-level Verilog netlist
Logic Synthesis
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Digital Design Flow : Place & Route
Place & Route
GDSII layout
Innovusv. 17.11-000.isr1
Core area : 0.25mm²
Total area : 0.70mm²
Floorplan Core cells placed
Signalsrouted
Verilog netlist
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
Simulations
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Digital Design Flow : check points
Coefficients loading Outputs calculationReset
Incisivv. 15_20_035
LVS / DRC final verifications
RTL simulation
Gate-level simulation
Back-annotated simulation
Calibrev. 2017.3_38.30
Logic Synthesis
Place & Route
Verilog RTL
Gate-level Verilog netlist
Verilog netlist
GDSII layout
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
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Take full advantages of 28nm FDSOI node
Integrate body biasing methodology :
VDDSGNDS
Speed optimization
Leakage optimization
OR
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
Users experience : IMT Atlantique, France
Courtesy of IMT Atlantique, France
1,6M standard cells fabricated area : 2,85mm²
1 designer 1 year of development
For further details about this project :http://www-labsticc.univ-ubs.fr/~boutillon/un_arch/un_arch.html
Testchip “tracker_gps”
several versions of robust GPS receiver
Redundant mechanisms
reliable, even with low voltage supply
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Rémi PALLAS, Cyril LAHUECFabrice SEGUIN, Emmanuel BOUTILLONMourad HAFIDHI, Arnaud DION
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
Users experience : UCLouvain, Belgium
More than 1K gates fabricated area : 1,25mm²
2 design parts / 2 designers 6-8 months of development
Testchip “AES_SBOX” :
6 substitution boxes for standard
cryptographic algorithms (AES)
1 block for low frequency noise analysis
Auxiliary circuits for logic control
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Kashif NAWAZ, Léopold VAN BRANDT
Courtesy of UCLouvain, Belgium
CMP annual users’ meeting - 07-Feb.-19 - PARIS
From layout to chips
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Tutorial versioning
More than 100 institutions receive RTL2GDS tutorial updates
Version 3.1(Nov. 2017)
Version 4.1(coming soon)
Version 1.4(July 2015)
Version 2.3(Aug. 2016)
• PDK 2.5.d
• Synthesis : Cadence RC and Synopsys DC
• Place&Route: Cadence EDI
• RTL, gate level, back-annotated simulations
• PDK 2.5.f
• Body biasing functionalities
• Cadence Genus and Innovus
• New foundation techno kits from ST
• PDK 2.9
• Migration to 8ML stack
• P&R script updated for Cadence Innovus16.12
• Review of Clock Tree Synthesis strategy
• PDK 1.0.a
• Scripts updates from designers' feedbacks
• Description of LVS and DRC steps
