248 Lab 6 Report
description
Transcript of 248 Lab 6 Report
Ross Lightfoot ECEN 248504
Lab 6 Mehnaz 3715
1.Objectives To use what we’ve learned so far and design and test
a 4bit Arithmetic Logic Unit(ALU) which will add, subtract or perform bitwise and operations. This entails learning about add/sub modules as well as multiplexers. 2.Design
1)
S A B Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1 Y = S’A + SB 2) Schematics for prelab
3)
C_0 C_1 Op
0 0 AND
0 1 AND
1 0 ADD
1 1 SUB 4)
Control(0, 1) A B R Overflow
0x 0000 1010 0000 0
0x 1111 1011 1011 0
0x 1010 0101 0000 0
0x 0110 1101 0100 0
0x 1100 1110 1100 0
0x 0011 0111 0011 0
0x 1110 1111 1110 0
0x 0101 0011 0001 0
10 1110 0110 0100 0
10 1111 0000 1111 0
10 1100 1001 0101 1
10 1011 1100 0111 1
11 1010 0011 1001 0
11 0111 0101 1010 0
11 0110 1010 1100 0
11 0011 1111 0011 0
5) 3.Results
My modules all performed as expected. Different c values gave different different opperations on the input operands. 4. conclusion
In this lab I designed and implemented a 4bit ALU. To do this we learned about and then designed am addition/subtract module along with a 2:1 multiplexer. Then we used our knowlege and already built circuits to form a 4bit ALU from the two components we built earlier.
5.Questions
Max gate delay: 12 see Design 4&5
“What did you like most about the assignment and why? What did you like
least about it and why?”
I liked how each task was a different component until the end when we combined the things we had already completed to get the final product. The lab manual was clear and I have no sugestions.