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2196 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 6, JUNE 2005

Layout-Level Synthesis of RF Inductors and Filtersin LCP Substrates for Wi-Fi Applications

Souvik Mukherjee, Student Member, IEEE, Bhyrav Mutnury, Student Member, IEEE, Sidharth Dalmia, Member, IEEE,and Madhavan Swaminathan, Senior Member, IEEE

Abstract—A fast and accurate layout-level synthesis and op-timization technique for embedded passive RF components andcircuits such as inductors and bandpass filters have been presented.The filters are composed of embedded inductors and capacitors ina multilayer liquid crystalline polymer substrate. The proposedapproach is based on a combination of segmented lumped-circuitmodeling, nonlinear mapping using polynomial functions, artifi-cial neural network-based methods, and circuit-level optimization.Synthesis and optimization results of inductors for spiral/loopdesigns based on microstrip and stripline configuration are within5% of data obtained from electromagnetic (EM) simulations. ForRF circuits, the methodology has been verified through synthesisof 2.4- and 5.5-GHz bandpass filters with and without transmis-sion zeros. Scalability has been shown over a range of 2–3 and4–6 GHz, respectively, with bandwidth variation of 0.5%–3% ofcenter frequency. The synthesized models are within 3%–5% ofEM simulation data.

Index Terms—Artificial neural networks (ANNs), filtersynthesis, inductor optimization, liquid crystalline polymer(LCP), synthesis.

I. INTRODUCTION

WITH THE evolutionary development in wireless commu-nications technology, the need for low-cost, small-size,

and high-performance RF front-end modules is continuously in-creasing. For integration, there is a clear need for design cycletime reduction of passive and active RF modules. This is impor-tant because layout level electromagnetic (EM) optimization ofRF circuits has been the major bottleneck for reduced designtime. Circuit simulators that use coarse circuit models are timeefficient, but do not have sufficient accuracy. The focus of thispaper is the development of methods that enable the synthesisof layouts for new technologies, which significantly reduces thedesign cycle time.

In RF designs, the physical effects of layout such as EM cou-pling and parasitics affect circuit performance. Furthermore,with the emergence of multiple frequency standards, the elec-trical specifications of components have different constraints.For example, a voltage-controlled oscillator (VCO) operatingat 2.45 GHz may require an inductor with a self-resonancefrequency (SRF) of at least 5.5–6 GHz with a high-quality

Manuscript received October 1, 2004; revised December 10, 2004.S. Mukherjee and B. Mutnury are with the Department of Electrical and

Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332USA (e-mail: [email protected]; [email protected]).

S. Dalmia is with Jacket Micro Devices Inc., Atlanta, GA, 30308 USA.M. Swaminathan is with the Department of Electrical and Computer

Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA andalso with Jacket Micro Devices Inc., Atlanta, GA, 30308 USA.

Digital Object Identifier 10.1109/TMTT.2005.848782

factor ( ). However, a 5.8-GHz VCO may require an inductorwith a high SRF ( 8–10 GHz) and a reasonable . Designrequirements of this kind can lead to very long EM simulationtime. Since a liquid crystalline polymer (LCP) substrate pro-vides design flexibility of RF circuits across a large frequencyrange (0.5–20 GHz) by embedding the passives in the substrate[1]–[5], a time-efficient design-constraint-based synthesis andoptimization technique can be very useful. High-performanceminiaturized filters, low-noise amplifiers (LNAs), VCOs,duplexers, and baluns functional from 500 MHz to 6 GHzusing embedded inductors and capacitors on multilayer organiclaminate substrate with LCP have been reported in [1]–[6].The inductors demonstrated have ’s varying from 30 to 200for an inductance range of 1–25 nH [6]. The capacitors with acapacitance density of 1 pF/mm and ’s greater than 300 havealso been demonstrated [6]. In this paper, a synthesis methodhas been described and applied to embedded passives in LCPsubstrates. The synthesized models and layouts have beencompared with EM modeling results for accuracy and speed.

Optimization of silicon-based RF inductors based on geo-metric programming has been described in [7]. The methodis limited by the use of analytical expressions for inductorparameters. This is because it is difficult to extract analyticalexpressions for inductor parameters on multilayer substrates.Polynomial mapping [7], [8] provides good interpolation forsingle or multiple parameter variations for weakly nonlineardata. However, this method does not provide convergence toa unique solution, which is optimum. Efficient EM optimiza-tion techniques using space mapping have been described in[9]–[11]. This method is ideally suited for optimizing struc-tures once it has been generated. Artificial neural network(ANN)-based modeling techniques have also been applied foroptimization of linear and nonlinear circuits [12]–[15]. How-ever, this technique is limited by the complexity of the modelsfor complete circuits that have multiple active and passivecomponents. Recent research has reported the application ofANNs and aggressive space mapping (ASM) based on coarsemodels for design optimization of compact RF passive cir-cuits on multilayer substrates like low-temperature co-firedceramic (LTCC) technology [16], [17]. However, the focus ofthese studies is on time-efficient layout optimization and notsynthesis.

This paper presents a method for the layout-level syn-thesis of RF passive circuits. The synthesis method has beendemonstrated on a multilayered organic substrate with an LCPdielectric material ( , ), which is anew technology for embedding RF passive devices [1]–[4].

0018-9480/$20.00 © 2005 IEEE

MUKHERJEE et al..: LAYOUT-LEVEL SYNTHESIS OF RF INDUCTORS AND FILTERS IN LCP SUBSTRATES FOR Wi-Fi APPLICATIONS 2197

The method presented in this paper enables the synthesis ofinductors and filters based on the constraints imposed by designspecifications. The technique is based on nonlinear mapping ofinductor and filter geometries and its electrical specificationsusing ANNs and polynomial functions with a limited EMdataset. The synthesis approach has the following advantages.

1) It enables global tradeoff analysis between competingobjectives such as area, , and SRF for inductors andcapacitors.

2) It uses a small dataset for neural model training by usinginterpolation techniques.

3) It enables inductor and circuit synthesis across varioustopologies.

4) It allows for the mapping between electrical response andphysical parameters.

5) It enables scalability of the synthesized layout over arange of 20% of center frequency (CF).

6) It allows bandwidth controllability of 0.5%–5% of CF.7) It enables reduction in the number of iterations for EM

simulations performed on the layout to meet designspecifications.

This paper is an extension of the work on synthesis pub-lished by the same authors in [18]. This paper is organizedas follows; Section II discusses the importance of synthesisin RF circuits. Section III discusses LCP technology that hasbeen used to demonstrate synthesis. Synthesis of inductorshave been discussed in Section IV. This is followed by filtersynthesis in Section V. The paper finally concludes with asummary of the contributions of this work in Section VI.

II. SYNTHESIS OF RF CIRCUITS

Synthesis is the process of extracting network/layout-levelparameters for a component/circuit from electrical specifica-tions. It is common in digital designs and is being increasinglyused in low-frequency analog circuits. The main reason for thisis the scalability of design cells, which allows an automated hi-erarchical design flow. RF designs, however, lack this scalabilitydue to the effects of layout level parasitics on circuit perfor-mance. Fig. 1 shows the steps involved in developing a synthesismethod for RF circuits. A conventional design flow tries to op-timize circuit performance at the layout level at the premium oftime-consuming EM iterations for entire layouts. In contrast, asynthesis approach extracts physical dimensions of the layoutfrom the electrical specifications by using some intermediatecircuit-level modeling and optimization. As shown in Fig. 1,the synthesis method develops a lumped-circuit model with par-asitics from a layout. In order to scale the model to a differentfrequency specification without multiple EM iterations, the syn-thesis method performs optimization at the circuit level. Afteroptimization, the physical dimensions of the layout are extractedusing polynomial functions that map the circuit geometries totheir component values.

III. EMBEDDED PASSIVES IN LCP SUBSTRATE

LCP is a low-loss material with a relativepermittivity of 2.95. These material properties are invariant

Fig. 1. Flowchart for conventional design and synthesis; the iteration shownon the left-hand side is performed in forward mapping, while that shown on theright-hand side is performed in synthesis.

Fig. 2. Fabricated LCP board (size � 9 in � 12 in).

up to 20 GHz with negligible moisture absorption (0.04%). Asa result, the embedded passives provide high and stabilityof component values across a large frequency range [6]. Theprocess is low cost due to the use of large area manufacturing,as shown in Fig. 2. Furthermore, the process is low temperature(200 C) and large area in in boards can be batch fabri-cated, making it compatible with a printed wiring board (PWB)infrastructure. The photograph of a fabricated LCP board (sizeof in in) containing 10 000 bandpass filters is shown inFig. 2.

The bandpass filter is an important block in the design of anRF front-end. With the convergence of multiple frequency stan-dards, the design of filters requires controllability of passbandripple, bandwidth, stopband attenuation, and harmonic rejec-tion. High-performance miniaturized filters have been designedon LCP across different topologies to meet different frequencyspecifications, which include inductively coupled resonator fil-ters, coupled line filters, and a capacitively coupled filter [5], [6].Designs are also based on hybrid topologies with a combination


Fig. 3. Fabricated bandpass filters in LCP substrate.

Fig. 4. Cross section of the substrate and metal stackup used in the designs.

of coplanar waveguide (CPW) and stripline configurations toensure compact designs in a multilayer substrate. The filters areelectromagnetically shielded with the use of top–bottom groundplanes for reducing signal coupling from adjacent blocks. Fig. 3is a photograph of fabricated filters with a size of mm mm

mm for Wi-Fi applications. The cross section used for thefilters is shown in Fig. 4. It consists of a four-metal-layer stackupwith top and bottom ground planes. The core dielectric material

on either side of the LCP layer has low loss and hasa thickness of 36 mil. The laminated LCP and the metal layersare 1- and 0.5-mil thick, respectively.

The passives are designed on the middle two metal layers.The entire cross-sectional thickness of 1.8 mm (can be aslow as 0.9 mm) was fixed in the designs that have beensynthesized in this paper. In addition to the synthesis of filters,details on inductor synthesis have also been described. Thisis because, for a fixed cross section, the capacitance is afunction of the width and the length and its value islimited by the loss tangent of the dielectric material[6]. However, inductors have multiple geometrical parameterssuch as side-length, linewidth, line spacing, and number ofturns. Furthermore, inductor values are comparatively lowerthan capacitors, which make the geometry optimization duringinductor synthesis an indispensable part of RF circuit design.

IV. LAYOUT LEVEL SYNTHESIS OF INDUCTORS

In the absence of extensive design libraries of embeddedpassives in LCP substrates, synthesis techniques for induc-tors based on design constraints is important. Methods for

Fig. 5. Multilayer perceptron-based neural-network structure; one hiddenlayer has been used in this paper.

optimization of inductor geometries in a multivariable designenvironment have been addressed in [7] and [8]. In contrast,this section provides a layout-level synthesis technique forinductors used in RF front-end modules.

A. Nonlinear Mapping Using ANNs

In the design of inductors, a nonlinear relationship existsbetween electrical parameters like inductance , , and SRFand geometrical design variables such as side length, linewidth,line spacing, and number of turns. ANNs have emerged asa powerful alternative to numerical and analytical modelingtechniques for capturing nonlinear circuit behavior. ANNs arepreferred due to their asymptotic properties and because theygive very smooth results for approximating discrete measuredand simulated data. Fig. 5 shows a multilayer perceptron-basedneural-network structure that has been used in this paper.During forward mapping, from the inductor geometries to theelectrical parameters, the input neurons receivethe inductor geometries and the output neuronsproduces , SRF, and as the output, and being thenumber of inputs and outputs in a general ANN structure. Thedatasets get reversed during reverse mapping. A single hiddenlayer of neurons has been used in this paper. The outputs fromall the processing units are summed through weightsto produce given by (1). This output passes through theactivation function given by (2) as follows:

(1)

(2)


Fig. 6. Layout of a spiral inductor (1.5 turns).

Fig. 7. Substrate cross section used for the microstrip inductors.

The activation function shown in (2) is a hyperbolic tangentfunction. After passing through the activation function, theoutput dataset is obtained as shown in (3) as follows:

(3)

In this paper, Levenberg–Marquadt nonlinear optimizationalgorithm has been used to train the neural network, as it isan efficient method for training multilayer feedforward neuralnetworks compared to Newton-quasi and other gradient-basedtraining methods [19]–[21].

B. Neural-Network Training and Adaptive Data Sampling

In this paper, an initial library of 150 spiral and loopinductors [5] based on stripline and microstrip topology,respectively, were simulated using Sonnet, a commerciallyavailable two-and-one-half-dimensional (2.5-D) full-wavemethod-of-moments-based EM solver.1 The layout of an in-ductor in Sonnet is shown in Fig. 6. The cross section used formicrostrip design is shown in Fig. 7, while the inductors withstripline topology have the cross section shown in Fig. 4. Theinductance and quality factor were extracted from Sonnet dataas and ,while the SRF was measured at the impedance transitionfrequency, as shown in Fig. 8. For the training of the neuralnetworks to “coarsely” map the input dataset to the output,80% of the 150 inductors simulated were used. When theremaining 20% of the inductor designs were used to test theneural networks, the mapping accuracy was worse than 10%.This is because the number of data points (120) that was usedfor training the neurons was not sufficient to develop a mapping

1Sonnet Inc., Syracuse, NY [Online]. Available: http://www.sonnetusa.com

Fig. 8. Frequency characteristic of Imag[Z11] of an inductor.

with the desired accuracy. The inductor , area, , and SRFwere represented as nonlinear functions of inductor side length,width, and turns, shown in (4) and (5) as follows:

(4)

side length width turns (5)

where represent , , and SRF; and are weights associatedwith the neural network, represents the number of hiddenneurons, represents the number of outputs, and is theregressor vector [19], [20]. In the design of a spiral inductorlibrary from EM simulations, for example, the number of turnsvaried from 0.75 to 1.75 in steps of 0.25. For each of thesedesigns, the side length varied from 0.5 to 3.75 mm in stepsof 0.25 mm and width ( ) from 0.075 to 0.225 mm in steps of0.075 mm. The orders of magnitude of various input and outputparameter values of inductors are very different. Therefore,a systematic preprocessing of training data called “scaling”is desirable for efficient neural-network training. The EMsimulation data was normalized before being fed to the neuralnetwork. The data was scaled with respect to the maximumand minimum of the data range for each electrical/geometricalparameter using linear scaling, shown in (6) as follows:

(6)

Fig. 9(a)–(c) shows the variation of different electrical pa-rameters for a section of the dataset. There is an apparentdiscontinuity in Fig. 9(a)–(c) when compared to the smoothcontours of Figs. 10 and 11. It should been seen that inFig. 9(a)–(c), there is no sample point in the region of discon-tinuity, rather sample points exist only in the smooth regions.The ANN-modeled plot for the training dataset looks the way itis because the variation of parameters were taken for differentwidths of the inductor geometries. Every monotonic section


Fig. 9. Forward mapping of ANN-modeled data and EM data of electricalparameters in a training subset. (a) Variation of SRF. (b) Variation of Q.(c) Variation of L.

of the curve represents geometry variations with respect to asingle width. The next monotonic section begins with the next

Fig. 10. MATLAB TrainLM ANN model to EM data correlation in forwardmapping after training of ANN. Graph 1 is the EM simulation result for testdata and graph 2 is the TrainLM output for test data .X-axis is the test samplenumber; made continuous by interpolation. (a) and (b) represent two differenttraining results for the same test data.

Fig. 11. L-contour for the inductors (length in mils; 1 mm = 40 mil).

width step in between, which is the discontinuity (where asexpected, no sample points exist), where and representthe normalized and denormalized values of the input data and

and represent the normalized and de-normalized maximum/minimum values of the data range for


Fig. 12. Q-contour for the inductors (length in mils; 1 mm = 40 mil).

a particular parameter. During training, the number of neu-rons in the hidden layers were manually adjusted so that thetraining error (the correlation between the neuromodeled outputand training data) is neither too small (less than 2%), whichhampers the generalization capability of the neuromodels, norlarge (greater than 10%), which reduces mapping accuracy.As stated before, it was found that the generated dataset ofinductors was too small to provide accuracy within 5% ofEM simulation. Generation of EM data, which is required fortraining of neural networks, is computationally expensive. Ini-tially, MATLAB’s inbuilt TrainLM neural-network tool was usedto train the neural models with limited EM data for forwardmapping. The EM data to MATLAB neuromodel correlation forfive test data is shown in Fig. 10(a) and (b). Fig. 10(a) and (b)shows an ANN model to EM data correlation for two differenttraining instants (with the same data). The large correlationerror can be seen readily.

In order to tackle this problem, the contour of electrical pa-rameters as a function of geometry variations was developed.As an example, the contour plots for and as a function ofdominant geometrical parameters are shown in Figs. 11 and 12.It can be seen that the surfaces are roughly monotonic in nature.This means that more data points can be generated from the ex-isting library based on interpolation.

An adaptive sampling algorithm was included in theneural-network structure developed by the authors and wasused in conjunction with the training of the neural models.Based on the desired accuracy of the required , , area, andSRF ( 1%–5%), the training dataset was sampled throughinterpolation to generate more data points (the final size of thelibrary can be 10–15 times the size of the library developedfrom EM simulation). At each stage, the neural network wastrained with this larger library size than the previous stage toimprove mapping accuracy. The neuromodel was then used toforward and reverse map between the electrical parameters andgeometries. If the design-imposed accuracy of the componentvalues was met, the training data interpolation was stopped.

Fig. 13. ANN model to EM data correlation using interpolation for test data(same as that used in Fig. 10). Graph 1 is the TrainLM output for test dataand graph 2 is the EM simulation result for test data. X-axis is the test samplenumber; made continuous by interpolation.

Fig. 14. Flowchart of the data-sampling algorithm.

Otherwise, the training loop was iterated using interpolateddata that have smaller step size. The method works very wellfor monotonic data variations. The only time-consuming partwas the generation of highly nonlinear data points. The neu-romodels were then checked for new test case values of sidelengths, linewidths, and turns for inductance calculations. Thecorrelation with modeled and EM data was within 5%. Fig. 13shows the correlation between ANN-modeled data using theinterpolation technique and EM simulation data for forwardmapping using test data. The sampling technique enabled highmapping accuracy without developing extensive EM simulationdata. The nonlinear mapping approach is generic and can beapplied to different inductor topologies. The flowchart for thesampling algorithm is shown in Fig. 14.

C. Synthesis and Optimization

Synthesis of inductors require reverse mapping from the elec-trical specifications to geometries. The neuromodeled outputprovided multiple solutions of geometries for a given inductance


TABLE ISYNTHESIS FOR A 12.5-nH (@2.4 GHz) SPIRAL INDUCTOR EXHIBITING Q,

AREA, AND SRF TRADEOFFS FOR A LINE SPACING OF 0.1 mm; 1 mm = 40 mil

and different values of and SRF. Table I illustrates this situ-ation. From a design perspective, the synthesized inductor ge-ometry that meets the design specifications of SRF, area, and

and has the maximum is the design that is to be selected.Mathematically, the optimization function can be written as

Area Area maximize (7)

where Area is the maximum area of the inductor allowedby a design and is the minimum SRF required for theinductor in the design. The design space exploration leading tothe synthesis of inductors can be formulated as follows.

Let the geometry dataset associated with the th inductor begiven by (8) as follows:

(8)

where is the number of geometrical parameters and isthe number of inductors. The area of the inductor can beobtained as a function of as , where representsthe geometrical relationship. Let the dataset for , SRF, andand Area ( ) for the th inductor be given by

(9)

The neural network described earlier has been used to developweighted mapping functions to map to through theforward-mapping procedure and to through the reverse-mapping procedure. The algorithm for design space explorationcan now be outlined as follows:

begininitialize index, ;for to{ if{ if

{ };index ;}

} }

The geometries synthesized by reverse nonlinear mappingmay not exactly be feasible for fabrication since the resolution ofthe process is 12.5 m, while the reversed-mapped geometriescan have higher decimal orders. In this case, the design valueswere rounded (as shown in Table I) in accordance with processrules with minimum error. For example, a current LCP-sub-strate-based fabrication process allows a minimum linewidthand line spacing of 75 m. Synthesized designs gave 2%–5%variation as compared to EM simulations. Table I shows andSRF variation with synthesized data for a 12.5-nH spiral mi-crostrip inductor at 2.4 GHz. This table clearly indicates thetradeoffs incurred in maximizing and minimizing area.

V. LAYOUT-LEVEL FILTER SYNTHESIS

Layout-level synthesis of filters in the absence of extensivedesign templates to meet different frequency standards cansignificantly reduce the time required for EM simulations andredesign. Previous work has focused on efficient optimizationtechniques of a pre-designed layout [9]–[11], [16], [17]. Incontrast, this paper focuses on design reuse of filter layouts inLCP and enables scalability of circuit models for synthesizinglayout geometries to meet different frequency specifications.The advantage lies in using a single layout template designedfor a particular frequency specification and extracting layoutlevel parameters over a range of frequencies from the same setof EM simulation data. The technique described consists ofmultiple levels of abstraction, which will be detailed below.

A. Development of Lumped-Circuit Models

The stages of the proposed synthesis technique at a circuitlevel can be best explained with the help of a circuit layout.The layout is a 3 mm 3 mm 1.5 mm two-pole bandpassfilter at 2.45 GHz with a bandwidth of 300 MHz on an LCPsubstrate, as shown in Fig. 15 [22]. The layout has two innermetal layers with top and bottom ground planes (not shown inthis figure), which are 1.83 mm from each other, as shown inFig. 4. In Fig. 15, the resonator capacitors , , and

-resonator section have mutual coupling, which was takeninto account while segmenting the circuit. The layout was thusdecomposed into circuit sections, which are isolated from eachother without significant loss of accuracy [1]–[3]. In Fig. 15,the dotted lines represent the segmented sections. For example,the -resonators were segmented into coupled section anduncoupled sections and . This approach allowed separatescaling and mapping of geometrical sections, which have littleEM interaction between them. Based on the two- and one-port


Fig. 15. Segmentation of filter layout into lumped-circuit models.

Fig. 16. Mapping of reference ground plane of the resonator capacitors; separate polynomial functions for split and continuous ground plane coupling.

modeling of the sections using Sonnet (which has good corre-lation with measurement data) [6], lumped-circuit models in-cluding the effect of parasitics and coupling were developed[6]. Fig. 15 also shows the schematic of the models for cou-pled -resonator, matching capacitors , center capac-itor and coupled . The models showed verygood correlation with EM simulation up to the second harmonicwith a CF of 2.45 GHz. Due to the use of segmented models,fast optimization at the circuit level was possible to meet designspecifications without losing the effects of physical layout oncircuit performance.

The reference ground plane has a significant effect on thecoupling between the capacitors, which affects the bandwidthcharacteristics of the filter. The lower plates of the two res-onator capacitors were grounded through a common groundplane. During lumped-element modeling, it was seen that themutual coupling between the two resonator capacitors is not justa function of their size and spacing, but also depends on the pres-ence or absence of the ground planes, as shown in Fig. 16. InFig. 16, the spacing indicates the separation between the inner

edges of the top metal planes of the capacitors. Furthermore, thebottom plane has an overlay over the top plane to compensate forfringing capacitance. As a result, the bottom planes touch eachother and become continuous at a point when the top planes areseparated by 0.19 mm. Hence, the coupling coefficient betweenthe capacitors in the models will have different values based oncontinuous or split ground planes. This effect has been includedin this study through piecewise mapping.

B. Synthesis Using Model Mapping

The segmented models were made scalable based on non-linear polynomial mapping of the circuit model parameters toEM simulation data. The one- and two-port circuit models forinductors and capacitors, taking into account the effect of cou-pling, were developed based on [6]. In its general form, the map-ping can be mathematically outlined as follows.

Let the segmented component parameters (which include theparasitics) be represented by the vector in (10) as follows:

(10)


where is the total number of model parameters. Here, con-sists of all the parameters in the circuit model, which includesthe ideal components and their parasitics. Let us assume that fora component , there exists a vector

(11)

where is the number of geometrical parameters associatedwith the component. Given a reference layout, its segmentedcomponents could be parameterized to generate a data set ofcomponent values with a varying geometrical parameter. Thisprocess was fast using the EM solver since it solves for sectionsinstead of a complete layout. Let the dataset vector for a seg-ment’s th geometrical parameter be given by

(12)

where is the number of data points for which the solver wasinstructed to parameterize. Based on this data, nonlinear polyno-mial functions can be extracted for each of the geometricalsections to its corresponding component value in the model.This can be written as

(13)

Therefore, from the lumped-circuit model component vector, the geometry mapping functions can be rep-

resented by the vector

(14)

where each vector represents all the polynomialmapped geometries (equal to ) associated with the component

as follows:

(15)

where is the number of geometrical parameters associatedwith . The circuit level optimization parameters in the entiremodel is a subset of the entire model parameter and is givenby (16) as follows:

(16)

All the optimization parameters in the model now have map-ping relations to its geometries given by

(17)

where is the number of variables selected for optimization.The next stage is to have mapping functions, which correlates

the component values to its parasitics. Let the mapping func-tions for this relation be given by , where

(18)

In (18), represents the parasitic associated with the com-ponent and also

(19)

where is the entire model parameter vector, as shown in (10)and represents the union of the two component sets. In con-ventional simulation methods, the component set is the inputfrom which certain variables are selected for optimization. Inthis paper, the vector is used in the optimizationroutine where is the number of parameters selected for opti-mization. At each step of the optimization of , the parasiticsalso get updated through in the simulation. As a result,the final optimized component values take into account the asso-ciated parasitics. Therefore, the physical effects of layout havebeen captured in the circuit models, while the time for simu-lation is reduced by performing the optimization at the circuitlevel. After optimization of the components in the lumped-cir-cuit model, the geometry values could be synthesized throughthe reverse mapping of the same functions. Mathematically, theth geometrical parameter of the th component value could

be extracted as follows:

(20)

where is the optimized th geometrical parameter corre-sponding to the optimized component . From the theory ex-plained here, it is important to note that the reverse mappingwas made under the premise that the mapping function stillremained the same over the frequency range in which the ref-erence layout was scaled. This is true since the method de-scribed involves scaling of a reference layout within 20%of its CF with 0.5%–5% tunability in bandwidth. EM simula-tions over the entire frequency range of scaling have verifiedthat the mapping functions remain unchanged. This has alsobeen confirmed using separate reference layouts for the designof 2.4- and 5.5-GHz bandpass filters. The above methodologyis best explained with the help of the layout of a bandpass filter,as shown in Fig. 15. In Fig. 15, the uncoupled inductor sectionin the lower half of the right lumped inductor model with shuntcapacitor and series resistance were mapped to the in-ductor geometry as

(21)

(22)

(23)

where is the increment in the inductor length of andfor a fixed inductance of 0.8 nH. Similar mappings were

obtained for all the circuit models. The scalable models withparasitics were combined to perform filter circuit optimization


TABLE IICOMPARISONOF COMPONENT VALUESFOR THREE SYNTHESIS TEST CASES

BASED ON 2.45-GHz REFERENCE LAYOUT CORRELATION OF

EM SIMULATION DATA WITH POLYNOMIAL MAPPED MODEL

using Agilent’s Advanced Design System (ADS).2 At each stageof the optimization process, the desired components were tunedand the corresponding polynomial-mapped geometries and par-asitics were updated as well. At the end of optimization, thevariable geometries of the components were extracted from thecomponent values of the models using their reverse-mappingfunctions. The reverse mapping is represented by (20). As anexample, the length and spacing of the inductors,as well as the width of the capacitors, illustrated in theprevious numerical example, was reverse mapped from the com-ponent parameters as follows:

(24)

(25)

(26)

The values of the components obtained from synthesis andthose obtained by simulating the designs in the EM solver areshown in Table II. The flowchart for the optimization and syn-thesis method is shown in Fig. 17.

Table II shows that the component values obtained fromoptimization are within 2%–5% of EM simulation using thesynthesized geometries. The simulated results for the refer-ence layout are shown in Fig. 18. Based on different designspecifications, the reference layout was scaled to a design at2.2 GHz with a bandwidth of 325 MHz and to another filterwith a CF of 2.85 GHz and a bandwidth of 400 MHz. The

-parameters of the data from synthesis and that from theEM solver shows good correlation. Fig. 19 shows the EM tomodel correlation for a synthesized 2.2-GHz bandpass filter.Fig. 20 shows the EM to model correlation for a synthesized2.8-GHz bandpass filter.

2Advanced Design System 2002\doc\ccdist\SCLIN.htm

Fig. 17. Flowchart for optimization and synthesis procedure.

Fig. 18. S-parameters of the reference layout for the 2.45-GHz bandpass filter.

Fig. 19. Correlation between full-wave data (sampled) and data from synthesis(solid) for the 2.2-GHz bandpass filter.

C. Correlation of Synthesized Model to EM Simulation

A detailed analysis of the -parameters of the extensivelumped-circuit models and that obtained from the EM data


Fig. 20. Correlation between full-wave data (sampled) and data from synthesis(solid) for the 2.8-GHz bandpass filter.

by using the synthesized geometries (shown in Figs. 18–20)showed that while had very good correlation, theresults had some discrepancy. This can be explained as follows.The return-loss characteristic ( ) is predominantly a functionof the matching capacitors in the filter. It can be seen in thelayout that the segmented sections of these capacitors alongwith the central capacitors include the vias that were used inthe design. In other words, separate via models were not usedas part of the synthesis. As a result, the mapping functions forthe capacitor geometries and its component values needed to beof higher order than what was used in the design for capturingthe nonlinearities introduced due to the vias. The argument issupported by the fact that no such discrepancies were seen inthe characteristic. This is because the resonator inductorsand capacitors, which predominantly affect the passband char-acteristic, did not have any vias in their structures.

D. Test Cases

The synthesis method discussed was applied to bandpassfilters across frequencies and topologies. Reference layout offilters at different frequency bands and with transmission zeroeswere synthesized. Synthesis results will be discussed below.

1) 5.5-GHz Bandpass Filter: The synthesis methodologywas applied to a capacitively coupled resonator bandpass filterwith a CF of 5.5 GHz and a bandwidth of 750 MHz. The crosssection of the layout is the same as shown in Fig. 4. The filterhas a lateral dimension of 2.3 mm 2.3 mm. The layout of thefilter is shown in Fig. 21. The filter has the same topology asthe 2.45-GHz filter in Fig. 15. Consequently, a similar segmen-tation procedure was applied to the layout. For correcting thediscrepancies due to via effects, which are prominent at higherfrequencies, higher order mapping functions were used for thecenter, as well as the matching capacitors. For example, thematching capacitor in the layout in Fig. 15 with param-eters and were mapped to its length increment ofthe capacitor plates from EM simulation data by fourth-orderpolynomial functions as follows:

(27)

Fig. 21. Layout of the 5.5-GHz bandpass filter.

Fig. 22. Correlation between full-wave data (triangular) and data fromsynthesis (solid) for filters centered at 4.7 and 6.5 GHz based on coarse data ofthe 5.5-GHz filter, which is shown in the middle.

(28)

(29)

The improvement can be clearly seen in the -parametersshown in Fig. 22. From this figure, it is clear that has abetter correlation between the synthesized models and EM sim-ulation due to the use of higher order polynomials. The polesof the filter have also been captured in the synthesized layout.The reference layout has been scaled to a filter at 4.7 GHz witha bandwidth of 550 MHz and another filter at 6.5 GHz witha bandwidth of 750 MHz. The component values are within3%–5% to that obtained from EM simulation. The circuit leveloptimization took 5 min on Dell PC with a 2.8-GHz PentiumIV processor and 1-GB RAM. EM simulation in Sonnet of eachsegmented part with geometrical variation took on an average of10 s per frequency point with a cell size of 3 3 mil. Table IIIshows the comparison of component values for three synthesis


TABLE IIICOMPARISON OF COMPONENT VALUES FOR THREE SYNTHESIS TEST CASES

BETWEEN POLYNOMIAL MAPPED MODEL AND FULL-WAVE EM SIMULATION

Fig. 23. Ideal schematic of the inductively coupled resonator filter.

test cases between polynomial mapped model and full-wave EMsimulation. Results in Table III show that the use of fourth-ordermodels gave higher correlation with EM data compared to thethird-order models in the first design.

2) Filter With Transmission Zeros: The synthesis methodwas applied to a different filter topology. The filter shown inFig. 23 is an inductively coupled resonator bandpass filter. Thefeedback capacitor and the inductively coupled resonatorsprovides multiple signal paths between the input and output,which are out-of-phase, resulting in transmission zeros [23],[24]. The transmission zeros in the design allows controllabilityof the stopband attenuation and rejection at specific frequencies.The layout of the filter has a lateral dimension of 3.9 mm4.1 mm. The cross section for the layout is same as that shownin Fig. 4. The spacing between the inductors, which controlsthe inductive coupling in this design is an important design pa-rameter. Further, during EM modeling, the inductive lines onthe lower plane were also segmented. The top and bottom metallayers of the layout are shown in Fig. 24. The EM response fromsynthesized geometries is shown in Fig. 25.

The synthesized model was within 2%–5% of EM simula-tion and similar EM modeling time as that for 2.45-GHz band-pass filter synthesis. It should be understood, however, that thesegmented lumped-element technique, which was seen to workvery well for two metal layer designs (considering the number

Fig. 24. Layout of the 1.8-GHz filter with transmission zeros. (a) Top metallayer of the layout. (b) Bottom layer of the layout. The components have beenlabeled in correspondence with Fig. 23.

Fig. 25. Synthesized filters centered at 2.9 GHz from a reference layout at1.85 GHz (EM data) based on synthesized geometries.

of layers in which the passives are embedded) will have prob-lems with multilayer designs (number of metal layers 3). Thiswas realized in modeling the inductor coupling for the filter in


Fig. 26. Layout of 2.3- and 4.25-GHz dual-band filter.

Fig. 24. This is due to EM coupling between multiple metallayers, which is not accurately captured by lumped models.

3) Synthesis of Dual-Band Filters: In the design ofdual-band filters, if the frequency bands are further awaythan the scalability of each frequency band, then separatemapping functions need to be used for the two filters. Withreference to (10)–(19), such a synthesis can be mathematicallyformulated, as described here. Let the entire lumped-circuitmodel vector for each of the two filters be defined by and

, where the vectors are similar to (10). For components forthe first filter , let represent the polynomials for mappingthe model parameters to geometries, and represent the map-ping of the ideal component values to their parasitics. Similarrelations hold for (in terms of and ). Therefore, in thecircuit-level optimization of a dual-band design, the vector ofparameters that is optimized is given by (30) as follows:

(30)

where represent the components of the whole filter to beoptimized and and are the number of components in eachfilter to be optimized. The geometries for the design are ex-tracted, as follows in (31a) and (31b), which is similar to (20)for a single band design:

(31a)

(31b)

where and represent the extracted geometries forthe two bandpass filters. The filter layout of the dual-band filteris shown in Fig. 26. The design consists of single-band filterssynthesized from the 2.45- and 5.5-GHz reference layouts. Thecircuit model of the combined design was optimized to meetmatching conditions and reverse mapped to obtain the dual-banddesign. The design has a lateral dimension of 6.8 mm 3.3 mmwith a cross section shown in Fig. 4. The EM simulation resultswith the synthesized geometries are shown in Fig. 27. It consistsof two bandpass responses centered at 2.3 and 4.25 GHz withbandwidths of 250 and 300 MHz, respectively. Synthesized de-signs have a scalability of 20% of CF with a bandwidth

Fig. 27. Dual-band filter response in EM solver using synthesized geometries.

tenability of 0.5%–5%. This was expected since the single banddesigns, from which the dual-band filter is synthesized, had sim-ilar scalability and tenability in terms of CF and bandwidth.

VI. CONCLUSIONS

This paper has presented a fast and accurate layout-levelsynthesis of RF passive components and circuits in multilayeredorganic substrates with LCP dielectric material. It is based onsegmented lumped-circuit modeling, polynomial mapping, andcircuit-level optimization. An optimization technique based onANNs and design space exploration has also been discussedfor inductor synthesis. Synthesized results for components andcircuits show accuracy that is within 5% of EM data. The ANN-based technique was not applied in the synthesis of inductors inthe bandpass filters. This is because the inductors in the bandpassfilters were less than 2.5 nH for which simple polynomialmapping of the segmented inductor sections gave results within3% of EM data. Design cycle time was significantly reducedsince optimization were performed at the circuit level. Filtersynthesis was demonstrated across frequencies and topologies.The mapping technique can be also applied to diagnosticanalysis of circuit layouts in batch processing where geometricalvariations affect circuit performance.


REFERENCES

[1] S. Dalmia, V. Sundaram, G. White, and M. Swaminathan, “Liquid crys-talline polymer based RF/wireless components for multiband applica-tions,” in Proc. IEEE Electronic Components Technology Conf., LasVegas, NV, Jun. 1–4, 2004, pp. 1866–1873.

[2] A. Bavisi, S. Dalmia, G. White, V. Sundaram, and M. Swaminathan, “A3G/WLAN VCO with high Q embedded passives in high performanceorganic substrate,” presented at the IEEE Asia–Pacific Microwave Conf.,Seoul, Korea, Nov. 2003.

[3] V. Govind, S. Dalmia, and M. Swaminathan, “Design of integrated LNAusing embedded passives in organic substrates,” Trans. Adv. Packag.,vol. 27, pp. 79–89, Feb. 2004.

[4] V. Govind, S. Dalmia, V. Sundaram, G. White, and M. Swaminathan,“Design of multiband baluns on liquid crystalline polymer (LCP) basedsubstrates,” in Proc. IEEE Electronic Components Technology Conf.,Las Vegas, NV, Jun. 1–4, 2004, pp. 1812–1818.

[5] S. Dalmia, F. Ayazi, M. Swaminathan, S. H. Min, S. H. Lee, W. Kim,D. Kim, S. Bhattacharya, V. Sundaram, G. White, and R. Tummala,“Design of inductors in organic substrate for 1–3 GHz wireless appli-cation,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2–7, 2002, pp.1405–1408.

[6] S. Dalmia, “Design and implementation of high Q passive devices forwireless applications using SOP based organic technologies,” Ph.D. dis-sertation, School Elect. Comput. Eng., Georgia Inst. Technol., Atlanta,GA, 2002.

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[12] Q. J. Zhang, K. C. Gupta, and V. K. Devabhaktuni, “Artificial neuralnetworks for RF and microwave design-from theory to practice,” IEEETrans. Microw. Theory Tech., vol. 51, no. 4, pp. 1339–1349, Apr. 2003.

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Souvik Mukherjee (S’02) received the B.Tech(Hons.) degree in electronics and electrical com-munication engineering from the Indian Instituteof Technology, Kharagpur, India, in 2002, the M.S.degree in electrical engineering from the GeorgiaInstitute of Technology, Atlanta, in 2004, and is cur-rently working toward the Ph.D. degree in electricalengineering at the Georgia Institute of Technology.

He is currently with the Epsilon Group, GeorgiaInstitute of Technology. His research involves devel-oping modeling, synthesis, and diagnosis techniques

of RF passive and active circuits.

Bhyrav Mutnury (S’00) received the B.Sc. degreefrom the College of Engineering, Jawaharlal NehruTechnological University (JNTU), Hyderabad, India,in 2000, the M.S. degree in electrical engineeringfrom the Georgia Institute of Technology, Atlanta,in 2002, and is currently working toward the Ph.D.degree in electrical engineering at the GeorgiaInstitute of Technology.

In Fall 2000, he joined the Georgia Institute ofTechnology. His current research concerns nonlinearmacromodeling.

Sidharth Dalmia (M’03) received the B.S., M.S.,and Ph.D. degrees from the Georgia Institute ofTechnology, Atlanta, in 1998, 1999, and 2002,respectively.

In 2002, he joined the Epsilon Group, GeorgiaInstitute of Technology, as Research Faculty. Heis also the co-founder of Jacket Micro DevicesInc., Atlanta, GA, which focuses on integratedpassive devices and RF modules for wireless localarea network (WLAN), ultrawide-band (UWB),and cellular applications using organic/laminate

packaging technology. He has authored or coauthored over 30 peer-reviewedpapers in the areas of passive circuits, lumped-element filters, RF packaging,and monolithic-microwave integrated-circuit (MMIC) design. He has fourpatents pending. His current research interests are high-level system integrationbased on multilayer low-cost high-performance organic system-on-packagingconcepts.

Dr. Dalmia is a reviewer for the IEEE TRANSACTIONS ON ADVANCED

PACKAGING and the IEEE TRANSACTIONS ON COMPONENTS, PACKAGING,AND MANUFACTURING TECHNOLOGIES. His thesis was nominated for the2002 Outstanding Thesis of the Year Award by the School of Electrical andComputer Engineering, Georgia Institute of Technology.


Madhavan Swaminathan (A’91–M’95–SM’98) re-ceived the M.S. and Ph.D. degrees in electrical engi-neering from Syracuse University, Syracuse, NY, in1989 and 1991, respectively.

He is currently a Professor with the School of Elec-trical and Computer Engineering, Georgia Instituteof Technology, Atlanta, and the Deputy Director ofthe Packaging Research Center, Georgia Institute ofTechnology. He is the co-founder of Jacket Micro De-vices Inc., Atlanta, GA, a company that specializesin integrated devices and modules for wireless appli-

cations, for which he serves as the Chief Scientist. Prior to joining the GeorgiaInstitute of Technology, he was with the Advanced Packaging Laboratory, IBM,where he was involved with packaging for super computers. While with IBM, hereached the second invention plateau. He has authored or coauthored over 150publications in refereed journals and conferences and has coauthored three bookchapters. He holds nine issued patents with six pending. His research interestsare digital, RF, opto-electronics, and mixed-signal packaging with emphasis ondesign, modeling, characterization, and test.

Dr. Swaminathan has served as the co-chair for the 1998 and 1999 IEEETopical Meeting on Electrical Performance of Electronic Packaging (EPEP).He is the co-founder and has served as the technical and general chair for theInternational Microelectronics and Packaging Society (IMAPS) Next Gener-ation Integrated Circuits (IC) and Package Design Workshop. He serves asthe chair of TC-12, the Technical Committee on Electrical Design, Modeling,and Simulation within the IEEE Components, Packaging, and ManufacturingTechnology (CPMT) Society and was the co-chair for the 2001 IEEE FutureDirections in IC and Package Design Workshop. He is the co-founder ofthe IEEE Future Directions in IC and Package Design Workshop. He alsoserves on the Technical Program Committees of the EPEP, Signal Propagationon Interconnects Workshop, Solid-State Devices and Materials Conference(SSDM), Electronic Components and Technology Conference (ECTC),and Interpack. He has been a guest editor for the IEEE TRANSACTIONS ON

ADVANCED PACKAGING and the IEEE TRANSACTIONS ON MICROWAVE THEORY

AND TECHNIQUES. He was the associate editor of the IEEE TRANSACTIONS ON

COMPONENTS AND PACKAGING TECHNOLOGIES. He was the recipient of the2002 Outstanding Graduate Research Advisor Award presented by the Schoolof Electrical and Computer Engineering, Georgia Institute of Technology andthe 2003 Outstanding Faculty Leadership Award for the mentoring of graduateresearch assistants from the Georgia Institute of Technology. He was also therecipient of the 2003 Presidential Special Recognition Award presented by theIEEE CPMT Society for his leadership of TC-12 and the 2004 IBM FacultyAward. He was the recipient of the Shri. Mukhopadyay Best Paper Awardpresented at the International Conference on Electromagnetic Interferenceand Compatibility (INCEMIC), Chennai, India, 2003. He has also served asthe coauthor and advisor for numerous outstanding student paper awards atEPEP’00, EPEP’02, EPEP’03, EPEP’04, ECTC’98, and the 1997 IMAPSEducation Award.

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