20702032 Universal Logic Gates

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Universal logic gates

1. INTRODUCTION

2. LOGIC GATES

3. UNIVERSAL LOGIC GATES

4. WORKING

5. APPLICATIONS

INTRODUCTION

In this 20th century, world cannot be imagined without the use of

electronic devices and IC’s are the pillars for these devices and these

devices are mainly constructed using different combinations of logic gates

.The concept of logic gates brought a great revolution in the field of

electronic devices.A logic gate performs a logical operation on one or more logic inputs

and produces a single logic output. The 1st logic Gates was developed in

1837 by Charles Babbage and they are of mechanical form. From then a

large variety and different type of logic gates are constructed there are

different types of logic gates like And, Or, Nand, nor, ex-or etc, these logic

gates are also known as Boolean logic gates.

The fundamental logic gates are or & and Gates. But these are not the

basis for making of different gates. So there came the concept of

universal logic gates and the universal logic gated are nand and nor

gates, they are called so because using both these logic gates all the

other logic Gates can be constructed. They are like the pillars for making

all the Boolean logic gates. These are of digital in nature and their inputs

and outputs will be accounted in 1’s and 0’s i.e, operating at high and low

voltages.

It looks very amazing that why AND & OR gates are not extensively used

gates their complements are the most extensively used gates. This is

because such circuits involve transistors where inversion occurs

automatically.



We can see of these gates by implementing other basic logic gates with

the help of these gates only. Otherwise, mathematically also it has been

tried to prove the universality of these functions in Boolean algebra.

LOGIC GATES

Logic gates are used in the constructing digital circuits. Logic gates are

primarily implemented electronically using diodes or transistors, but can

also be constructed using

electromagnetic relays, fluidics, optics, molecules, or even mechanical

elements. The complexity of their construction depends upon the

materials from which they are made and the simplest one is diode logic

and these cannot be used to construct complex functional logics. Now

diode logic has evolved to transistor-transistor logics (TTL) following

resistor –transistor logics and then diode-transistor logics levels. The

transistors used are BJT (bipolar junction transistor) so as to reduce the

space occupied and to increase the level of complexity in logics.TT implies

that one transistor amplify the functions and the other helps in the logic

gating function.

Electronic logic gates are generally preferred than the mechanical ones

because of its qualities like speed, size and they consume less power.

Semiconductor logic gates are also built which act as high gain voltage

amplifier. The inputs and outputs levels, which are represented by voltage or

current, can be tabulated and that is known as a truth table. So for each

logic gate a unique truth table and a symbol can be associated. The

fundamental logic gates are or & and gates and the other logics include

inverter, Nand, or, Ex-or gates

Example:

Symbol of and gate:

Truth table of and gate

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Electronics



UNIVERSAL LOGIC GATES

As said before Nand & nor gates are said to be the universal logic

gates

Symbol Rectangular symbol Function Truth table

NAND

NOR

INPUT OUTPUT

A B A AND B

0 0 0

0 1 0

1 0 0

1 1 1

INPUT OUTPUT

A B A NAND B

0 0 1

0 1 1

1 0 1

1 1 0

INPUT OUTPUT

A B A NOR B

0 0 1

0 1 0

1 0 0

1 1 0

http://en.wikipedia.org/wiki/NAND_gate


http://en.wikipedia.org/wiki/NOR_gate

http://en.wikipedia.org/wiki/File:NOR_IEC.svg

http://en.wikipedia.org/wiki/File:NOR_ANSI.svg

http://en.wikipedia.org/wiki/File:NAND_IEC.svg

http://en.wikipedia.org/wiki/File:NAND_ANSI.svg



http://en.wikipedia.org/wiki/NOR_gate



2 input TTL nand gate

Explanation: we know that the voltage of the collector should be greater

than the base voltage which in turn should be greater than emitter

voltage for proper functioning of the transistor. The input is always given

through the emitter of the transistor because of the low impedance.

When both the inputs are high i.e., 1 then the transistor will be in reversed

bias, thus allowing the charge in the base flows through the transistor

On applying an input as 0 or low then T1 will be forward biased (base-

emitter junction) and current flows out through the collector. The stored

base charge in T2 will be discharged through T1 and taking it into a cut-off

region so current doesn’t flow through the transistor, since there is no



base current inT4 it will be in cut-off region. The current from Vcc goes

into the transistor T3 through the resistor and making it into the

saturation level and because of that the output will be high.

Similarly when both the inputs are high or 1 the T1 will be in reversed bias

(base-emitter junction). So the current flows through resistor R1 into the

base of T2 making T2 into saturation level and the stored charge from the

base of the T3 will flow from it to the emitter ofT2 and make the T4 into

cut-off region making the output to be 0 or low .And T3 will also be in the

cut-off region so no current flows through it. So the output will be low.

So from the figure we can say that unless both the inputs are high the

output cannot be high.

VOLTAGE LEVELS

The definitions for high level and low level will be different for different

ones used for the building of nand gate. Like for TTL nand gate the idealvoltage at which it is operated is 5+%5 volts. The definition for high input

is any voltage between 2v and 5v and the low is between 0v to 0.8v.

The output high value will be possible when the output value voltage is

between 2.7v and 5v. And low means the voltage levels between 0v and

0.5v

Similarly for CMOS the input high means 3.5v to 5v and low corresponds

to 0v to 1.5v and the output high corresponds to 4.95 to 5v and the low

corresponds to 0v to 0.05v. But unlike TTL the CMOS can be operated atdifferent voltage levels like 12v and 15v etc.

Factors affecting voltage levels:

The values are not exactly 5 for high and 0 for low because some

resistance in the transistor present is responsible in that and the noise

margin also affects the output voltage levels. If the noise is greater than

the noise margin the output will be affected. So care should be taken such

that noise should be less than noise margin i.e., to minimize the noise or

to maximise the signal.



The advantage of using CMOS in building the NAND gate is that the noise

margin will be high for CMOS compared to BJT’s.

Since ideal nand gates are not possible so one can try to make it more

closer towards the ideal nature.

REALISATION OF LOGICAL FUNCTION USING NAND

GATES:

Any logic function can be implemented using nand gates only. First the

logic functions are converted to POS (product of sum) form, then it is very

easy to implement it using nand gates .

Consider the following SOP expression

F = W.X.Y + X.Y.Z + Y.Z.W

The above expression can be implemented with three AND gates in firststage and one OR gate in second stage as shown in figure.

If bubbles are introduced at AND gates output and OR gates inputs (thesame for NOR gates), the above circuit becomes as shown in figure.



Now replace OR gate with input bubble with the NAND gate. Now we havecircuit which is fully implemented with just NAND gates.

NOR GATE

It is the second universal logic gate. Same as nand gate any entire logicsystem can be implemented using only NOR gate. It is basicallycomplement of OR logic gate and denoted by different ways. Logic norgate function is sometimes called the ‘pierce function’ and denoted by A B

.the other way to represent it is A+B.A NOR gate gives high output only when all the inputs given to it are lowotherwise the output remains high.

CONSTRUCTION AND WORKING NOR GATE:

NOR gate is constructed following different types of circuitry

(TTL,CMOS,NMOS etc).depending upon circuitry the limitations and other

characteristics may be somewhat different.



Structure of NMOS NOR gate Idealised

corresponding circuit

This consists of two identical NMOS enhancement drivers and one

depletion load. For ideal inverters, the behaviour of this circuit is

analogous to the second circuit. In 2

nd

circuit the switches are open forinputs of V(0) and closed for input V(1).consequently if either one of the

inputs is at V(1),a switch is closed and output will be 0.the output will be

SUPPLIED VOLTAGE only if when both

Inputs A and B are at V(0).



CMOS NOR GATE AND ITS IDEALISED ANALOGOUS

CIRCUIT

If we represent this CMOS NOR GATE with analogous idealised circuit then

it will be like 2nd circuit. If either A or B is at logic 1, the output is ground.

No path is permissible between the output node and the power supply

Vdd .if either or both inputs are at 1, then output gives 0.if both switches

are open output will be Vdd.

REALISATION OF LOGICAL FUNCTION USING NOR GATES

As we know any logical function can be implemented using NOR gates. Inorder to do this at first, the logic function is converted to POS (product of

sum) form.

After converting logical expression to corresponding pos form it is very

convenient to implement it using NOR gate.

Like the POS expression

F = (X+Y) . (Y+Z)

Like other POS expression this can also be implemented very easily stepby step.



The above expression can be implemented with three OR gates in firststage and one AND gate in second stage as shown in figure.

If bubble are introduced at the output of the OR gates and the inputs of AND gate, the above circuit becomes as shown in figure.

Now replace AND gate with input bubble with the NOR gate. Now we havecircuit which is fully implemented with just NOR gates.

Comparison between NAND & NOR gates

Although both gates are universal, they differ in their performance The NOR gate has a higher logical effort than the NAND (5/3 versus 4/3 fora 2-input gate), and thus is slower. I don't know what exactly you mean by"reliability" at high speed, but the NAND gate is faster.

The logical effort of a gate is basically the product of its input capacitanceand drive resistance, divided by the input capacitance and driveresistance of an inverter, which is used for reference.

http://opt/scribd/conversion/tmp/scratch4/javascript:;



The typical inverter has an input capacitance of 3 units, since the PMOS istypically twice the size of the NMOS. The inverter's drive resistance istaken to be 1, and thus the bottom of the fraction is always 3.

To achieve the same drive strength as the inverter, the 2-input NAND

must have an input capacitance of four units (as seen by each input), andthus its logical effort is taken to be 4/3. The 2-input NOR has an inputcapacitance of five units (as seen by each input) and thus its logical effortis taken to be 5/3.

More complex gates necessarily have more input capacitance than theinverter, and thus are slower, given identical output drive strengths.Logical effort captures this in a single number; gates with higher logicaleffort are slower.

Applications of universal gates

NOR & NAND gates are two pillars of logic and logic circuits are widelymade by them only. Logic circuits include devices such as multiplexers,registers, arithmetic logic units (ALUs) and computer memory all the wayup through complete micro processors which contain 100 million logic

gates.In computer memory the most debated application of these gates is flashmemory.

Flash memory, it is a type of non-volatile memory allocation. Flashmemory stores information in an array of memory cells made fromfloating-gate transistors. Flash is used as secondary storage devices suchas hard disks, memory cards, memory stick, micro SD, xD-Picture Card, Intelligent Stick.etc. The most commonly used flash memories are NOR flash & NAND flash.

Both have their own qualities and drawbacks.NOR flash



NOR flash memory wiring and structure on siliconIntel saw the massive potential of the invention and introduced the firstcommercial NOR type flash chip in 1988.In NOR gate flash, each cell has one end connected directly to ground,and the other end connected directly to a bit line. This arrangement iscalled "NOR flash" because it acts like a NOR gate when one of the wordlines is brought high, the corresponding storage transistor acts to pull theoutput bit line low.

Programming

Programming a NOR memory cell (setting it to logical 0), via hot-electron

injection.

http://en.wikipedia.org/wiki/File:Flash-Programming.svg

http://en.wikipedia.org/wiki/File:NOR_flash_layout.svg



A single-level NOR flash cell in its default state is logically equivalent to abinary "1" value, because current will flow through the channel underapplication of an appropriate voltage to the control gate. A NOR flash cellcan be programmed, or set to a binary "0" value, by the followingprocedure:

• an elevated on-voltage (typically >5 V) is applied to the CG

• the channel is now turned on, so electrons can flow from the sourceto the drain (assuming an NMOS transistor)

• the source-drain current is sufficiently high to cause some highenergy electrons to jump through the insulating layer onto the FG,via a process called hot-electron injection

Erasing

Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling.

To erase a NOR flash cell (resetting it to the "1" state), a large voltageof the opposite polarity is applied between the CG and source, pulling theelectrons off the FG through quantum tunneling. Modern NOR flashmemory chips are divided into erase segments (often called blocks orsectors). The erase operation can only be performed on a block-wisebasis; all the cells in an erase segment must be erased together.

Programming of NOR cells, however, can generally be performed one byteor word at a time.

NAND flash:

http://en.wikipedia.org/wiki/File:Flash_erase.svg



NAND flash memory wiring and structure on silicon

NAND flash architecture was introduced by Toshiba in 1989

NAND flash also uses floating-gate transistors, but they are connected in away that resembles a NAND gate several transistors are connected inseries, and only if all word lines are pulled high (above the transistors' V T)is the bit line pulled low. These groups are then connected via someadditional transistors to a NOR-style bit line array.

To read, most of the word lines are pulled up above the V T of aprogrammed bit, while one of them is pulled up to just over the V T of anerased bit. The series group will conduct (and pull the bit line low) if theselected bit has not been programmed.

Despite the additional transistors, the reduction in ground wires and bit

lines allows a denser layout and greater storage capacity per chip. Inaddition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free).Manufacturers try to maximize the amount of non-faulty storage byshrinking the size of the transistor below the size where they can be madereliably, to the size where further reductions would increase the numberof faults faster than it would increase the total storage available.

NAND flash uses tunnel injection for writing and tunnel release for erasing.NAND flash memory forms the core of the removable USB storage devicesknown as USB flash drivers and most memory card formats available

today.

http://en.wikipedia.org/wiki/File:Nand_flash_structure.svg

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