2007 03 12 Ling25 MOSFET Capacitances

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    MOSFET Capacitances

    CopyrightCopyright The McGrawThe McGraw--Hill Companies, Inc. Permission required for reproduction or disHill Companies, Inc. Permission required for reproduction or display.play.

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    Device Capacitances

    There is some capacitance between every

    pair of MOSFET terminals.Only exception: We neglect the

    capacitance between Source and Drain.

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    Gate to Substrate capacitance

    C1 is the oxide capacitance (between Gateand channel)

    C1 = WLCOX

    C2 is the depletion capacitance between

    channel and Substrate

    C2 = WL(qsiNsub/(4F))1/2 = Cd

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    Gate-Drain and Gate-Source Overlap

    Capacitance

    C3

    and C4

    are due to overlap between the gate

    poly-silicon and the Source and Drain regions.

    No simple formulas for C3 and C4: It is incorrect to

    write C3=C4=WLDCOX because of fringing electricfield lines.

    We denote the overlap capacitance per unit widthas Cov

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    Source-Substrate and Drain-Substrate

    Junction Capacitances

    Again, no simple formulas for C5 and C6:See right figure: Each capacitance should be

    decomposed into two components:

    Bottom-plate capacitance, denoted as Cj, which

    depends on the junction area.

    Side-wall capacitance Cjsw which depends on theperimeter of the junction.

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    Source-Substrate and Drain-Substrate

    Junction Capacitances

    In MOSFET models Cj and Cjsw are usually given ascapacitance-per-unit-area, and capacitance-per-unit-

    length, respectively.

    Cj = Cj0 / [1+VR/B]m where VR is the junctions reversevoltage, B is the junction built-in potential, and m

    typically ranges from 0.3 to 0.4

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    Examples (both transistors have

    the same Cj and Cjsw parameters)

    Calculate CDB and CSB for each structure

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    Left structure

    CDB=CSB = WECj + 2(W+E)Cjsw

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    Layout for Low Capacitance (see

    folded structure on the right)

    Two parallel transistors with onecommon Drain

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    Layout for Low Capacitance (see

    folded structure on the right)CDB=(W/2)ECj+2((W/2)+E)Cjsw

    CSB=2[(W/2)ECj+2 ((W/2)+E)Cjsw]=

    = WECj +2(W+2E)Cjsw

    Compare to the left structure:

    CDB=CSB = WECj + 2(W+E)Cjsw

    CSB slightly larger, CDB a lot smaller. Both

    transistors have same W/L

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    CGS

    ,CGD

    at Cutoff

    CGD=CGS=CovW

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    CGB

    at Cutoff

    C1 = WLCOX,C2= WL(qsiNsub/(4F))1/2 =CdCGB=C1C2/(C1+C2)= WLCOXCd/(WLCOX+Cd )

    L is the effective length of the channel.

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    CDB

    and CSB

    at all modes

    Both depend on the reverse voltages Drain toSubstrate and Source to Substrate

    Recall Cj = Cj0 / [1+VR/B]m

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    CGS

    ,CGD

    at Triode Mode

    If VDS

    is small enough, we can assume

    VGSVGD Channel uniform Gate-Channel

    capacitance WLCOX is distributed uniformly

    CGD=CGS (WLCOX)/2+CovW

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    CGS

    ,CGD

    at Saturation Mode

    CGD

    CovW because there isnt much ofa channel near Drain.

    (It can be proved):CGS=2WLeffCOX/3+WCov

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    CGB at Triode and Saturation

    Modes

    CGB is negligible, because channel acts as ashield between Gate and Substrate. That is, if

    VG varies, change of charge comes from Source

    and Drain, and not from the Substrate!

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    MOS Small Signal Model with

    Capacitance

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    C-V of NMOS

    In Weak Inversion CGS is a series

    combination of COX-capacitance and Cdep-

    capacitance Low capacitance peak nearVGSVTH

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    Gate Resistance