MOSFET Devices - SCU€¦ · MOSFET Devices S. Saha HO #14: ELEN 251 - MOSFET Fundamentals Page 1...
Transcript of MOSFET Devices - SCU€¦ · MOSFET Devices S. Saha HO #14: ELEN 251 - MOSFET Fundamentals Page 1...
MOSFET Devices
HO #14: ELEN 251 - MOSFET Fundamentals Page 1S. Saha
• Metal-oxide-semiconductor field-effect transistors (MOSFET) are the building blocks of modern VLSI circuits with the areas of applications:– microprocessors– dynamic memories– and so on.
• In modern VLSI circuits:– two types of MOSFET structures are used:
♦ nMOSFETs: p-substrate with n+ source-drain♦ pMOSFETs: n-substrate with p+source-drain
– nMOSFETs and pMOSFETs are used together and is called the complementary MOSFETs (CMOSFETs).
A. CMOS Device Structure
HO #14: ELEN 251 - MOSFET Fundamentals Page 2S. Saha
MOSFETs are four terminal devices as shown in the CMOS structure below:
Gateoxide
Channel Source-Drain
p-welln-well
STI
n+ Poly p+ Poly
n+ n+ p+ p+
NMOS PMOS
DielectricSpacer
p-substrate
Dual-polyGate
Halo
1 Gate: thermally grown oxide on Si-substrate with conducting electrode on the top.
2 Source-drain: heavily-doped regions at the two ends of the gate contacted with metal interconnects.
3 Body: substrate connected with metal interconnect.
CMOS Structure: A Typical Layout
HO #14: ELEN 251 - MOSFET Fundamentals Page 3S. Saha
p-substrate
p-well n-well
n+
NMOS PMOS
n+ p+p+STI
Gate oxideHalo
P+ polySpacerN+ poly
B. A Typical CMOS Fabrication
HO #14: ELEN 251 - MOSFET Fundamentals Page 4S. Saha
1 Shallow trench isolation (STI):– grow oxide and Mask #1– etch oxide– etch silicon– deposit oxide to form STI.
2 Mask #2: N-well/threshold adjust implant:– implant P– drive-in and grow oxide– clean.
3 Mask #3: P-well/threshold adjust implant:– implant B– drive-in B– clean.
P−
P-well N-well
Photoresist
P-well N-well
Photoresist
CMOS Fabrication
HO #14: ELEN 251 - MOSFET Fundamentals Page 5S. Saha
4 Gate formation:– Clean silicon surface– grow gate oxide– deposit poly-Si gate
electrode.
5 Mask #4: Gate definition– etch poly-Si– etch oxide– grow masking oxide.
6 Mask #5: N+ source / drain extension (SDE) and p-halo:– As SDE implant– B/BF2 halo implant– clean.
Gate oxide Poly-Si
P-well N-well
Photoresist
P-Well N-WellHalo
CMOS Fabrication
HO #14: ELEN 251 - MOSFET Fundamentals Page 6S. Saha
7 Mask #6: P+ SDE and n-halo:– B/BF2 SDE implant– As/Sb halo implant– clean.
8 Deep s/d (DSD) formation:– spacer deposition and etch– Mask #7 - N+ DSD
♦ As implant– Mask #8 - P+ DSD
♦ B/BF2 implant– dopant activation (RTA).
9 Interconnection:– Mask #9- contact opening– Mask #10: define metal.
Photoresist
P-Well N-Well
P-Well N-Well
NMOS PMOS
C. MOSFET Circuit Symbols
HO #14: ELEN 251 - MOSFET Fundamentals Page 7S. Saha
n+
n+
P Body
D
S
G B
D
S
G
D
S
GB
D
S
G
nMOSFETs
G = gate; D = drain; S = source; B = Bulk/BodypMOSFETs
p+
p+
N Body
D
S
G
D
S
GB
D
S
GB
D
S
G
D. Basic Features of MOSFETs
HO #14: ELEN 251 - MOSFET Fundamentals Page 8S. Saha
• Non-uniform channel doping profile:– vertically due to threshold implants– laterally due to halo implants
• Parasitic elements:– terminal resistances
♦ source (RS), drain (RD), and gate (RG)
– diodes♦ B → S (BS) and B → D (BD)
– capacitance♦ S → B (CBS) and D → B (CBD) junction capacitances♦ G → S (CGSO) and G → D (CGDO) overlap capacitance♦ G → B (CGBO)
Basic Features of MOSFETs - Capacitances
HO #14: ELEN 251 - MOSFET Fundamentals Page 9S. Saha
E. Equivalent Circuit: DC Model
HO #14: ELEN 251 - MOSFET Fundamentals Page 10S. Saha
• The simplest dc model for an MOS structure includes:– parasitic resistances RS, RD, and RG– parasitic diodes
♦ BS from B → S♦ BD from B → D.
• IDS = drain current from S → D.
• IG,leakage = gate leakage current through the oxide due to tunneling or due to high field effect.
Equivalent Circuit: Dynamic Model
HO #14: ELEN 251 - MOSFET Fundamentals Page 11S. Saha
• The basic MOSFET model consist of:– junction capacitances CBS
and CBD between S → B and D → B, respectively.
– overlap capacitances CGDO and CGSO due to G → S and G → D overlap, respectively.
– G → B capacitance CGBO– BS and BD diodes.
• ID as a function of VG, VD, and VB models the dc MOS device performance.
MOSFET Device Modeling Approach
HO #14: ELEN 251 - MOSFET Fundamentals Page 12S. Saha
VD
ID
5
4321
VG −VthID
VGVth
VD = 50 mV
• In MOSFET devices:– IDS = f(VGS, VDS, VBS).– a gate voltage VGS ≡ Vth is required to turn-on (off) the device. Vth
depends on process technology and device dimensions.
• The basic modeling approach is to develop models for:– threshold voltage, Vth with technology and geometry dependence– drain current, IDS as a function of applied biases– capacitances for dynamic response.
F. MOS Fundamentals: 1. Energy Band Diagram
HO #14: ELEN 251 - MOSFET Fundamentals Page 13S. Saha
• Note:– three materials in contact, EF = constant at equilibrium– currents through SiO2 are very small– holes flow from semiconductor → metal on contact– e− flow from metal → semiconductor on contact– bands will bend downwards in silicon at the interface (ΦM < Φs).
Metal(Al)
Oxide(SiO2)
Semiconductor(p-Si)
E0
qΦM= 4.1eV
EFM
qχox=0.95eV
Eg ≈ 8eV
Ec
Ev
EF
E0
Ec
EFEv
qΦS=5eVqχS= 4.15eV
Eg=1.1eVMOS structure
p-Si
SiO2
MOS System at Equilibrium
HO #14: ELEN 251 - MOSFET Fundamentals Page 14S. Saha
Note:• Abrupt transition in Ec and Ev levels at
the material interfaces.
• A typical potential drop ~ 0.6 eV across SiO2. This depends on EF in Si. This potential can be supported because no current flows through SiO2.
• Substantial barriers exist to current flow from:
– S → M – M → S.
• Depletion region exists near the surface because EF near the surface is further from Ev than the bulk region.
At equilibrium (V = 0).
Ec
Ev
EF
Al SiO2 p-Si
3.7eV
3.20eV3.15eV
0.6eVEc
Ev
MOS System - Accumulation
HO #14: ELEN 251 - MOSFET Fundamentals Page 15S. Saha
Applied Bias: negative voltage on Al
qVEFM EcEFEv
Al SiO2 p-Si
− ve
• EF is still constant in the Si since SiO2 prevents any current flow.• EF is closer to Ev at the surface.∴ more holes near the surface. ⇒ ACCUMULATION.
MOS System - Inversion
HO #14: ELEN 251 - MOSFET Fundamentals Page 16S. Saha
Applied Bias: positive voltage on Al
qVEFM
Ec
EFEv
Al SiO2 p-Si
+ ve
EiφFφs
QG
QdQn
• EF is still constant in the Si (I = 0).• EF is closer to Ec at the surface than it is to Ev.
∴ more e- than holes at the surface. ⇒ INVERSION.
F. MOS Fundamentals: 2. Surface Carrier Densities
HO #14: ELEN 251 - MOSFET Fundamentals Page 17S. Saha
At any point in silicon, we can calculate the hole and e-concentrations using:
If φs = surface potential and φF = bulk potential so that the potential drop across the depletion region = (φF − φs), Then, the surface concentrations are:
Since we know φF from the bulk doping, if we know φs for a given applied VG, then we can calculate the e- and holesurface concentrations.
ennenp
kTq
i
kTq
iφ
φ
=
= − (1)
(2)
eNnn
eNp
kTq
A
is
kTq
As
sF
sF
)(2
)(
φφ
φφ
−
−−
=
= (3)
(4)
G. MOS Capacitors: 1. Long Channel Vth Model
HO #14: ELEN 251 - MOSFET Fundamentals Page 18S. Saha
(a) Accumulation: VG > 0
Co
+
n-Si
SiO2
e−↑
VG
− +
Co
V
C
Note:• e- are attracted to the surface.• The small-signal capacitance per unit area is given by:
Co = εox/tox where
εox = dielectric constant in the oxide tox = oxide thickness.
C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 19S. Saha
(b) Depletion: VG < 0
−
n-Si
SiO2
e−
↓
+ + + + + ++ + + + + +
Ionizeddonoratoms Co
Cd − +
Co
V
C
• e- are repelled from the surface resulting in a depletion region.• The small-signal depletion capacitance per unit area is:
Cd = εs/xd
where εs = dielectric constant of silicon xd = width of the depletion layer.
• The total capacitance: C = CoCd/(Co + Cd)
C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 20S. Saha
(c) Inversion: VG << 0
− −
n-Si
SiO2
e−
↓
+ + + + + ++ + + + + +
Inversionlayer
holes
xdmax
Co
Cdmin − +
Co
V
C
Cmin
• Minority-carriers pile-up near the SiO2/Si interface.
• In strong INVERSION:– xdmax = maximum width of depletion region is a constant,– Cd = Cdmin is a constant.
• For VG between ACCUMULATION and strong INVERSION: – xd ∝ VG
1/2.
C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 21S. Saha
Let us consider the depletion condition (b), then: Q = QG = − Qs = − qNDxd (5)
where, xd = width of the depletion region ND = donor concentration/cm3.
Assuming that ND is independent of distance (uniform substrate doping), then from Poisson’s equation we have:
n-Si
SiO2
+ + + + + ++ + + + + + xd
VG
Qs
potential Surface 2
where
siliconin Potential 1
2
2
2
2
==
=⎟⎟⎠
⎞⎜⎜⎝
⎛−=∴
−=−=
εφ
φφ
εερφ
os
dDs
ds
os
D
os
KxNqxx
KNq
Kxdd (6)
(7)
(8)
C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 22S. Saha
n-Si
+ + + + + ++ + + + + + xd
VG
φs
toxVo
Assume, tox = oxide thickness Vo = potential across oxide
Then, the applied voltage is given by:
ε
φ
os
dDoxox
soG
KxNq
Et
VV
2
2
+=
+=
(9)
We know from Gauss’ Law, the electric displacement must be constant across Si/SiO2 interface, so that: KoEox = KsEs (10)
where Ko and Ks are dielectric constants of oxide and Si, respectively Eox & Es are ε-fields in oxide & in Si at the interface, respectively.
C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 23S. Saha
From (10) we get: Eox = Es(Ks/Ko) (11)
Substitute for Es in (11) from Gauss’ Law:
Then, from (9) we get:
Using (5) we have:
ε
εε
ooox
osos
ss
KQ
E
KQ
KQ
E
−=⇒
−=−= (12)
εε os
dD
oo
oxG K
xNqK
tQV2
2
+−= (13)
NqKQ
KtQV
Dosoo
oxG
εε 2
2
+−= (14)
C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 24S. Saha
From (14) we get:
This is the amount of charge on the metal plate or in the depletion region when the depletion is taking place.
The small signal-capacitance of the structure is given by:
VNqKK
tNqKK
tNqKQ GDoso
oxDs
o
oxDs ε22
+⎟⎟⎠
⎞⎜⎜⎝
⎛±=
VNqKK
tNqK
NqKVd
dQC
GDoso
oxDs
Dos
G
ε
ε
22
+⎟⎠
⎞⎜⎝
⎛==
VtKNq
KCC
GoxsD
ooo2
221
1
ε+
=∴ (15)
(Here, Co = Koεo/tox = Oxide cap/area)
C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 25S. Saha
− +
Co
V
C
Cmindepletion, C ∝ 1/√V
Vth
inversion, C is fixed
During depletion, C falls as 1/√(V).
However, when the surface inverts, C reaches a minimum value.
When an inversion layer forms, we have:
φF
φs EFEi
xd
xx dd
Fs
max≅−≅ φφ
⎭⎬⎫
⎩⎨⎧−+
NP,ln2)(@
nN
qkT
VVi
DthGs ±==∴φ (16)
( )φεF
D
osd
NqKxand 22, max = (17)
C − V Characteristics − Strong Inversion
HO #14: ELEN 251 - MOSFET Fundamentals Page 26S. Saha
In strong inversion,• φs = 2φF.
• the inversion layer width < 50 A.
• a higher φs or ε-field tends to confine inversion charge closer to the surface.
Generally, inversion-carriers must be treated quantum-mechanically (QM) as a 2-D gas. According to QM model:
• inversion layer carriers occupy discrete energy bands• peak distribution is 10 − 30 A away from the surface.
0.0E+00
2.0E+18
4.0E+18
6.0E+18
8.0E+18
1.0E+19
1.2E+19
0 50 100 150 200
Distance from surface, x (A)
Inve
rsio
n la
yer c
once
ntra
tion
(cm
-3)
N(sub) = 1016 cm-3
φs = 0.88 V
φs = 0.85 V
C − V Characteristics − Vth
HO #14: ELEN 251 - MOSFET Fundamentals Page 27S. Saha
When xd reaches xdmax, C reaches a minimum in the C − V plot and we have:
Co
Csmin
Co
VG
C
Cmin
Vth
nN
NKqkTxd
KCs
i
D
Dos
os
ln41
2max
min
ε
ε ==(18)
The threshold voltage is defined as the gate voltage necessary to just reach the inversion (that is, φs = −φF, xd = xdmax):
VV oFth +=∴ φ2
C − V Characteristics − Vth
HO #14: ELEN 251 - MOSFET Fundamentals Page 28S. Saha
dxx
KNq
KKt
EtVd
o os
D
o
soxF
oxoxFth
∫+=
+=max
2
2
εφ
φ
[use (11) for Εox and expression for Es]
Now, using the expression for Co and (17) for xdmax we get:
CKNq
Vo
FosDFth
)2(22
φεφ += (19)
In (19), we have assumed that QI ≈ 0 at Vth.
Co
VG
C
− +
Ideal
MeasuredN-typeSubstrate
Comparison of Ideal andthe measured C − V plot
C − V Characteristics − Vth
HO #14: ELEN 251 - MOSFET Fundamentals Page 29S. Saha
Actual C - V curves are shifted laterally from the theoretical curve due to:– Work function difference between the metal and silicon – Qf : charge at the Si/SiO2 interface.
CKNq
C
QqV
o
FosDF
o
fMSth
)2(22
φεφφ ±±−= (20)
(assume Qf is rightat Si/SiO2 interface)
+ p-type substrate− n-type substrate
Thus, by measuring a C - V curve for a particular process– tox can be calculated from Co
– ND can be calculated from Cmin
– Qf can be calculated from the difference between the ideal and experimental curves.
C − V Characteristics − Vth
HO #14: ELEN 251 - MOSFET Fundamentals Page 30S. Saha
If VSub = back bias = voltage between source and body: VSub < 0 for nMOSFETs VSub > 0 for pMOSFETs.
Then,
(21)C
VKNq
C
QqV
o
SubFosDF
o
fMSth
)2(22
±±±−=
φεφφ
FBV=
φφγ FSubFthth VVV 220 −±±=∴ (22)
factorbody2
Where
≡=C
KNq
o
osD εγ (23)
Low-Frequency C − V Characteristics
HO #14: ELEN 251 - MOSFET Fundamentals Page 31S. Saha
Co
VG
C
− +
Highfrequency
N-typeSubstrate
Lowfrequency
Vth
Co
Cmin
Co
Cd CI
(Low freq.)
If the frequency of the applied signal is lower (<< 100 Hz) than the reciprocal of the minority-carrier response time:
– inversion charge (QI) is able to follow the applied signal
– QI varies with φs and Cs depends on QI .
∴ C↑ as |VG|↑.
– At higher |VG|, C increases back to Co.
G. MOS Capacitors: 2. Polysilicon Gates
HO #14: ELEN 251 - MOSFET Fundamentals Page 32S. Saha
At equilibrium (VG = 0). At Inversion (VG >> 0).
Ec
Ev
EF
n+ poly SiO2 p-Si
Ei
φF
Ec
Ev
EF
n+ poly SiO2 p-Si
EiφS
VG
Ei
Ev
EFφp
Ec
Vox
Work-function difference:n+poly with p-type Si: φMS = − Eg/2 − (kT/q)ln(NA/ni)p+poly with n-type Si: φMS = Eg/2 + (kT/q)ln(ND/ni)
MOS Capacitors - Polysilicon Depletion Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 33S. Saha
Note:• Capacitance at inversion, Cinv
does not return to Cox.• Cinv shows a maximum value,
Cmax < Cox.• Cmax↑ as the polysilicon
doping concentration, Np↑.• As Np↑, depletion width↓
∴ Cmax → Cox for higher Np.
Total capacitance at strong inversion is given by: 1/C = 1/Cox + 1/Csilicon + 1/Cpoly
As VG↑, Csilicon↑ but xd(poly)↑ ⇒ Cpoly↓. ∴Low frequency C − V shows a local maximum at a certain VG.
G. MOS Capacitors: 3. Inversion Layer Quantization
HO #14: ELEN 251 - MOSFET Fundamentals Page 34S. Saha
• Typically, near the silicon surface, the inversion layer chargesare confined to a potential well formed by:– oxide barrier– bend Si-conduction band at the surface due to the applied gate
potential, VG.
• Due to the confinement of inversion layer e− (in p-Si): – e- energy levels are grouped in discrete sub-bands of energy, Ej
– each Ej corresponds to a quantized level for e− motion in the normal direction.
E2E1E0
Edge of EC
Distance from the surfaceBottom ofthe well
E
Inversion Layer Quantization
HO #14: ELEN 251 - MOSFET Fundamentals Page 35S. Saha
• Due to Quantum Mechanical (QM) effect, the inversion layer concentration:– peaks below the SiO2/Si interface− ≈ 0 at the interface determined by the boundary condition of
the e- wave function.
• Solve Schrodinger and Poisson Eq self-consistently with the boundary conditions for wave function equal to:– 0 for x < 0 in oxide– 0 at x = ∞.
QM
Classical
Depth
n (c
m-3
)
QM Effect on Device Performance
HO #14: ELEN 251 - MOSFET Fundamentals Page 36S. Saha
• At high fields, Vth↑ since more band bending is required to populate the lowest sub-band, which is some energy above the bottom of EC.
• Once the inversion layer forms below the surface, a higher VGover-drive is required to produce a given level of inversion charge density. That is, the effective gate oxide thickness, tOX
eff↑ by: ∆tOX = (εox/εsi)∆z (24)
• Inversion layer quantization can be treated as bandgap widening due to an increase in the effective bandgap by ∆Eg given by:
Here, ∆Eg = EgQM − EgCL. (25) ⇒ ni↓ and n↓ due to QM effect.
kTE
CLi
QMi
g
enn 2∆
−= (25)
H. Geometry Effect on Vth: 1. Short Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 37S. Saha
For short channel devices, Vth↓ as L↓. Many researchers have attempted to analyze this 2-D problem.
We will consider only the simplest approach (by Yau) to understand the basic idea of short channel effect.
Assume: – VD = 0 = VS− φs = 2φF @ VG = Vth and φs
is unaffected by short channel effect.
– xd = xdj
From charge conservation: QG + Qox + QI + QB = 0 (26)
Also,
whereo
BFFBth C
QVV ++= φ2 (27)
)2(2 SubFAosB VNqKQ +−= φε (28)
n+
P
L
rj n+L′
VG VDVS
xd
VSub
xdj
Short Channel Effect (SCE)
HO #14: ELEN 251 - MOSFET Fundamentals Page 38S. Saha
From first order MOS theory:
Now, let us assume that only the charge inside the trapezoid is supported by the gate, i.e. the junctions support the remaining charge. (This implies that QB is smaller than the long channel device and therefore, for a given VG, QI is larger to maintain charge neutrality. And, Vth↓).
The total charge in the trapezoid is:
QB′L = qNAxd[(L + L′)/2] (30)
where, QB′ < QB because L′ < L.
∴In Eq (27), QB is replaced by QB′.
( )SubFA
osd V
NqKx += φε 22
(29)
n+
P
L
rj n+L′
VG VDVS
xd
VB
xdj
Short Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 39S. Saha
From Fig. on the right, we get: (L−L′)/2
xdxd
rj
rj
(31)
( )
( )
( )
Lr
rx
LLL
rrxrrxrLLor
xxrrLLor
xrxrLL
j
j
d
jj
djjdj
ddjj
djdj
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
−+−=′+
∴
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
−+=−+=′−
−+=+′−
+=+⎟⎠⎞
⎜⎝⎛ +
′−
12112
12122
,
2,
222
222
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
−+−=Lr
rx
QQ j
j
dBB 1211' (32)
Using (29) and (31) in (30), we can show that:
Short Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 40S. Saha
Thus, if we assume that the effect of non-uniform QBdistribution can be averaged over L, then:
This is the desired result that predicts Vth as a function of L, rj and xd (or NA) for VD = 0.
Note: 1) ∆Vth ∝ 1/L. 2) As rj↓, ∆Vth↓, shallow junctions are preferred. 3) For large L↑, ∆Vth → 0 and the long channel form applies. 4) NA shows up in xd and QB. ∴ NA affects both Vth and ∆Vth
5) VSub is included in xd as well.
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
−+−++=Lr
rx
CQVV j
j
d
o
BFFBth 12112φ (33)
H2. Drain Induced Barrier Lowering (DIBL)
HO #14: ELEN 251 - MOSFET Fundamentals Page 41S. Saha
To this point we have modeled the effect of the drain voltage in short channel devices as a reduction in Vth.
n+
P
L
rj n+xd L4L3
( )DS
A
sDSbis
eff
VqN
VVL
LLLL
∝−+
=
−−=
φε24
43
Currents in the device (sub-threshold as well as “normal” high currents) are then increased because Leff↓ and Vth↓.
An alternative explanation of these effects is called drain-induced barrier lowering (DIBL). This phenomenon, in essence, is identical to ∆Vth modeling or SCE we discussed before.
Drain Induced Barrier Lowering (DIBL)
HO #14: ELEN 251 - MOSFET Fundamentals Page 42S. Saha
The drain bias lowers the potential barrier between source and channel and hence increases the current.
In principle, it seems possible to derive an analytical model to estimate ∆φs as a function of ∆L and VD. However, such models do not exist. Thus, only analytical models for SCE are based on charge sharing approaches.
In reality, 2-D computer simulations have to be used to analyze DIBL. If the surface region is implanted to shift Vth, then DIBL may occur
beneath the surface where the doping is lighter. Therefore, often a deep heavily doped channel implant is used to
prevent the drain potential from “punching through” to the source.
H. Geometry Effect on Vth: 3. Narrow Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 43S. Saha
In addition to channel length effects on Vth, small channel widths, also, affect Vth. These effects can be understood physically as follows:
Figure shows the MOS cross-section along the channel width direction.
The depletion layer cannot abruptly change from deep to shallow.Therefore, the transition region and some spreading of field lines from gate outside W.
Thus, QG supports some charge outside W. As a result, QI↓ and Vth↑.
P
QI QB
W
Narrow Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 44S. Saha
Consider the uniformly doped substrate with VD = 0.
P
xd
W
αxd
QBW = triangle area charge under thick oxide that is supported by gate.
n+
P
L
rj n+xd
QBL = trapezoidal area charge supported by gate (Yau).
The parameter α depends on oxide thickness, shape of field oxide edge, substrate doping, field threshold adjustment implant, and so on.
It is likely that α has to be experimentally determined.
Narrow Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 45S. Saha
The charge inside the volume is (1/2)QBW. The shape is rectangular on top, the sides are triangular and slope inward.
We know from SCE:
The charge contained in the volume above can be shown to be:
Now, we assume that the narrow width and short channel effects can be simply superimposed so that the total charge supported by the gate is given by: QT = QBL + QBW
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
−+−=Lr
rxLWxqNQ j
j
ddABL 1211 (34)
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
−+−=Lr
rxLxqNQ j
j
ddABW 3
212112α (35)
Narrow Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 46S. Saha
The charge contained in the volume can be shown to be:
The term in front of the brackets can be recognized as the bulk charge which would be present in a long and wide channel device so that:
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎟⎟⎠
⎞⎜⎜⎝
⎛−+⎟
⎠⎞
⎜⎝⎛ +−+=
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
⎟⎟⎠
⎞⎜⎜⎝
⎛−+−+⎟
⎟⎠
⎞⎜⎜⎝
⎛−+−=
+=
1213211
1213211211
j
ddjddA
j
djd
j
djdA
BWBLT
rx
Wx
Lr
WxLWxqN
rx
Lr
Wx
rx
Lr
LWxqN
QQQ
αα
α
(36)
CQ
C
QV
o
TF
o
fMSth ++−= φφ 2
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎟⎟⎠
⎞⎜⎜⎝
⎛−+⎟
⎠⎞
⎜⎝⎛ +−+++−=∴ 121
32112
j
ddjd
o
BF
o
fMSth r
xWx
Lr
Wx
CQ
CQ
V ααφφ (37)
Narrow Channel Effect
HO #14: ELEN 251 - MOSFET Fundamentals Page 47S. Saha
Note that if L and W → ∞, the normal long channel Vth Eq is obtained.
Summary:♦ L↓ ⇒ Vth↓
♦ W↓ ⇒ Vth↑
♦ xd↑ ⇒ Vth more sensitive to L and W (i.e. lightly doped substrates and/or VSub increase problems).
♦ rj↑ ⇒ Vth more sensitive to L (i.e. deep junctions undesirable).♦ α↓ ⇒ minimizes Vth variation due to narrow W.
⎥⎥⎦
⎤
⎢⎢⎣
⎡
⎟⎟⎠
⎞⎜⎜⎝
⎛−+⎟
⎠⎞
⎜⎝⎛ +−+++−=∴ 121
32112
j
ddjd
o
BF
o
fMSth r
xWx
Lr
Wx
CQ
CQ
V ααφφ (38)
)2(2 where BSFAosB VNqKQ +−= φε
I. Effect of Channel Doping on Vth
HO #14: ELEN 251 - MOSFET Fundamentals Page 48S. Saha
Assuming Nsub = constant, we showed :
where
In MOSFET devices Nsub varies vertically as well as laterally. Therefore, for accurate modeling of Vth, non-uniform channel doping concentration must be considered.
CKNq
C
QqV
ox
FossubF
ox
fMStho
|2|22
φεφφ ±±−= (40)
( )φφγ FSubFthth VVV 220 −±±=∴ (39)
factorbody2
≡=C
KNq
ox
ossub εγ (41)
Non-uniform Channel Doping Profile
HO #14: ELEN 251 - MOSFET Fundamentals Page 49S. Saha
I1. Vth Model due to Non-uniform Vertical Profile
HO #14: ELEN 251 - MOSFET Fundamentals Page 50S. Saha
• The doping concentration may be higher or lower at the Si/SiO2interface depending on Vth target.
• Due to the non-uniform body doping, γ = f(VSub).
• Let us model the non-uniform vertical doping profile by a step function shown below:– NCH = uniform shallow doping concentration– NSub = uniform deep doping concentration– Xdx = depletion width @ Vsub = Vbx; NSub= NCH.
• At VSub > Vbx, we can write the general expression:
(VSub and Vbx < 0 for NMOS and > 0 for PMOS).
Depth
Con
cent
ratio
n
Xdx
Model
Actual
( )( ) bxSubbxFSubF
FbxFthth
VVVV
VVV
>−−−+
−−+=
for 22
22
2
10
φφγ
φφγ
(42)
Non-Uniform Vertical Channel Profile
HO #14: ELEN 251 - MOSFET Fundamentals Page 51S. Saha
Here
In general (42) is complex and a unified expression for Vth is used to model the non-uniform vertical channel doping profile:
where ♦ K1 and K2 are the key parameters to model the vertically non-
uniform doping effect.♦ K1 and K2 are determined by fitting (43) to the measured Vth
data♦ VSub < 0 for NMOS ♦ VSub > 0 for PMOS.
( ) SubFSubFthth VKVKVV 210 22 −−−+= φφ (43)
CKNq
CKNq
ox
ossub
ox
osCH εγεγ2
and2
21 ==
I2. Effect of Non-uniform Lateral Channel Profile
HO #14: ELEN 251 - MOSFET Fundamentals Page 52S. Saha
For sub-micron devices, Vth is found to increase first as L↓and then decrease with further reduction in L.
The anomalous Vth↑ as L↓ is due to non-uniform lateral channel doping concentration caused by: • an enhanced diffusion of channel implant induced by the damage from S-D implant.• boron segregation to the S-D implant regions.
Gate
Std O2poly-reox
injectionof interstitialduring poly-reox.
S D
L
Vth
Non-uniform Lateral Profile due to S/D Processing
HO #14: ELEN 251 - MOSFET Fundamentals Page 53S. Saha
0.35 µm nMOSFETs 1.0 µm nMOSFETs
2-D non-uniform lateral boron channel profile after S-D processing
Non-Uniform Lateral Profile due to Halo Implant
HO #14: ELEN 251 - MOSFET Fundamentals Page 54S. Saha
DSD
Lg = 100 nmHalo
Lg = 250 nm
DSD
Halo
• Halo implant around source-drain extensions (SDE):– significantly increases the channel doping concentration as L↓– causes Vth↑ as L↓ (i.e. RSCE).
RSCE due to Halo Implant
HO #14: ELEN 251 - MOSFET Fundamentals Page 55S. Saha
0.10
0.15
0.20
0.25
0.30
0.35
0.40
20 60 100 140 180 220 260 300Leff (nm)
Vth (
V)
Strong haloModerate haloLow halo
nMOSFETsTOX(eff) = 2.7 nm
VDS = 50 mV; VBS = 0
• RSCE (i.e. Vth↑ with L↓) for Leff < 200 nm is due to halo implants around SDE.
• RSCE depends on halo doping concentration.
Vth Model for Non-Uniform Lateral Channel Profile
HO #14: ELEN 251 - MOSFET Fundamentals Page 56S. Saha
Similar to the previous case, we model the non-uniform lateral channel doping profile by a step function as shown below:
Let L = channel length LX = length of Halo-region NHalo = uniform concentration in LX
NCH = uniform concentration in L−2LX
If Neff is the average channel doping concentration, then the total charge Q is given by: Q = NeffL = NCH(L − 2LX) + NHalo(2LX)
Position along the channel
LX
N(x)
L
LXNCH
NHalo
⎥⎦⎤
⎢⎣⎡ +≡⎥
⎦
⎤⎢⎣
⎡ −+=∴
LNN
LL
NNNNN LX
CHX
CH
CHHaloCHeff 121 (44)
Vth Model for Non-Uniform Lateral Channel Profile
HO #14: ELEN 251 - MOSFET Fundamentals Page 57S. Saha
Where NLX is a fitting parameter extracted from the measured data and is given by:
Substituting Neff in (40) we get:CH
CHHaloXLX N
NNLN −≡ 2 (45)
φ
φφφφ
φφφ
φεφφ
FLX
th
FLX
FFox
fMS
FLX
Fox
fMS
ox
FoseffF
ox
fMStho
LNKV
LNKK
C
LNK
C
CKNq
C
QqV
211
21122
212
|2|22
10
11
1
⎟⎟⎠
⎞⎜⎜⎝
⎛−++=
⎟⎟⎠
⎞⎜⎜⎝
⎛−++++−=
⎟⎟⎠
⎞⎜⎜⎝
⎛+++−=
++−=′
(46)
Vth Model for Non-Uniform Lateral Channel Profile
HO #14: ELEN 251 - MOSFET Fundamentals Page 58S. Saha
Then from (43), Vth due to non-uniform lateral doping is given by:
Substituting V'tho from (46) we get:
Note:– K1 and K2 models the effect of non-uniform vertical channel
doping profile on Vth
– NLX models the non-uniform lateral profile on Vth:♦ at VSub = 0, as L↓, Vth↑ (RSCE) due to halo-profile.
( ) SubFSubFthth VKVKVV 210 22 −−−+′= φφ (47)
( )φ
φφ
FLX
SubFSubFthth
LNK
VKVKVV
211
22
1
210
⎟⎟⎠
⎞⎜⎜⎝
⎛−++
−−−+=
(48)
Home Work 5: Due May 19, 2005
HO #14: ELEN 251 - MOSFET Fundamentals Page 59S. Saha
1) MOS capacitors are fabricated on uniformly doped P-substrates with NA = 1x1017 cm−3, physical gate oxide thickness TOX = 6.7 nm, and N+ poly-silicon gate doping concentrations Np = 5x1018, 1x1019, and 5x1019 cm−3 as shown in the following C – V plots. Here C and Cox are the gate and oxide capacitances, respectively.
(a) Explain the observed variation in C/COX vs. Vg plots for each Np in the strong inversion region.
(b) Explain the observed increase in C/COX for Np = 5x1018 cm−3 and Vg ≥ 3.5 V.
(c) Describe the possible reasons for C/COX < 1 even for a heavily doped poly with Np = 5x1019
cm−3 in the accumulation as well as in the strong inversion regions?
Home Work 5: Due May 19, 2005
HO #14: ELEN 251 - MOSFET Fundamentals Page 60S. Saha
2) A p-type MOS-capacitor with NA = 1x1018 cm-3 and TOX = 3 nm was fabricated to characterize van Dort’s analytical bandgap widening quantum mechanical (QM) model we discussed in class. Due to inversion layer quantization, the increase in the effective bandgap ∆Eg = Eg
QM − EgCL ≅ 104
mV. Here EgQM and Eg
CL represent the QM and classical (CL) values of bandgap (Eg), respectively. Assume Qf = 0, VSUB = 0, and N+ poly gate.
(a) Show that the intrinsic carrier concentration due to QM effect is given by:
(b) Calculate the value of niQM at temperature T = 300oK.
(c) Calculate the value of threshold voltage Vth(CL) using the classical approach.
(d) Calculate the value of threshold voltage Vth(QM) due to QM effects.
(e) Calculate the shift ∆Vth due to QM effects.
kTE
CLi
QMi
g
enn 2∆
−=
Modeling Project: MOS Model Extraction
HO #14: ELEN 251 - MOSFET Fundamentals Page 61S. Saha
• 90-nm CMOS Technology:– complete models for nMOSFETs and pMOSFETs for logic design over
the temperature range, -55 to 125°C– select a MOS compact model of your choice (BSIM3/BSIM4/HiSIM)– justify why the model of your choice should be adequate for 90-nm
technology node.
• Modeling strategy:– selection of devices (W/L) over the design space– selection of data set for parameter extraction– measurement conditions and bias range– parameter optimization strategy and guidelines– temperature dependent parameters and extraction of temperature
coefficients– test/qualify the model and release to production.
Modeling Project: Final Report
HO #14: ELEN 251 - MOSFET Fundamentals Page 62S. Saha
The results of your modeling work are to be presented in an extended abstract form (3 to 4 pages maximum). The key points to be emphasized are the following:– selection of devices and reasons for your selection– data selection and how will you use specific data file to extract specific
model parameters of your selected model– measurement conditions for data collection data in tabular form
showing all bias conditions and temperature range you plan to use for your modeling
– a complete step by step strategy to extract model parameters from collected data set
– critical discussions of fitting errors to your data with the model equations.
– a typical model file including both p/n-channel devices. Use of extraction tool is not required. However, your report must be an
aid to device engineers for 90-nm compact model parameter extraction.