2005 Nanoscale MOSFET...

S.Deleonibus LETI - June 2005 YokohamaPanel session IFST 2005

2005

1

Nanoscale MOSFET fabrication

Lg~16nm

6893 P18

ConventionalConventional MOSFET architectureMOSFET architecture- 1.2nm SiO2 gate oxide- In situ doped polysilicon Gate- Channel : non intentionnaly adjusted but Super Halo SH :(only BF2 halos) or Non super Halo NSH : (B II + BF2 halos)

- As extensions - 30nm nitride spacers- As HDD Source and drain - RTP spike anneal 1050°C

Lgmin= 16nm

10-11

10-9

10-7

10-5

10-3

-0,5 0 0,5 1 1,5

Lg

= 29nmL

g= 16nm

I D(A

)V

G(V)

Lot 6893 P18B

Vd=50mV

Vd=1.5V

Channel : B 5keV

LDD 1.5 10 14cm-2

Halo 3.10 13cm-2 tilt 22°

W=10µmW=10µmTox=1.2nm

Bulk: improvement with superhalo

G. Bertrand et al., Proceedings ULIS 2003 SSE July 2004


2005

2

Limitation to transport

0

60

120

0

100

200

300

400

500

0,01 0,1 1 10

Rsd

>>2000 Ω .µm

Rsd

=1200 Ω .µm

Gm

max

(S/m

) @ V

d=50m

V

Gm

sat (S

/m) @

Vd=1

.5V

Lg

Low field mobilityLow field mobilitydegradationdegradation due due to halo to halo overlapoverlapmostlymostly in in the the case of case of efficient SCE controlefficient SCE control

Impact Impact atat roomroomtemperaturetemperature

G. Bertrand et al., Proceedings ULIS 2003 SSE July 2004


2005

3

From Fully Depleted SOI to Double Gate CMOSV

T(V

)

Tsi(nm)

Bulk or PD SOI like

FDSOI

Quantum

confinementN+ poly gate

J.Lolivier et al, ECS Spring meeting, Paris May 2003

SGMOS DGMOS

Lg=25nm

222

2

×=∞

sien T

nm

E hπQuantum confinement:

111 2

2ox

siAffbT C

TqNVV ++= φFully depleted SOI:

Low Doped thin channel

=> Lower dopant fluctuations

=> Higher VT stability vs thickness

Gate Workfunction engineering for dual gate /undoped FD channel Low VDD


2005

4

LETI: Wafer Bonding TiN gate

M. Vinet et al., SSDM2004, Sept 2004

Si substrate

ThinnedSi film

Film thinning

Buried oxide

Si substrate

ThinnedSi film

Film thinning

Buried oxide

Si substrate

LOCOS

Isolation definition

Buried oxide

Si substrate

LOCOS

Isolation definition

Buried oxide

Back gate patterningand oxide depositionSi substrate

Back gateEncapsulation oxide

Buried oxide

Back gate patterningand oxide depositionSi substrate

Back gateEncapsulation oxide

Buried oxide

Buried oxide

Si substrate

Si substrate

Initial wafer

Bondedwafer

Buried oxide

Si substrate

Si substrate

Initial wafer

Bondedwafer

Si substrateSubstrate removal

ThinnedSi film



ThinnedSi film

Si substrateTop gate patterning Si substrateTop gate patterning

Si substrateExtension

Extension implantation

Si substrateExtension Si substrateExtension

Extension implantation

Ion implantation

FD-SOI standard process

Raised source and drainIon implantation

FD-SOI standard process

Raised source and drain

Multigate MOSFET architectures : the Planar approach

STI

n+

Si substrate

SOURCE

GRILLE

DRAIN

n+

Conductionchannel

Top Gate

Bottom Gate

Raised S/D S

D

Spacers

STMicroelectronics : SON GAA Lg=25nmS.Harrison et al., SN Workshop 2004, S.Monfray et al. ,IEDM2004


2005

5INTEL: Poly gate Trigate Lg=60nm

B. Doyle et al., VLSI Tech Symp 20033 channelsTSMC: Poly gate FinFET Lg=5nm

FLYang et al., VLSI Tech Symp2004

C.Jahan et al., VLSI Tech Symp 2005,

ΩΩΩΩFET Lg=10nm TiN/HfO2 gate stack

Si

HfO2TiN

Lg = 10 nm

Si

HfO2TiN

Lg = 10 nm

Multigate MOSFET architectures : Non Planar approach


2005

6

tSi (nm)

SGWsi (nm)0

50

100

0 50 100

BOX

Si

FD-SOI

Lg ↓

vertical sidewall

non-uniformS-D doping

sub-lithographic CDFinFET

fixed WBOX

Si

WSi ≈≈≈≈ 1/2 Lg

tSi Lg

DG

/Fin

FET

tSi ≈≈≈≈ 1/4 Lg

trigate

BOX

Si

Best of both worlds?

tSi ≈≈≈≈ WSi ≈≈≈≈ Lg

Wsi

tSi

Scaling capabilities From FDSOI to DG/FinFET viaTrigate

Partly from B.Doyle et al, VLSI2003 paper 10A-2, Kyoto(Japan)

-TSi remains ≈≈≈≈ thickness SOI manufact. specs => transfer WSi control

-Design rules & layout issues (compatibility with existing design libraries): WFETmin=2*TSi+WsiWFET=n* WFETmin

=> layout factor(WFETmin /pitch)


2005

7

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

-0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2

Vg (V)

Id (µ

A/µ

m)

Lg=20nm - Vdd=1.2VIon=1250µA/µmIoff=1.3µA/µmSsw=102mV/decDIBL=220mV/V

Vd=50mV

Vd=1.2V

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

-1.2-1-0.8-0.6-0.4-0.200.2

Vg (V)

Id (µ

A/µ

m)

Lg=20nm - Vdd=-1.2VIon=630µA/µmIoff=24µA/µmSsw=270mV/decDIBL=250mV/V

Vd=-50mV

Vd=-1.2V

Lg=20nmIon=1250µA/µmIoff=1.3µA/µm

Tsi~10nm

Lg=20nmIon=630µA/µmIoff=24µA/µm

Tsi~7nm

NMOS

PMOS

M.Vinet et al., IEEE EDL, May 2005

Planar Bonded double metal gate down to Lg=10nmfor High Performance

IST NESTOR project

Lg~13nm

Lg~8nm

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

0 0.2 0.4 0.6 0.8 1 1.2

Vg (V)

Id (µ

A/µ

m)

Lg=10nm - Vdd=1.2VIon=1130µA/µmIoff=7.2µA/µm

Vd=50mV

Vd=1.2VLg=10nmIon=1130µA/µmIoff=7.2µA/µm

Tsi~6nm


2005

8

Double gate versus Single gate(FDSOI) MOSFET by Wafer Bonding(Lg=40nm)

M.Vinet et al. , SSDM 2004, Sept2004, Tokyo IST NESTOR project


2005

9

M.Vinet et al. , SSDM 2004, Sept 2004, Tokyo

Multigate devices for Multipurposes applications for Future SOC designs

Double gate MOSFET by bonding

IST NESTOR project


2005

10

-40

-20

0

20

40

60

80

100

0,01 0,1 1 10

Low

fiel

d M

obilit

y ga

in (%

)

Effective Gate Length (µm)

symbols = exp.lines=input for Id model

Strained Devices

= CESL-sSi

= sSi= sSiGe

ESL-sSi : ⊕ m* reduction ⊕ strain enhancement sSiGe : ⊕ m* reduction extra charged defects sSi : quantization effects phonon scattering not dominant

Mobility enhancement

Original & in-depth characterisation of µeff in strained devices

F.Andrieu et al. VLSI Symp, June 2005,Kyoto


2005

11

Ge versus Si4 Low field mobility higher than in silicon4 Electron and hole mobility values are

closer than in Si => Design compactness.4 Energy relaxation time > in Si=> velocity

overshoot appears for higher L than in Si. 4 Dopant Activation at lower

temperatures. High dopant diffusivity. 4 Compatibility with high-

κκκκdielectrics(necessity)4 GeOI : demonstrated feasability4 III-V (GaAs)/ Ge co-integration:

Optoelectronics, RF, power devices,…

but

4 Lower bandgap than Si. Junction leakage.4 Higher K than Si(Cj, SCE, DIBL,etc…)4 Lower thermal conductivity than Si(Self

heating,…)4 CMOS process Integration is an issue

RTB UNIMOS project


2005

12

GeOI substrates : the Smart-CutTM process

Rec

yclin

g

B

A

4- Cleaning / bonding

A

B5- Layer transfer

6- Final treatments

A1- Donor wafer (EPI Ge/Si)

A2- Oxide formation

A

H+ ions

3- Implantation

L.Clavelier et al. SNW 2005, Kyoto

RTB UNIMOS project


2005

13

STI

n+

Si substrate

SOURCE

GRILLE

DRAIN

n+

STMicroelectronics : SON GAA Lg=25nmS.Harrison et al., SN Workshop 2004, S.Monfray et al. ,IEDM2004

Silicon On Nothing(SON)

MBCFET(Multichannel)

Samsung MBCFET GAA

SYLee et al., VLSI Tech. Symp. 2004, June 2004 Honolulu(HI)

VLSI Tech. Symp. 2005, June 2005 Kyoto(Japan)

IonN=2100µA/µm IoffN=1.3µA/µm Lg=30nm

From SON to Multichannels and Multigates


2005

14

FLLiang, VLSI Tech Symposium 2004, June 2004, Honolulu(HI)

From Double gate to NanowireIncreasing electrostatic channel control

Si,sSi

Ge,sGe

CNTs


2005

15

65nm 45nm 32nm 22nm

2007 2010 2013 2016

High Performance Bulk+Strain========

====FDSOI/PDSOI +Strain=================

===========Multigate============…..======

LowPower FD/PD SOI=========

==========FDSOI+Strain========================Multigate========

Low Standby Power FDSOI===========================

========Multigate========

GeOI

Dual Nanowires

Multichannels

CNT

Devices architectures options

HiK+Metgate

HiK+Metgate

HiK+Metgate


2005

16

HP sub 32nm node(Lg=13nm ITRS)- Bulk or planar SOI, and when?

FDSOI, introduction 2007

-FinFET or tri-gate, and when?

DGMOS Multigate 2011-2013(Lg=13nm). Co-integration with planar FDSOI.

Global strain, local strain, or other techniques, and when?

Local(2005), global and dual(otherwise impact on CMOS design)

For High-performance or low-power applications?

LSTP: FDSOI, Multigate (both w HiK + Metgate )

LOP: FDSOI+Strain, Multigate(both w HiK + Metgate)

HP: FDSOI+Strain, Multigate, Multichannels (both w HiK + Metgate)

-Si nanowire, carbon nanotube FET, or other new devices, and when?

Si, Ge, sSi, sSiGe, sGe nanowires channels On Insulator@ sub 32nm already (Multigate w sub 10nm width) Dual channels and gates.

CNTransistors and interconnects sub 22nm node

2005 Nanoscale MOSFET...

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