16-bit MICROCONTROLLER MB96300 SERIES

16-bit MICROCONTROLLER

MB96300 SERIES

List of functional limitations 2009-01-19

European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse 47 63225 Langen, Germany File: DesignDifferences16FX.doc

CI-300010-E-V21-MB96300_List_of_functional_limitations.pdf

European MCU Design Centre CI-300010-E-V21

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Revision History

Version Date Remark 1.0 2006-11-08 Initial version 1.1 2006-11-22 Revised 16FXFL0016 1.2 2006-12-06 Added 16FXFL0022, 16FXFL0023 1.3 2007-01-22 Added 16FXFL0024, 16FXFL0025

Improved part number information in list of affected devices of all individual functional limitation description and list of functional limitations.

1.4 2007-02-08 Added MB96V300BRB 1.5 2007-06-06 Added 16FXFL0026 … 16FXFL0031.

Updated 16FXFL0024 to rev. 3. 1.6 2007-07-04 Changed wording in 16FXFL0030. 1.7 2007-12-03 Added 16FXFL0032, 16FXFL0033, 16FXFL0034 1.8 2007-01-18 Added 16FXFL0035, 16FXFL0036, 16FXFL0037 1.9 2008-06-27 Added 16FXFL0038, 16FXFL0039, 16FXFL0040. Added

MB96385B and moved MB96385A to list of outdated devices. 2.0 2008-11-27 Added 16FXFL0041, 16FXFL0042, 16FXFL0043, 16FXFL0044,

16FXFL0045, 16FXFL0046 Removed column “Issue” in Table 2 and Table 3.

2.1 2009-01-19 Added MB96F31x, MB96F353, MB96F355


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Table of contents

Overview .............................................................................................................................. 5 16FXFL0001: Power-on debug feature............................................................................. 15 16FXFL0002: Peripheral access during debug mode ..................................................... 18 16FXFL0003: CANbus 3 output enable register .............................................................. 21 16FXFL0004: Guarded access break after conditional branch ...................................... 24 16FXFL0005: Data value break on byte access............................................................... 27 16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources .............. 30 16FXFL0007: Bit positions in Real Time Clock register WTCKSR ................................. 33 16FXFL0008: Synchronous start of Programmable Pulse Generators.......................... 37 16FXFL0009: Embedded debug support data value break............................................. 40 16FXFL0010: Embedded debug support data write protection...................................... 43 16FXFL0011: EDSU USART Transmit Interrupt ............................................................... 46 16FXFL0012: DMA stop when CLKB > CLKP1/2 ............................................................. 49 16FXFL0013: LCD prescaler ............................................................................................. 52 16FXFL0014: CLKP2 divider setting................................................................................. 55 16FXFL0015: Wake-up by RTC from timer mode ............................................................ 58 16FXFL0016: Interrupt while MOVS/MOVSW is executing ............................................. 61 16FXFL0017: Flash read buffer after programming ........................................................ 66 16FXFL0018: NMI relocation lock..................................................................................... 69 16FXFL0019: Phantom wake-up from timer or sleep mode............................................ 72 16FXFL0020: Read value of PDR/EPSR ........................................................................... 75 16FXFL0021: Initial state of external interrupt flag ......................................................... 78 16FXFL0022: Permitted settings for the Flash configuration registers......................... 81 16FXFL0023: Usage of Flash read buffer......................................................................... 85 16FXFL0024: Side effect of disabled DMA controller channels ..................................... 88 16FXFL0025: Increased current consumption ................................................................ 92 16FXFL0026: Feature emulation....................................................................................... 95 16FXFL0027: Trace function limitation ............................................................................ 99 16FXFL0028: Stuck on SW instruction break ................................................................ 102 16FXFL0029: Limitation in using Operand break points as trace triggers.................. 105 16FXFL0030: Limitation in using Pass Count of Operand break points of DSU......... 108 16FXFL0031: Wrong instruction execution detection of DSU...................................... 111 16FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time.... 116 16FXFL0033: FLASH Reset............................................................................................. 120


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16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion .......... 124 16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3 ........................... 130 16FXFL0036: EDSU2 register not available on all devices (INT9 source selection) ... 133 16FXFL0037: Initial value of some I/O timer registers not correct ............................... 136 16FXFL0038: Watchdog detection during debugging is not correct ........................... 140 16FXFL0039: Low voltage detector threshold levels differ from datasheet specification 144 16FXFL0040: Limitation in using P13_5 and P13_7 as input........................................ 147 16FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt152 16FXFL0042: Failure of String Instructions and WBTC/WBTS Instructions................ 157 16FXFL0043: Limitations for IRQ clearing of LIN-USART and RTC ............................. 166 16FXFL0044: Limitation when using LCD segment 33 ................................................. 174 16FXFL0045: USB: STALL response release specification limitation of endpoint0 ... 180 16FXFL0046: USB: Specification of limitation on isochronous transfer ..................... 184


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OverviewFor some devices a shortcut name was used as in the table below:


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Table 1: Relation of device shortcut to product name.Device shortcut Product name

MB9638X MB96384RSA, MB96384RWA, MB96384YSA, MB96384YWA, MB96385RSA, MB96385RWA, MB96385YSA,MB96385YWA

MB9638XB MB96384RSB, MB96384RWB, MB96384YSB, MB96384YWB, MB96385RSB, MB96385RWB, MB96385YSB,MB96385YWB

MB96F32X MB96F326ASA, MB96F326AWA, MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWAMB96F32XB MB96F326ASB, MB96F326AWB, MB96F326RSB, MB96F326RWB, MB96F326YSB, MB96F326YWBMB96F33x MB96F336USA, MB96F336UWA, MB96F338RSA, MB96F338RWA, MB96F338YSA, MB96F338YWA, MB96F338USA,

MB96F338UWAMB96F348H/T MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWAMB96F348H/TB MB96F348CSB, MB96F348CWB, MB96F348HSB, MB96F348HWB, MB96F348TSB, MB96F348TWBMB96F348H/TC MB96F348CSC, MB96F348CWC, MB96F348HSC, MB96F348HWC, MB96F348TSC, MB96F348TWCMB96F34XY/R MB96F346ASA, MB96F346AWA, MB96F346RSA, MB96F346RWA, MB96F346YSA, MB96F346YWA, MB96F347ASA,

MB96F347AWA, MB96F347RSA, MB96F347RWA, MB96F347YSA, MB96F347YWA, MB96F348ASA, MB96F348AWA,MB96F348RSA, MB96F348RWA, MB96F348YSA, MB96F348YWA

MB96F34XY/RB MB96F346ASB, MB96F346AWB, MB96F346RSB, MB96F346RWB, MB96F346YSB, MB96F346YWB, MB96F347ASB,MB96F347AWB, MB96F347RSB, MB96F347RWB, MB96F347YSB, MB96F347YWB, MB96F348ASB, MB96F348AWB,MB96F348RSB, MB96F348RWB, MB96F348YSB, MB96F348YWB

MB96F35X MB96F356ASA, MB96F356AWA, MB96F356RSA, MB96F356RWA, MB96F356YSA, MB96F356YWAMB96F35XB MB96F356ASB, MB96F356AWB, MB96F356RSB, MB96F356RWB, MB96F356YSB, MB96F356YWBMB96F37X MB96F378HSA, MB96F378HWA, MB96F378TSA, MB96F378TWA, MB96F379RSA, MB96F379RWA, MB96F379YSA,

MB96F379YWAMB96F38(8/9) MB96F388HSA, MB96F388HWA, MB96F388TSA, MB96F388TWA, MB96F389RSA, MB96F389RWA, MB96F389YSA,

MB96F389YWAMB96F3(8/9)5 MB96F385RSA, MB96F385RWA, MB96F385YSA, MB96F385YWA, MB96F395RSA, MB96F395RWA, MB96F395YSA,

MB96F395YWAMB96F38X MB96F386RSA, MB96F386RWA, MB96F386YSA, MB96F386YWA, MB96F387RSA, MB96F387RWA, MB96F387YSA,

MB96F387YWAMB96F38XB MB96F386RSB, MB96F386RWB, MB96F386YSB, MB96F386YWB, MB96F387RSB, MB96F387RWB, MB96F387YSB,

MB96F387YWB


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Device shortcut Product nameMB9634(5/6) MB96345RSA, MB96345RWA, MB96345YSA, MB96345YWA, MB96346RSA, MB96346RWA, MB96346YSA,

MB96346YWAMB96F918 MB96F918TSA, MB96F918HSA, MB96F918TWA, MB96F918HWAMB96F3(1/5)5 MB96F313RSA, MB96F313RWA, MB96F313YSA, MB96F313YWA, MB96F315RSA, MB96F315RWA, MB96F315YSA,

MB96F315YWA, MB96F353RSA, MB96F353RSA, MB96F353RWA, MB96F353RWA, MB96F353YSA, MB96F353YSA,MB96F353YWA, MB96F353YWA, MB96F355RSA, MB96F355RSA, MB96F355RWA, MB96F355RWA, MB96F355YSA,MB96F355YSA, MB96F355YWA, MB96F355YWA

MB96F3(1/5)x MB96F313RSA, MB96F313RWA, MB96F313YSA, MB96F313YWA, MB96F315RSA, MB96F315RWA, MB96F315YSA,MB96F315YWA, MB96F353RSA, MB96F353RSA, MB96F353RWA, MB96F353RWA, MB96F353YSA, MB96F353YSA,MB96F353YWA, MB96F353YWA, MB96F355RSA, MB96F355RSA, MB96F355RWA, MB96F355RWA, MB96F355YSA,MB96F355YSA, MB96F355YWA, MB96F355YWA

An overview of the functional limitation and the list of affected devices is given below. This table is showing most recent devices only, which arerecommended for new designs. For the list of functional limitations for outdated devices, please refer to Table 3.


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Table 2: List of functional limitations and affected devices (most recent devices recommended for new designs).

Functional limitation Page

MB

96V3

00B

RB

MB

96F3

(1/5

)5

MB

96F3

(1/5

)x

MB

96F3

2XB

MB

96F3

3x

MB

96F3

48H

/TC

MB

96F3

4XY/

RB

MB

96F3

5XB

MB

96F3

7X

MB

96F3

8(8/

9)

MB

96F3

(8/9

)5

MB

96F3

8XB

MB

96F3

8(6/

7/8/

9)

MB

9634

(5/6

)

MB

9638

XB

MB

96F9

18

16FXFL0024: Side effect of disabled DMA controllerchannels

88 ● ● ●

16FXFL0032: Divider Change of CLKP2/CLKP3 andChange of Stabilization Time

116 ● ● ● ●

16FXFL0033: FLASH Reset 120 ● ● ● ●

16FXFL0034: Watchdog intervals and delay on thewatchdog reset assertion

124 ● ● ● ● ● ● ●

16FXFL0035: Limitation when using LCD with dutycycle 1/2 or 1/3

130 ●

16FXFL0036: EDSU2 register not available on alldevices (INT9 source selection)

133 ● ● ●

16FXFL0037: Initial value of some I/O timer registers 136 ● ● ● ● ● ● ●

16FXFL0038: Watchdog detection during debugging isnot correct

140 ● ● ● ● ● ● ●

16FXFL0039: Low voltage detector threshold levelsdiffer from datasheet specification

144 ●

16FXFL0040: Limitation in using P13_5 and P13_7 asinput

147 ● ● ● ● ●


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MB

96V3

00B

RB

MB

96F3

(1/5

)5

MB

96F3

(1/5

)x

MB

96F3

2XB

MB

96F3

3x

MB

96F3

48H

/TC

MB

96F3

4XY/

RB

MB

96F3

5XB

MB

96F3

7X

MB

96F3

8(8/

9)

MB

96F3

(8/9

)5

MB

96F3

8XB

MB

96F3

8(6/

7/8/

9)

MB

9634

(5/6

)

MB

9638

XB

MB

96F9

18

16FXFL0041: Wrong execution of scan stringinstruction SCEQ/SCWEQ at Interrupt

152 ● ● ● ● ● ● ● ● ● ● ● ● ● ●

16FXFL0042: Failure of String Instructions andWBTC/WBTS Instructions

157 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●

16FXFL0043: Limitations for IRQ clearing of LIN-USART and RTC

166 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●

16FXFL0044: Limitation when using LCD segment 33 174 ● ● ● ● ● ● ●

16FXFL0045: USB: STALL response releasespecification limitation of endpoint01)

180 ●

16FXFL0046: USB: Specification of limitation onisochronous transfer1)

184 ●

1) Only valid for devices with USB controller

The following table shows the functional limitations of outdated devices. It is not recommended to start new designs with these devices.


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Table 3: List of functional limitations and affected outdated devices (not recommended for new designs)


MB

96V3

00R

B

MB

96F3

2X

MB

96F3

48H

/T

MB

96F3

48H

/TB

MB

96F3

4XY/

R

MB

96F3

5X

MB

9638

X

MB

96F3

8(6/

7/8/

9)

16FXFL0001: Power-on debug feature 15 ●16FXFL0002: Peripheral access during debug mode 18 ●16FXFL0003: CANbus 3 output enable register 21 ●16FXFL0004: Guarded access break after conditional branch 24 ●16FXFL0005: Data value break on byte access 27 ●16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources 30 ●16FXFL0007: Bit positions in Real Time Clock register WTCKSR 33 ●16FXFL0008: Synchronous start of Programmable Pulse Generators 37 ●16FXFL0009: Embedded debug support data value break 40 ●16FXFL0010: Embedded debug support data write protection 43 ●16FXFL0011: EDSU USART Transmit Interrupt 46 ●16FXFL0012: DMA stop when CLKB > CLKP1/2 49 ●16FXFL0013: LCD prescaler 52 ●16FXFL0014: CLKP2 divider setting 55 ●16FXFL0015: Wake-up by RTC from timer mode 58 ●16FXFL0016: Interrupt while MOVS/MOVSW is executing 61 ● ●16FXFL0017: Flash read buffer after programming 66 ●16FXFL0018: NMI relocation lock 69 ● ●16FXFL0019: Phantom wake-up from timer or sleep mode 72 ● ●16FXFL0020: Read value of PDR/EPSR 75 ● ●16FXFL0021: Initial state of external interrupt flag 78 ● ●16FXFL0022: Permitted settings for the Flash configuration registers 81 ●16FXFL0023: Usage of Flash read buffer 85 ●16FXFL0024: Side effect of disabled DMA controller channels 88 ● ● ● ●


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MB

96V3

00R

B

MB

96F3

2X

MB

96F3

48H

/T

MB

96F3

48H

/TB

MB

96F3

4XY/

R

MB

96F3

5X

MB

9638

X

MB

96F3

8(6/

7/8/

9)

16FXFL0025: Increased current consumption 92 ●16FXFL0026: Feature emulation 95 ●16FXFL0027: Trace function limitation 99 ●16FXFL0028: Stuck on SW instruction break 102 ●16FXFL0029: Limitation in using Operand break points as trace triggers 105 ●16FXFL0030: Limitation in using Pass Count of Operand break points of DSU 108 ●16FXFL0031: Wrong instruction execution detection of DSU 111 ●16FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time 116 ● ● ●16FXFL0033: FLASH Reset 120 ● ● ● ● ● ●16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion 124 ● ● ● ● ● ● ●16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3 130 ● ●16FXFL0036: EDSU2 register not available on all devices (INT9 source selection) 133 ● ● ● ●16FXFL0037: Initial value of some I/O timer registers 136 ● ● ● ● ● ●16FXFL0038: Watchdog detection during debugging is not correct 140 ● ● ● ● ● ●16FXFL0039: Low voltage detector threshold levels differ from datasheet specification 144 ● ● ● ●16FXFL0040: Limitation in using P13_5 and P13_7 as input 147 ● ● ●16FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt 152 ● ● ● ● ● ● ● ●16FXFL0042: Failure of String Instructions and WBTC/WBTS Instructions 157 ● ● ● ● ● ● ● ●16FXFL0043: Limitations for IRQ clearing of LIN-USART and RTC 166 ● ● ● ● ● ● ● ●16FXFL0044: Limitation when using LCD segment 33 174 ● ● ●

FUJITSU SEMICONDUCTOR

Power-on debug feature

16FX functional limitation 16FXFL0001

European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse 47 63225 Langen, Germany

European MCU Design Centre 16FXFL0001 ver. 2

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Revision History

Version Date Remark 1 2006-10-30 Initial version 2 2007-01-19 Improved part number information in list of affected devices


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16FXFL0001: Power-on debug feature

1. Description of functional limitation The Power-on debug feature is not available.

2. List of affected Devices MB96V300RB

3. Detailed explanation The Power-on debug feature enables debugging the application right after powering up. This is implemented by separating the power supply for the application part and the debug support logic part of 16FX EVA chips.

This feature is not available on the affected devices.

4. Possible workaround None.

5. Fujitsu countermeasure Future 16FX EVA chips will support the Power-on debug feature.


Peripheral access during debug mode




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Revision History



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16FXFL0002: Peripheral access during debug mode

1. Description of functional limitation When the EVA chip is in debug mode and the feature is used to stop the peripheral clocks CLKP1/CLKP2 while being in debug mode, any read/write access to peripherals in clock domain CLKP1 or CLKP2 will freeze the MCU.


3. Detailed explanation 16FX EVA chips offer the feature to stop peripheral clocks CLKP1 and CLKP2 while being in debug mode. This feature prevents that for example timers continue counting while the application is stopped by the user for inspection. If the counters would continue operation, they may overflow and the application would have to handle according interrupts directly after leaving the debug mode.

However, since CLKP1 and CLKP2 are stopped when this feature is chosen, the debug system freezes when the user tries to read or write to registers in the CLKP1 or CLKP2 domain.

4. Possible workaround Memory content can be read or written as long as no registers in CLKP1 or CLKP2 domain are referenced. Avoid reading/writing to registers in CLKP1 and CLKP2 domain while in debug mode.

5. Fujitsu countermeasure Future 16FX EVA chips will enable to read register contents in CLKP1 and CLKP2 domain while being in debug mode, even when CLKP1 and CLKP2 are stopped. Write access to registers in CLKP1 or CLKP2 domain will be ignored.


CANbus 3 output enable register




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Revision History



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16FXFL0003: CANbus 3 output enable register

1. Description of functional limitation CANbus channel 3 Output Enable Register COER3 has different offset than at other CANbus channels. It is 0xABE. It should be 0xACE.


3. Detailed explanation The register layout of all CANbus controllers is the same, so that drivers can make use of a base address for each CANbus and constant offsets to address each register of the CANbus controller with the given base address.

However, CANbus controller 3 has register COER3 on another offset than the other CANbus controllers.

4. Possible workaround Do not use CAN base address and register offset scheme, but individual register addresses as defined in 16FX C-header file.

5. Fujitsu countermeasure Future 16FX chips having CANbus controller channel 3 will have COER3 at address 0xACE.


Guarded access break after conditional branch




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Revision History



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16FXFL0004: Guarded access break after conditional branch

1. Description of functional limitation Debug Support: If a guarded access area is defined directly behind a conditional branch instruction, the guarded access break is activated even when the conditional branch is taken.


3. Detailed explanation See above.


5. Fujitsu countermeasure Future 16FX EVA chips will not have this limitation.


Data value break on byte access




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Revision History



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16FXFL0005: Data value break on byte access

1. Description of functional limitation Debug Support: Data value break on byte access can not be used.


3. Detailed explanation Data value break on byte access can not be used. The byte on the other byte lane is not masked correctly (only lower bit is masked, not complete byte).

Operand break (w/o data value break feature) is working without restriction on byte size and word size operands.

4. Possible workaround None. Do not use data value break on byte size. Use only data value break on words.

5. Fujitsu countermeasure Future 16FX EVA chips will not have this limitation.


Wake-up from sleep mode by CLKP2 clock domain resources




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Revision History



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16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources

1. Description of functional limitation Resources in CLKP2 domain (like CANbus, Sound Generator) can not wake-up the device from sleep mode.


3. Detailed explanation

4. Possible workaround All CANbus RX pins also have an external interrupt. External interrupts are located in the CLKP1 domain, which is not affected. Hence, for wake-up by CANbus, it is possible to use the external interrupt on the RX pin to wake-up the MCU from any low power mode. However, the wake-up event will always occur when the external interrupt detects a sensitive event on the RX/INT

5. Fujitsu countermeasure Future 16FX chips will not have this limitation.


Bit positions in Real Time Clock register WTCKSR




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Revision History



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16FXFL0007: Bit positions in Real Time Clock register WTCKSR

1. Description of functional limitation RTC: bit position for write access of register WTCKSR:[CKSEL1:CKSEL0] should be bit [9:8], but is [1:0].


3. Detailed explanation 7 6 5 4 3 2 1 0 - - - - - - INTE4 INT4 WTCER

- - - - - - R/W R/W Initial value X X X X X X 0 0

15 14 13 12 11 10 9 8 - - - - - - CKSEL1 CKSEL0 WTCKSR- - - - - - R/W R/W

Initial value X X X X X X 0 0

Registers WTCER and WTCKSR are located at the lower and upper byte of a 16-bit word.

At 16-bit read access, WTCER:INT4 and WTCER:INTE4 are located at bits 1 and 0, and bits WTCKSR:CKSEL1 and WTCKSR:CKSEL0 are located at bit 9 and 8, respectively.

However, at 16-bit write access, WTCER:INT4 and WTCER:INTE4 are located at bits 1 and 0, but bits WTCKSR:CKSEL1 and WTCKSR:CKSEL0 are also located at bit 1 and 0, respectively.

Hence,

1. when writing a 16-bit word to {WTCKSR, WTCER} the value on bit position 1 and 0 is written into WTCER:INTE4 and WTCER:INT4, and also into WTCKSR:CKSEL1 and WTCKSR:CKSEL0.

2. when writing a 8-bit word to WTCER the value on bit position 1 and 0 of WTCER is also written into WTCKSR:CKSEL1 and WTCKSR:CKSEL0.

Read access to these register is not affected.


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4. Possible workaround Do not use byte access to write the content of WTCER, because it will overwrite former content of WTCKSR:CKSEL1 and WTCKSR:CKSEL0.

To set the content of {WTCKSR, WTCER} to the binary value XXXX.XXab.XXXX.XXcd, use the following procedure:

Step Content of WTCKSR:INTE4, INT4

Content of WTCER:CKSEL1,CKSEL0

1. Make sure the RTC interrupt is disabled as by initial value of the Interrupt Control Register ICR for the interrupt vector of the RTC.

Initial value Initial value

2. Write the content of {WTCKSR, WTCER} by 16-bit access, value = XXXX.XXab.XXXX.XXcd

c, d c, d

3. Write the content of WTCKSR by 8-bit access, value = XXXX.XXab a, b c, d

4. Continue as usual, i. e. enable interrupts etc.



Synchronous start of Programmable Pulse Generators




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Revision History



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16FXFL0008: Synchronous start of Programmable Pulse Generators

1. Description of functional limitation For the Programmable Pulse Generators, the synchronous start of multiple channels by external trigger is not ensured. There may be a difference in start time by one CLKP1 cycle.






Embedded debug support data value break




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Revision History



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16FXFL0009: Embedded debug support data value break

1. Description of functional limitation The Embedded Debug Support which can be built with the memory patch function, features a data value break. The data value break can generate phantom breaks.


3. Detailed explanation When using the data value break of the Embedded Debug Support implemented by the Memory Patch function, a break condition can be generated though the condition was not met.

4. Possible workaround None. Do not use data value break function in the embedded debug support of the memory patch unit or check in the interrupt handler, that the data value has matched.



Embedded debug support data write protection




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Revision History



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16FXFL0010: Embedded debug support data write protection

1. Description of functional limitation The memory patch unit’s embedded debug support does not feature data write protection.


3. Detailed explanation The data patch function allows superseding the values read from a memory location by a value stored in the memory patch function. This is implemented by redirecting read accesses to the memory patch function. The memory location to be patched is not selected.

However, write accesses to the memory location are not redirected.

4. Possible workaround None

5. Fujitsu countermeasure Future 16FX chips feature also write access redirection to the memory patch function. By this, it is possible to implement a write protection.


EDSU USART Transmit Interrupt




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Revision History



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16FXFL0011: EDSU USART Transmit Interrupt

1. Description of functional limitation The register EDSU does not allow to map the transmit interrupt of the USART, which is selected by EDSU:SEL1, EDSU:SEL0, to the INT9 interrupt. However, performance of a debug system can be increased by offering the possibility to map the selected USART’s transmit interrupt to the INT9 interrupt.




5. Fujitsu countermeasure Future 16FX chips’ EDSU register feature the bits EDSU:TIE and EDSU:TINT to map the selected USART’s transmit interrupt to the INT9 interrupt.


DMA stop when CLKB > CLKP1/2




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Revision History



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16FXFL0012: DMA stop when CLKB > CLKP1/2

1. Description of functional limitation DMA may stop after data transfer has completed when CLKB > CLKP. After this, no more DMA transfers can be done.



4. Possible workaround None. Do not use DMA on CLKP1 domain devices, when CLKB > CLKP1. Do not use DMA on CLKP2 domain devices, when CLKB > CLKP2.

5. Fujitsu countermeasure Future 16FX MCUs will be fixed to allow usage of DMA when CLKB > CLKP1 and CLKB > CLKP2..


LCD prescaler




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Revision History



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16FXFL0013: LCD prescaler

1. Description of functional limitation The LCD prescaler values do not allow operation of LCD w/ sub-clock/RC clock within frequency limits (frame rate < 90Hz).




5. Fujitsu countermeasure Future 16FX MCUs will offer different prescaler seetings in the LCR register.

Old setting of LCR:FP1,FP0:

FP1 FP0 When peripheral clock CLKP1 is selected

When sub clk CLKSC or RC clock CLKRC is selected

0 0 FCLKP1/(213 X N) FCLKP1/(23 X N) 0 1 FCLKP1/(214 X N) FCLKP1/(24 X N) 1 0 FCLKP1/(215 X N) FCLKP1/(25 X N) 1 1 FCLKP1/(216 X N) FCLKP1/(26 X N)

New setting of LCR:FP1,FP0:

FP1 FP0 When peripheral clock CLKP1 is selected

When sub clk CLKSC or RC clock CLKRC is selected

0 0 FCLKP1/(213 X N) FCLKP1/(28 X N) 0 1 FCLKP1/(215 X N) FCLKP1/(29 X N) 1 0 FCLKP1/(217 X N) FCLKP1/(210 X N) 1 1 FCLKP1/(219 X N) FCLKP1/(211 X N)


CLKP2 divider setting




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16FXFL0014: CLKP2 divider setting

1. Description of functional limitation CLKP2 divider setting as defined by CKFCR:PC2D[3:0] = ‘0001’ can only be used for frequency of:

• CLKS2 <= 26MHz (1.8V core voltage)

• CLKS2 <= 28MHz (1.9V core voltage)

2. List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA


4. Possible workaround For CLKS2 <= 26/28MHz there is no restriction on the setting of CKFCR:PC2D[3:0].

For CLKS2 > 26/28MHz, use other settings for CLKP2, like 1:3, 1:4, …

5. Fujitsu countermeasure Future 16FX MCUs will not have this limitation.


Wake-up by RTC from timer mode




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16FXFL0015: Wake-up by RTC from timer mode

1. Description of functional limitation The real-time clock can not wake-up the MCU from timer mode




5. Fujitsu countermeasure Future 16FX MCUs will not have this limitation.


Interrupt while MOVS/MOVSW is executing




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Revision History

Version Date Remark 1 2006-11-03 Initial version 2 2006-11-14 Improved description, added workarounds, added that Fujitsu will

offer modified Assembler that enables workaround by command-line switch -@movs_16FX

3 2006-11-22 Added list of affected library functions 4 2007-01-19 Improved part number information in list of affected devices


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16FXFL0016: Interrupt while MOVS/MOVSW is executing

1. Description of functional limitation When MOVSI, MOVSD, MOVSIW or MOVSDW instruction is executed and the source start address is an odd address (address not dividable by 2) and an interrupt is accepted by the CPU, then the fetched interrupt vector is invalid and the application crashes.


3. Detailed explanation When MOVSI, MOVSD, MOVSIW or MOVSDW instruction is executed and the source start address is an odd address (address not dividable by 2) and an interrupt is accepted by the CPU, then the fetched interrupt vector is invalid and the application crashes.

When memory model “small” or “medium” (Data address space 16bit), the instructions MOVSI, MOVSD, MOVSIW or MOVSDW are used by the Softune C-compiler for the following C-language constructs:

C-language construct Example • Passing an argument of type struct or

union to a function

• The object which is passed as argument must start at an odd address

typedef struct { int len; char buf[20]; } my_type; void procedure_a(my_type); my_type my_struct; procedure_a(my_struct); // Problem, if my_struct has odd address

• Passing a return value of a function of type struct or union or double.

typedef struct { int len; char buf[20]; } my_type; my_type my_struct; my_type procedure_b(void); my_struct = procedure_b(); // Problem, if return value of procedure_b // is on odd address.

• Initializing a local variable of type struct or union

struct { int len; char buf[20] } my_struct = { 6, “Hello!” }; // Problem, if my_struct is on odd address.

• Copy variables of type struct or union or double

struct { int len; char buf[20] } my_struct_a, my_struct_b; my_struct_a = my_struct_b;


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C-language construct Example // Problem, if my_struct_b is on odd address

• Passing an argument to a function which is the return value of a previous function call of type double

double fabs(double); double sin(double); double x; …x = fabs(sin(x));

• Sign inversion of a variable of type double

double x, y; y = -x; // Problem if x is on odd address.

The following table lists the library functions that are using the MOVSI, MOVSD, MOVSIW or MOVSDW instruction in certain memory models:

Memory model Library function name LARGE COMPACT SMALL MEDIUM

acos yes yes yes yes asin yes yes yes yes atan yes yes yes yes atan2 yes yes yes yes div yes yes yes yes ldiv yes yes yes yes log yes yes yes yes log10 yes yes yes yes pow yes yes yes yes tan yes yes yes yes atof yes yes ceil yes yes cos yes yes cosh yes yes exp yes yes floor yes yes fmod yes yes fprintf yes yes fscanf yes yes modf yes yes printf yes yes scanf yes yes sin yes yes sinh yes yes sprintf yes yes sscanf yes yes strtod yes yes tanh yes yes vfprintf yes yes vprintf yes yes vsprintf yes yes


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4. Possible workaround Workarounds rely on exclusion of one of the three conditions of this limitation. Hence:

3. Avoid using MOVSI, MOVSD, MOVSIW or MOVSDW instruction. You can do by avoiding using above mentioned C-language constructs. Or you can only use memory model “Large” or “Compact”.

4. Avoid odd addresses for variables of type struct, union or double. When MOVSI, MOVSD, MOVSIW or MOVSDW is used with variables on even addresses, there is no limitation.

5. Avoid accepting interrupts while MOVSI, MOVSD, MOVSIW or MOVSDW is executing. This can be performed by the following modification of the assembly language code, which disables interrupts before executing MOVSI and re-enables it after MOVSI finishes:

Original code Modified code

MOVSI DTB, ADB

PUSHW PS AND CCR, #0x0BF MOVSI DTB, ADB POPW PS

5. Fujitsu countermeasure 1. By November 30, 2006, Fujitsu will offer a modified version of 16LX/16FX Assembler

tool.

The new Assembler tool will have two new command line switches:

Switch Call example Effect -@movs_16FX fasm907s -cpu MB96V300RB -@movs_16FX Special code will be generated in which

interrupts are disabled during execution of MOVSI, MOVSD, MOVSIW or MOVSDW Ignore -@movs_16FX option (default behavior)

2. By November 30, 2006, Fujitsu will offer a library compiled with the modified Assembler tool with the command line switch to apply the workaround activated.

3. Future MCUs will not have this limitation.


Flash read buffer after programming




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Revision History



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16FXFL0017: Flash read buffer after programming

1. Description of functional limitation During programming the Flash, the Flash Code and Data read buffer content becomes invalid.

2. List of affected Devices MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA


4. Possible workaround Before programming, disable Flash read buffers by programming MFMCS:CRBE, DRBE, SFMCS:CRBE, DRBE.

5. Fujitsu countermeasure Future MCUs will not have this limitation.


NMI relocation bit lock




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16FXFL0018: NMI relocation lock

1. Description of functional limitation Even when NMI is enabled, it is possible to relocate the NMI function to the NMI_R pin or vice versa by changing the value of PRRR7:NMI_R. By this, the NMI function can be deactivated or issued, depending on the state of the NMI and NMI_R pins.




5. Fujitsu countermeasure Future MCUs will not have this limitation. The bit PRRR7:NMI_R is locked when the NMI function is enabled.


Phantom wake-up from timer- or sleep mode




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16FXFL0019: Phantom wake-up from timer or sleep mode

1. Description of functional limitation A phantom wake-up from timer mode or sleep mode can be generated.



4. Possible workaround After wake-up, application should check for wake-up cause and return to sleep/timer mode if no wake-up cause was found.



Read value of PDR/EPSR




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16FXFL0020: Read value of PDR/EPSR

1. Description of functional limitation When the general purpose ports’ PDR/EPSR are read, the read value is not the value at the time, the read is executed, but the value at the last time of a read or write access to any resource of clock domain CLKP1.



4. Possible workaround Read the PDR/EPSR register twice and use last value.



Initial state of external interrupt flag




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16FXFL0021: Initial state of external interrupt flag

1. Description of functional limitation The initial state of the external interrupt flags EIRRn:ER[7:0] have initial value ‘1’ instead of required value ‘0’.



4. Possible workaround Do not rely on initial value of EIRR.



Permitted settings for the Flash configuration registers




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Revision History

Version Date Remark 1 2006-11-28 Initial version 2 2006-12-06 Revised header, 16FXFL number, formatting of tables 3 2007-01-19 Improved part number information in list of affected devices


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16FXFL0022: Permitted settings for the Flash configuration registers

1. Description of functional limitation Not all settings of the Flash configuration registers described in the Hardware Manual are allowed. In certain cases this leads to a higher number of wait cycles.


3. Detailed explanation Not all features of the Flash interface are supported by the affected devices. Hence some of the recommended settings in the HWM do not apply for these devices. Instead the Flash interface must be configured as described in the next chapter.

4. Possible workaround • The MFMTC0:ADS and SFMTC0:ADS bits must always be set to ‘1’.

• The MFMTC0:CLKBW and SFMTC0:CLKBW bits must always be set to ‘1’.

• If the CLKB frequency is lower than the CLKS1 frequency (CLKB divider setting CKFRC:BCD not “0000”), disable the code and data read buffer (Set MFMCS:DRBE, CRBE and SFMCS:DRBE,CRBE to ‘0’).

Recommended settings for Synchronous reading: Max CLKS1 frequency

CKFCR:BCD setting

FMTC setting (number of Wait States)

Code/data read buffer

Div1 Enabled or disabled 25MHz

Div2 – Div16 0239h (1WS)

Disabled

Div1 Enabled or disabled

Div2 223Ah (2WS)

Disabled 50MHz

Div3 – Div16 2239h (1WS) Disabled

Div1 4B3B (3WS) Enabled or disabled

Div2, Div3 4B3A (2WS) Disabled 56MHz Div4 – Div16 4B39 (1WS) Disabled


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Recommended settings for Synchronous reading and writing: Max CLKS1 frequency

CKFCR:BCD setting




Div2 – Div16 223Ah (2WS)

Disabled


Div2 – Div16 4B3D (5WS)

Disabled

Recommended settings for Asynchronous reading/writing: Max CLKS1 frequency

CKFCR:BCD setting




Div2 – Div16 0231h (1WS)

Disabled



Usage of Flash Read buffer




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Revision History

Version Date Remark 1 2006-11-28 Initial version 2 2006-12-06 Revised header 3 2007-01-19 Improved part number information in list of affected devices


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16FXFL0023: Usage of Flash read buffer

1. Description of functional limitation The Flash read buffer cannot be used in all operation modes.


3. Detailed explanation The Flash read buffer cannot be used in the following two cases:

• A divided CLKB clock is used (CLKS1 frequency higher than CLKB frequency)

• During Flash programming and erasing

In both cases, invalid data could be read from the Flash.

4. Possible workaround • Usage of a divided CLKB clock: Disable all read buffer by setting MFMCS:DRBE,

CRBE and SFMCS:DRBE,CRBE to ‘0’ before writing to the CKFCR:BCD bits.

• Flash programming and erasing: Disable all read buffer by setting MFMCS:DRBE, CRBE and SFMCS:DRBE,CRBE to ‘0’ before submitting the program/erase command. The read buffer can be enabled again after termination of the program/erase algorithm.



Side effect of disabled DMA controller channels




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Revision History

Version Date Remark 1 2007-01-14 Initial version 2 2007-01-19 Improved part number information in list of affected devices 3 2007-06-06 Extended list of affected devices: MB96F348HSA,

MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA (as already in chapter “Overview”).

4 2008-01-10 Extended list of devices: B versions of MB9634x and MB9638x.


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16FXFL0024: Side effect of disabled DMA controller channels

1. Description of functional limitation A DMA controller channel that is not enabled can affect the operation of a DMA controller channel that is enabled, when the content of the DISEL register of both channels is the same.

2. List of affected Devices MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HWA, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348TSA, MB96F348TWA, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB, MB96V300RB-ES

3. Detailed explanation A DMA controller channel x that is not enabled (DER:ENx = 0), for which the content of the DISEL register is the same as the content of the DISEL register of a DMA controller channel y, that is enabled (DER:ENy = 1), can affect the operation of the DMA controller channel y.

The effect is that if DMA controller channel y is receives an interrupt, it performs the data transfer correctly, but the interrupt is not filtered correctly. Instead of the interrupt being filtered as long as the Data Count register (DCT) is not 0, the interrupt is forwarded to the CPU. Hence, the DMA interrupt service routine is called at each data transfer and not only after the DMA has completed the transfer.

4. Possible workaround DISEL registers of DMA controller channels which are not intended to be used must be initialized to a value that is not used by DMA controller channels which are used.

For example, all DISEL registers are initialized to a value that is never used by DMA, e. g. 12 (= delayed interrupt).

Please take care not to overwrite the value of the DISEL register of disabled DMA channels later in the application.


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5. Fujitsu countermeasure Type A: First countermeasure is to initialize DISEL registers at reset to a value that is never used by DMA controller channels (12 = delayed interrupt). For products of this type, please take care that the software does not override the content of the DISEL register of disabled DMA channels to a value that is used by enabled DMA channels.

Type B: Second workaround is to remove the functional limitation. For these products, even when DISEL register content of a disabled channel x is the same as DISEL register content of enabled channel y, operation of channel y is not affected. Nevertheless, the content of all DISEL registers is reset to 12 at reset.

The following table gives an overview of the status of different products.

Product Functional limitation present

Countermeasure type

MB96V300RB MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA,

Yes No countermeasure, please use software workaround

MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB

Yes Type A. Please take care not to override DISEL register of disabled channels to a value used in enabled channels.

All other 16FX devices No Type B


Increased current consumption




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16FXFL0025: Increased current consumption

1. Description of functional limitation Some devices have increased current consumption.

2. List of affected Devices MB96F348HSA, MB96F348TWA, MB96F348HWA, MB96F348CWA, MB96F348CSA

3. Detailed explanation Some devices have increased current consumption as shown in the table below.

Device Approximate additional current consumption UnitMB96F348HSA 140 µAMB96F348TWA 140 µAMB96F348HWA 280 µA

4. Possible workaround There is no workaround available.

5. Fujitsu countermeasure Future MCUs will not have this increased current consumption.


Feature emulation




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Revision History

Version Date Remark 1 2007-02-16 Initial version 2 2007-04-17 Added WOT for MB96340, MB96320, MB96350 series 3 2007-07-18 Added relocation for ICU 2, 3, 4, 5


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16FXFL0026: Feature emulation

1. Description of functional limitation Some features of MB96300 series devices are not supported by the EVA chip.

2. List of affected Devices MB96V300RB-ES

3. Detailed explanation The following features of MB96300 series devices are not supported by the affected device

Feature Register Pin function

USART 7 PRRR8:SIN7_R, PRRR8:SOT7_R, PRRR8:SCK7_R USART 8 PRRR8:SIN8_R, PRRR8:SOT8_R, PRRR8:SCK8_R USART 9 PRRR8:SIN9_R, PRRR8:SOT9_R, PRRR9:SCK9_R Clock Output Function channel 0

PRRR9:CKOT0_R

Output Compare Unit 10 PRRR9:OUT10_R Free Running Timer 2 PRRR9:FRCK_2 Sound Generator 1 PRRR9:SGA1_R, PRRR9:SGO1_R Input Capture Unit 2, 3, 4, 5

PRRR4:IN2_R, PRRR4:IN3_R, PRRR4:IN4_R, PRRR:IN5_R

Programmable Pulse Generator 8

PRRR10:PPG8_R, PRRR10:TTG8_R















External bus chip selects 0, 1, 2, 4, 5

PRRR12:CS0_R, PRRR12:CS1_R, PRRR12:CS2_R, PRRR12:CS4_R, PRRR12:CS5_R

WOT output of Real time clock

WTCR:OE (bit available, but no function if a device of series MB96340, MB96320 or MB96350 is emulated)

WOT


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4. Possible workaround No workaround is possible.

5. Fujitsu countermeasure Future EVA chips will not have this limitation. MB96V300RB-ES will be updated by MB96V300BRB-ES.


Trace function limitation




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Revision History

Version Date Remark 1 2007-04-04 Initial version


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16FXFL0027: Trace function limitation

1. Description of functional limitation Reading trace data of the MB2198 and MB96V300 based debug system does not work correctly at certain conditions.


3. Detailed explanation Under certain conditions it is not possible to read out the trace data. The probability of the problem depends on the number of trace events which occur at a break. The Trace RAW shows the address 0x000000 for each trace frame. The shown instructions are meaningless. Because the other Trace views are deduced from the RAW data, these show also invalid data.

The trace data are nevertheless recorded correctly in the Trace memory.

4. Possible workaround When the Trace shows this symptom, manually perform a Single Step. This results in correct reading of the Trace buffer and hence correct display of the trace.

5. Fujitsu countermeasure The limitation will be corrected on MB96V300BRB-ES.


Stuck on SW instruction break




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16FXFL0028: Stuck on SW instruction break

1. Description of functional limitation Software instruction break can not be used together with interrupts.


3. Detailed explanation • If interrupts are occurring together with using SW instruction breaks, it could cause wrong

behaviour of the MCU:

• (1) A wrong branch address to the IRQ handler could happen at simultaneous occurrence of decoding INTE instruction (SW break entry) and an IRQ event. The debugger application will loose connection to the MCU.

• (2) The application seems to stuck at the break point if an IRQ is already occurred during staying in a break point. Pressing the continue button to leave the break point seems to have no effect (except handling the IRQ).

4. Possible workaround Use hardware instruction break instead.

5. Fujitsu countermeasure The limitation will be fixed on MB96V300BRB.


Limitation in using Operand break points as trace trigger




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16FXFL0029: Limitation in using Operand break points as trace triggers

1. Description of functional limitation Operand break point 1, 2 and 3 cannot be used as trace triggers.


3. Detailed explanation Some break channels of the 16FX-DSU can be used to start and stop tracing (Trace trigger). Instruction break channel 0 to 3 and Operand break channel 0 to 3 are intended for use as Trace trigger.

On the affected device, Trace trigger functionality of Operand break channel 1 to 3 is not available.

4. Possible workaround No workaround available.

5. Fujitsu countermeasure The limitation will be fixed on MB96V300BRB-ES.


Limitation in using Pass Count of Operand break points of DSU




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Revision History

Version Date Remark 1 2007-04-19 Initial version 2 2007-07-04 Changed wording (Pass count instead of Detection Counter)


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16FXFL0030: Limitation in using Pass Count of Operand break points of DSU

1. Description of functional limitation The pass counter of the Operand break points 0 to 3 can detect one operand access as multiple accesses and assert a break, sequencer change or trace trigger (depends on the configuration) before the actual number of accesses occurred.


3. Detailed explanation For all four operand break points of the 16FX-DSU a pass count can be used. In the pass counter the number of detection events for the corresponding operand break point can be configured. The counter is decremented at every detection event. When the counter has elapsed the configured function will be triggered (e.g. Break, sequencer change, trace trigger).

On MB96V300RB-ES the counter may detect a single break event as multiple events and trigger the configured function too early. This misbehaviour depends on the ongoing bus transfers.




Wrong instruction execution detection of DSU




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16FXFL0031: Wrong instruction execution detection of DSU

1. Description of functional limitation Some features of the DSU do not detect the instruction execution correctly.

Trace start/stop event detection

If a trace start/stop event is set at an instruction after a conditional branch instruction and the branch is taken, the event occurs accidentally even if the instruction is not executed.

The trace status changes to ‘enabled’ or ‘disable’ depending on the configuration of the Trace event. A ‘Trace trigger’ frame is recorded to the Trace memory.

Example:label: INSTR1 INSTR2 INSTR3 COND_BRANCH label: INSTR4 � Trace start or stop set to this instruction INSTR5

If the condition for COND_BRANCH matches and the CPU jumps to ‘label’, the trace trigger is hit nevertheless.

Real time instruction monitoring

If an instruction monitoring address is set to an instruction after a conditional branch instruction and the branch is taken, the instruction execution is indicated at the pin even if the instruction is not executed.



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3. Detailed explanation The reason for this behaviour is that the CPU starts executing the instruction located after the conditional branch (INSTR4) but does not finish it. When the CPU has evaluated the branch condition and the condition is TRUE, it continues the execution at the branch target address (INSTR1) and discards the instruction after the branch (INSTR4). The DSU interprets this CPU behaviour wrongly as ‘execution of address after the conditional branch instruction’.

Following instructions are affected: CBNE_A_IMM_rel CWBNE_A_IMM_rel BBC_IOB_rel BBC_DIRB_rel BBC_ADRB_rel BBS_IOB_rel BBS_DIRB_rel BBS_ADRB_rel SBBS_ADRB_rel CWBNE_ea_IM_rel CBNE_ea_IMM_rel DBNZ_ea DWBNZ_ea Bcc_rel

Trace start/stop event detection

16FX-DSU4 support two different kinds of Trace start/stop events: triggered by Operand break channel or triggered by Instruction break channel. This limitation is regarding the Instruction break.

Assuming that an Instruction break channel is configured as Trace start or Trace stop event and the address is configured to point to an instruction after a conditional branch instruction (e.g. BCC). If the CPU executes the conditional branch and jumps to the branch target address the Trace start or Trace stop event is triggered. This will cause the trace to start or stop – depending on the configuration.

Real time instruction monitoring

16FX-DSU support real time instruction monitoring which 4 addresses. An execution of the configured address can be monitored at 4 different pins of MB96V300RB.

Assuming that a Real time instruction monitoring address is set to an instruction after a conditional branch, the execution is indicated even if the CPU branches to the jump target of the branch.


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4. Possible workaround Do not use instructions after conditional branch instructions as Trace start or Trace stop events or for real time instruction monitoring.



Divider Change of CLKP2/CLKP3 and Change of Stabilization Time




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Revision History

Version Date Remark 1 2007-11-12 Initial version 2 2007-11-14 Typo correction: 6 cycles SC_T[6] wait time is needed after SUB

clock stabilization time change (not after MAIN clock stab.change)3 2007-11-15 MB96F387 removed from list of affected devices 4 2007-11-19 Better description of the Workaround (example to ensure the wait

time in between divider change by peripheral access)


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16FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time

1. Description of functional limitation Changing of clock divider settings of CLKP2 and CLKP3 and change of stabilization time of the main clock or sub clock may be ignored, if the previous change has happened too short before.

2. List of affected Devices MB96F326ASA, MB96F326ASB, MB96F326AWA, MB96F326AWB, MB96F326RSA, MB96F326RSB, MB96F326RWA, MB96F326RWB, MB96F326YSA, MB96F326YSB, MB96F326YWA, MB96F326YWB, MB96F348CSB, MB96F348CSC, MB96F348CWB, MB96F348CWC, MB96F348HSB, MB96F348HSC, MB96F348HWB, MB96F348HWC, MB96F348TSB, MB96F348TSC, MB96F348TWB, MB96F348TWC, MB96F356ASA, MB96F356ASB, MB96F356AWA, MB96F356AWB, MB96F356RSA, MB96F356RSB, MB96F356RWA, MB96F356RWB, MB96F356YSA, MB96F356YSB, MB96F356YWA, MB96F356YWB, MB96V300BRB-ES

3. Detailed explanation Changing of clock divider settings of CLKP2 and CLKP3 and change of stabilization time of the main clock or sub clock may be ignored, if the previous change has happened too short before.

A minimum number of 6 cycles CLKB plus 6 cycles CLKS2 is needed for the clock divider settings, before the divider setting is allowed to be changed again.

A minimum number of 6 cycles CLKS1 plus 6 cycles MC_T[6] (main clock timer, bit6) is needed, before the main clock stabilization time is allowed to be changed again.

A minimum number of 6 cycles CLKS1 plus 6 cycles SC_T[6] (sub clock timer, bit 6) is needed, before the sub clock stabilization time is allowed to be changed again.

Following configuration registers are affected:

• CKFCR_PC2D (Peripheral group 2 clock divider)

• PLLCR_PC3D (Peripheral group 3 clock divider)

• CKSSR_MCST (Main clock stabilization time)

• CKSSR_SCST (Sub clock stabilization time)

Reason is the relaxation time of the used synchronizer circuit, which is needed to ensure data consistency of multiple bits.


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4. Possible workaround (1) Ensure minimum relaxation time of 6 cycles CLKB and 6 cycles CLKS2 before changing the clock divider setting again. Usually time for function entry or calling interrupt service is sufficient already. However it is worth to check minimum cycles between the divider changes of CKFCR_PC2D or PLLCR_PC3D, especially if low speed is used for CLKS2. If these minimum clock cycles can not be ensured otherwise, execute 3 dummy accesses to peripherals (read or write) before updating the clock divider again. The peripheral group 2 (CAN) or peripheral group 3 (USB) needs to be accessed, according to the clock divider to be changed. Synchronization time for the peripheral access consists of 2 clock cycles CLKB plus 2 clock cycles CLKP2 or CLKP3 in best case (synchronous mode). CLKP2 and CLKP3 are derived (divided) clocks of CLKS2.

(2) Do not change the Main clock or Sub clock stabilization time more than one times. Otherwise the relaxation time needs to be ensured (6 * 64 cycles of CLKMC or CLKSC + 6 cycles CLKS1). Usually it should not be required to change this setting multiple times.

5. Fujitsu countermeasure This phenomenon is fixed on future devices (since MB96F338 and MB96F379).

The fixed devices have no such functional limitation.


FLASH Reset




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Revision History

Version Date Remark 1 2007-11-14 Initial version (Uwe Moslehner) 2 2007-11-15 Description updated (Carsten Schonlau) 3 2007-12-06 Description updated, list of affected devices updated (mfr) 4 2008-01-10 Flash Memory Control Status registers renamed from

MFMCS/SFMCS to MCSRA/MCSRB. Effect of limitation for Flash A and Flash B described (CS)


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16FXFL0033: FLASH Reset

1. Description of functional limitation If a Software Reset, a Watchdog Reset or a Clock Stop Reset is asserted while the Flash memory is being programmed or erased, invalid data may be read subsequently.

2. List of affected Devices MB96F326ASA, MB96F326AWA, MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWA, MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348CSA, MB96F348CSB, MB96F348CSC, MB96F348CWA, MB96F348CWB, MB96F348CWC, MB96F348HSA, MB96F348HSB, MB96F348HSC, MB96F348HWA, MB96F348HWB, MB96F348HWC, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348TSA, MB96F348TSB, MB96F348TSC, MB96F348TWA, MB96F348TWB, MB96F348TWC, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F356ASA, MB96F356AWA, MB96F356RSA, MB96F356RWA, MB96F356YSA, MB96F356YWA, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB

3. Detailed explanation After submitting a Flash write or erase command, the Flash memory executes the automatic algorithm. In this state, a read access to the Flash memory returns the status of the hardware sequence flags instead of the Flash data (“BUSY state”). After completion of the automatic algorithm, the Flash memory automatically changes back into the “READ” state.

In case of an abnormal operation (for example when trying to program a bit from ‘0’ to ‘1’), the Flash memory enters the “TIMEOUT” state where also hardware sequence flags are output instead of Flash data. Return from “TIMEOUT” state to the “READ” state is possible by submitting the “Read/Reset” command

Executing a Power reset (Power-on or Low voltage) or an External reset initializes the Flash memory state machine from any state back to the “READ” state.

However the Flash memory is not initialized in case of a Software Reset, Watchdog Reset or Clock Stop Reset. This means the Flash memory continues to output the hardware sequence flags when being read. After reset release, the CPU reads the ROM configuration blocks of the Flash A (and Flash B for products supporting Flash B), leading to the following situation:

• Application crash if Flash A outputs the hardware sequence flags while the CPU reads the reset vector.

• Automatic setting of the Flash write protection registers does not work in case this feature is used. This is relevant only for products supporting Flash B).


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4. Possible workaround For Flash memory A: No Software, Watchdog or Clock Stop reset must be asserted when the Flash memory A is in the “BUSY” or “TIMEOUT” state (MCSRA:RDY=’0’).

• Do not assert a software reset as long as the MCSRA:RDY bit is ‘0’.

• Make sure the Watchdog timer is cleared on time when the MCSRA:RDY bit is ‘0’.

• Do not activate the Clock Stop reset function when programming the Flash memory A.

For Flash memory B: Do not use the automatic setting of the Flash write protection for this Flash.

Otherwise, the same restrictions as for Flash memory A apply (No Software, Watchdog or Clock Stop reset must be asserted when the Flash memory B is in the “BUSY” or “TIMEOUT” state (MCSRB:RDY=’0’)).

The TIMEOUT state should be left by submitting the “read/reset” command as soon as this state is indicated by the hardware sequence flags.

5. Fujitsu countermeasure The Flash state machine is initialized by any reset, including Software, Watchdog and Clock Stop reset.

Future MCUs will not have this limitation.


Watchdog intervals and delay on the watchdog reset assertion




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Revision History

Version Date Remark 1 2007-11-14 Initial version 2 2007-11-15 Interval change added, description updated 3 2008-07-21 Added MB96F386RSB, MB96F386RWB, MB96F386YSB,

MB96F386YWB, MB96F387RSB, MB96F387RWB, MB96F387YSB, MB96F387YWB


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16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion

1. Description of functional limitation a) The specification of the watchdog intervals in the preliminary hardware manual (up to

revision “MB96300_HWM_rev13_20070827”) was wrong.

b) If the watchdog is not cleared within the specified interval time, then the watchdog reset assertion will not be immediate (maximum delay is one interval time).

2. List of affected Devices MB96F326ASA, MB96F326AWA, MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWA, MB96F346ASA, MB96F346AWA, MB96F346RSA, MB96F346RWA, MB96F346YSA, MB96F346YWA, MB96F347ASA, MB96F347AWA, MB96F347RSA, MB96F347RWA, MB96F347YSA, MB96F347YWA, MB96F348ASA, MB96F348AWA, MB96F348CSA, MB96F348CSC, MB96F348CWB, MB96F348HSA, MB96F348HSC, MB96F348HWB, MB96F348RSA, MB96F348RWA, MB96F348TSA, MB96F348TSC, MB96F348TWB, MB96F348YSA, MB96F348YWA, MB96F356ASA, MB96F356RSA, MB96F356YSA, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB, MB96V300BRB-ES, MB96V300RB-ES

The corrected specification of the watchdog intervals in the hardware manual is valid for ALL 16FX devices.


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3. Detailed explanation a) The specification of the watchdog interval times in the hardware manual is corrected.

The effective watchdog interval times are half as long as previously specified:

Figure 12.2-2 Configuration of the Watchdog Timer Configuration Register (WDTC)

Old specification Corrected specification

WTI3 WTI2 WTI1 WTI0Watchdog Timer Interval selection

bits (CLKWT is clock selected by

WTCS[1:0] bits)

Watchdog Timer Interval selection bits

(CLKWT is clock selected by WTCS[1:0] bits)

0 0 0 0 29 / CLKWT 28 / CLKWT 0 0 0 1 210 / CLKWT 29 / CLKWT 0 0 1 0 211 / CLKWT 210 / CLKWT 0 0 1 1 212 / CLKWT 211 / CLKWT 0 1 0 0 213 / CLKWT 212 / CLKWT 0 1 0 1 214 / CLKWT 213 / CLKWT 0 1 1 0 215 / CLKWT 214 / CLKWT 0 1 1 1 216 / CLKWT 215 / CLKWT 1 0 0 0 217 / CLKWT 216 / CLKWT 1 0 0 1 218 / CLKWT 217 / CLKWT 1 0 1 0 219 / CLKWT 218 / CLKWT 1 0 1 1 220 / CLKWT 219 / CLKWT 1 1 0 0 221 / CLKWT 220 / CLKWT 1 1 0 1 222 / CLKWT 221 / CLKWT 1 1 1 0 223 / CLKWT 222 / CLKWT 1 1 1 1 224 / CLKWT 223 / CLKWT

The resulting interval times described in Table 12.2-1 are reduced accordingly by 50% to the following values:

WTI3 WTI2 WTI1 WTI0 RC clock selected

(corresponding time for nominal RC clock frequency

of 2MHz/100kHz)

Main clock selected (corresponding time for Main clock frequency

of 4MHz)

Sub clock selected (corresponding time for

Sub clock frequency of 32.768kHz)

0 0 0 0 28 / CLKRC (~128us/2.5ms) 28 / CLKMC (~64us) 28 / CLKSC (7.8ms) 0 0 0 1 29 / CLKRC (~256us/5.1ms) 29 / CLKMC (~128us) 29 / CLKSC (15.6ms) 0 0 1 0 210 / CLKRC (~512us/10.2ms) 210 / CLKMC (~256us) 210 / CLKSC (31.25ms) 0 0 1 1 211 / CLKRC (~1ms/20.5ms) 211 / CLKMC (~512us) 211 / CLKSC (62.5ms) 0 1 0 0 212 / CLKRC (~2ms/41ms) 212 / CLKMC (~1ms) 212 / CLKSC (125ms) 0 1 0 1 213 / CLKRC (~4ms/82ms) 213 / CLKMC (~2ms) 213 / CLKSC (250ms) 0 1 1 0 214 / CLKRC (~8ms/164ms) 214 / CLKMC (~4ms) 214 / CLKSC (500ms) 0 1 1 1 215 / CLKRC (~16ms/328ms) 215 / CLKMC (~8ms)) 215 / CLKSC (1s) 1 0 0 0 216 / CLKRC (~32ms/655ms) 216 / CLKMC (~16ms) 216 / CLKSC (2s) 1 0 0 1 217 / CLKRC (~65ms/1.3s) 217 / CLKMC (~32ms) 217 / CLKSC (4s) 1 0 1 0 218 / CLKRC (~131ms/2.6) 218 / CLKMC (~65ms) 218 / CLKSC (8s) 1 0 1 1 219 / CLKRC (~262ms/5.2s) 219 / CLKMC (~131ms) 219 / CLKSC (16s) 1 1 0 0 220 / CLKRC (~524ms/10.4) 220 / CLKMC (~262ms) 220 / CLKSC (32s) 1 1 0 1 221 / CLKRC (~1.05s/21s) 221 / CLKMC (~524us) 221 / CLKSC (64s) 1 1 1 0 222 / CLKRC (~2.1s/42s) 222 / CLKMC (~1.049s) 222 / CLKSC (128s) 1 1 1 1 223 / CLKRC (~4.2s/84s) 223 / CLKMC (~2.097s) 223 / CLKSC (256s)


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b) For devices which are listed above, the following restriction applies:

If the watchdog is not cleared within the interval time specified in the corrected hardware manual (WDTC:WTI setting), then a watchdog reset is asserted. The reset assertion however will not happen immediately after the watchdog counter has reached the interval end time. Instead there are two possibilities:

1. If the watchdog is cleared after elapsing of the specified interval time, then the reset will be asserted immediately after this watchdog clear command.

2. If the watchdog is not cleared within a second interval of the same length as the specified interval time, then the watchdog reset will be asserted at the end of this second interval time. Hence the maximum time for which the watchdog reset assertion can be delayed equals to the previously specified interval time.

Behaviour of devices with delayed watchdog reset assertion:


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4. Possible workaround Select a suitable watchdog interval according to the corrected hardware manual and clear the Watchdog within this specified time.

5. Fujitsu countermeasure • The Watchdog specification in the hardware manual was corrected to show the

correct time intervals where the watchdog must be cleared to avoid a reset.

• The Watchdog reset assertion logic was modified to fix the problem with the delayed reset assertion for all future devices (since MB96F338, MB96F379, MB96F326B and MB96385). For these devices, the Watchdog reset will be asserted directly at the end of the selected interval.

Please note that the effective watchdog interval times of ALL devices (before and after this bug fix) are same.


Limitation when LCD is used with duty cycle 1/2 or 1/3




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Revision History

Version Date Remark 1 2007-12-06 Initial version (Andre’ Marth)


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16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3

1. Description of functional limitation If LCD Controller is used with a duty cycle of 1/2 or 1/3, all LCD-common drivers (COM0, COM1, COM2, COM3) must be enabled in register LCDCMR:COMEN[3:0] although they are not required. The IO-pins of the not required LCD-common drivers cannot be used for other purposes.

2. List of affected Devices MB96V300RB, MB96V300BRB, MB96F386YA, MB96F386RA, MB96F387YA, MB96F387RA

3. Detailed explanation Every LCD-common driver output (COM-line) has its own enable bit COMEN in the LCDCMR-register (LCDCMR;COMEN[3:0]).

The 16FX-LCD controller offers different duty cycle settings which require a different number of COM-lines.

1/2 duty cycle – COM0, COM1

1/3 duty cycle – COM0, COM1, COM2

1/4 duty cycle – COM0, COM1, COM2, COM3

On affected devices all COM-lines must be enabled in LCDCMR:COMEN[3:0] to operate the LCD controller, independent of the selected duty cycle.

This disables the digital function of the General Purpose Pin. Hence the pin cannot be used for other functions although LCD-common driver function is not required on this pin.

4. Possible workaround Enable all LCDCMR:COMEN[3:0] bit independent from the selected duty cycle.

5. Fujitsu countermeasure Future MCU will not have this limitation. The design is modified to enable the LCD-Controller if at least one of the LCDCMR:COMEN[3:0]-bits is enabled.


EDSU2 register not available on all devices (INT9 source selection)




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Revision History

Version Date Remark 1 2008-01-10 (UM) Initial version 2 2008-07-21 Changed list of affected devices to explicit part number listing (no

change of affected devices)


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16FXFL0036: EDSU2 register not available on all devices (INT9 source selection)

1. Description of functional limitation The registers EDSU2_TSEL and EDSU2_RSEL are not available.

2. List of affected Devices MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HWA, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348TSA, MB96F348TWA, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB, MB96V300RB

3. Detailed explanation -

4. Possible workaround On these devices only the hard-wired interrupt sources (selected by EDSU_SEL1 and EDSU_SEL0) can be mapped to INT9. The full flexibility is not available.

5. Fujitsu countermeasure Newer devices will support full flexible IRQ selection by EDSU2.


Initial value of some I/O timer registers not correct




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Revision History



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16FXFL0037: Initial value of some I/O timer registers not correct

1. Description of functional limitation At certain conditions, some registers of the I/O timer do not show the correct initial value.

2. List of affected Devices MB96F326RWA, MB96F326YWA, MB96F326RSA, MB96F326YSA, MB96F346RWA, MB96F346YWA, MB96F346RSA, MB96F346YSA, MB96F346RWB, MB96F346YWB, MB96F346RSB, MB96F346YSB, MB96F347RWA, MB96F347YWA, MB96F347RSA, MB96F347YSA, MB96F347RWB, MB96F347YWB, MB96F347RSB, MB96F347YSB, MB96F348RWA, MB96F348YWA, MB96F348RSA, MB96F348YSA, MB96F348RWB, MB96F348YWB, MB96F348RSB, MB96F348YSB, MB96F348HWB, MB96F348TWB, MB96F348HSB, MB96F348TSB, MB96F348HWC, MB96F348TWC, MB96F348HSC, MB96F348TSC, MB96F356RWA, MB96F356YWA, MB96F356RSA, MB96F356YSA, MB96F386RWA, MB96F386YWA, MB96F386RSA, MB96F386YSA, MB96F387RWA, MB96F387YWA, MB96F387RSA, MB96F387YSA, MB96384RWA, MB96384YWA, MB96384RSA, MB96384YSA, MB96385RWA, MB96385YWA, MB96385RSA, MB96385YSA, MB96F386RWA, MB96F386YWA, MB96F386RSA, MB96F386YSA, MB96F387RWA, MB96F387YWA, MB96F387RSA, MB96F387YSA, MB96F338RSA, MB96F338RWA, MB96F379RWA, MB96F379YWA, MB96F379RSA, MB96F379YSA, MB96F389RWA, MB96F389YWA, MB96F389RSA, MB96F389YSA, MB96F386RWB, MB96F386YWB, MB96F386RSB, MB96F386YSB, MB96F387RWB, MB96F387YWB, MB96F387RSB, MB96F387YSB

3. Detailed explanation When the MCU is in internal Vector Mode (MD[2:0] = 0 1 1B) and the Boot ROM is performing temporary UART scan (the UART Scan Deactivation Marker {USDM1, USDM0} is not set to the value 292D3A7BH), then the following registers do not show the correct initial value:

For MB96F356, MB96F326:

Register Correct initial value

Actual initial value

Effect

ICE67 X X X 0 X 0 0 0 B X X X 1 X 1 0 0 B ICE67:ICUS6 is set to 1, hence USART2 is input of ICU6 ICE67:ICUS7 is set to 1, hence USART3 is input of ICU7

ICE89 X X X 0 X 0 0 0 B X X X 1 X 0 0 0 B ICE89:ICUS9 is set to 1, hence USART7 is input of ICU9

ICE1011 X X X 0 X 0 0 0 B X X X 0 X 1 0 0 B ICE1011:ICUS9 is set to 1, hence USART8 is input of ICU10


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Register Correct initial value

Actual initial value

Effect

ICS89 0 0 0 0 0 0 0 0 B X X 0 0 1 1 1 1 B ICS89:ICP9 and ICS89:ICP8 are not reset to 0 but are undefined. ICS89:EG91, ICS89:EG90, ICS89:EG81, ICS89:EG80 are set to 1, hence edge detection is active for both edges.

ICS1011 0 0 0 0 0 0 0 0 B X X 0 0 1 1 1 1 B ICS1011:ICP11 and ICS1011:ICP10 are not reset to 0 but are undefined. ICS1011:EG111, ICS1011:EG110 are set to 1, hence edge detection is active for both edges at ICU11 ICS1011:EG101, ICS1011:EG100 are set to 1, hence edge detection is active for both edges at ICU10

TCCSL2 0 0 0 0 0 0 0 0 B X 0 0 0 0 0 1 0 B TCCSL2:IVF is not reset to 0 but is undefined TCCSL2:CLK1 is set to 1, hence Φ/4 is selected instead of Φ for Free-Running Timer 2.

TCCSL3 0 0 0 0 0 0 0 0 B X 0 0 0 0 0 1 0 B TCCSL2:IVF is not reset but may be undefined TCCSL2:CLK1 is set to 1, hence Φ/4 is selected instead of Φ for Free-Running Timer 3.

For all other affected devices: Register Documented

initial value Actual initial

value Effect

ICE01 X X X 0 X 0 0 0 B X X X 1 X 1 0 0 B ICUS0 is set to 1, hence USART0 is input of ICU0 ICUS1 is set to 1, hence USART1 is input of ICU1

ICE67 X X X 0 X 0 0 0 B X X X 1 X 1 0 0 B ICUS6 is set to 1, hence USART2 is input of ICU6 ICUS7 is set to 1, hence USART3 is input of ICU7

4. Possible workaround Please initialize the registers to the correct value by software.



Watchdog detection during debugging is not correct




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Revision History

Version Date Remark 1 2008-07-21 Initial version 2 2008-11-27 Added MB96F918FSA, MB96F918DSA, MB96F918FWA,

MB96F918DWA


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16FXFL0038: Watchdog detection during debugging is not correct

1. Description of functional limitation An enabled watchdog will not be properly detected, if the user application has been stopped due to a breakpoint or an external break.

2. List of affected Devices MB96345RSA, MB96345RWA, MB96345YSA, MB96345YWA, MB96346RSA, MB96346RWA, MB96346YSA, MB96346YWA, MB96384RSA, MB96384RWA, MB96384YSA, MB96384YWA, MB96385RSA, MB96385RWA, MB96385YSA, MB96385YWA, MB96F326ASA, MB96F326ASA, MB96F326AWA, MB96F326AWA, MB96F326RSA, MB96F326RSA, MB96F326RWA, MB96F326RWA, MB96F326YSA, MB96F326YSA, MB96F326YWA, MB96F326YWA, MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348CSA, MB96F348CSC, MB96F348CWA, MB96F348CWC, MB96F348HSB, MB96F348HSC, MB96F348HWB, MB96F348HWC, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348TSB, MB96F348TSC, MB96F348TWB, MB96F348TWC, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F356ASA, MB96F356ASA, MB96F356AWA, MB96F356AWA, MB96F356RSA, MB96F356RSA, MB96F356RWA, MB96F356RWA, MB96F356YSA, MB96F356YSA, MB96F356YWA, MB96F356YWA, MB96F378HSA, MB96F378HWA, MB96F378TSA, MB96F378TWA, MB96F379RSA, MB96F379RWA, MB96F379YSA, MB96F379YWA, MB96F386RSA, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWA, MB96F387YWB, MB96F388HSA, MB96F388HWA, MB96F388TSA, MB96F388TWA, MB96F389RSA, MB96F389RWA, MB96F389YSA, MB96F389YWA, MB96F918FSA, MB96F918DSA, MB96F918FWA, MB96F918DWA

3. Detailed explanation After stopping user program due to breakpoint or external break, the Watchdog is checked for active watchdog operation. That check fails, if the bit0 of watchdog interval WTI (WDTC:WTI0) is '1'.


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4. Possible workaround If background debugging is used (BDCB marker is set) for applications, which use the watchdog, only Watch Timer Intervals (WDTC:WTI[3..0]) with WTI0=0 shall be used. Another possibility would be to disable the watchdog in the application if background debugging is enabled. Otherwise, the monitor program may not correctly detect, whether watchdog is active or not.



Low voltage detector threshold levels differ from datasheet specification




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Revision History

Version Date Remark 1 2008-01-11 Initial version 2 2008-07-17 Added MB96V300BRB, MB96F348*A


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16FXFL0039: Low voltage detector threshold levels differ from datasheet specification

1. Description of functional limitation The low voltage detector threshold levels specified in the datasheet are not valid for all devices. For the devices listed below, the correct detection levels are specified in this document.

2. List of affected Devices MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWA, MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HSB, MB96F348HWA, MB96F348HWB, MB96F348TSA, MB96F348TSB, MB96F348TWA, MB96F348TWB, MB96F356RSA, MB96F356RWA, MB96F356YSA, MB96F356YWA, MB96V300BRB, MB96V300RB

3. Detailed explanation The devices listed above are using a different version of the low voltage detector with different max values for the detection levels as described in the following table:

Value Detection Level

Symbol Min Max

(Max value according to datasheet for reference)

Level 0 VDL0 2.7V 2.97V (2.9V) Level 1 VDL1 2.9V 3.2V (3.1V) Level 2 VDL2 3.1V 3.4V (3.3V) Level 3 VDL3 3.5V 3.85V (3.75V) Level 4 VDL4 3.6V 4.0V (3.85V) Level 5 VDL5 3.7V 4.1V (3.95V) Level 6 VDL6 3.8V 4.2V (4.05V) Level 7 VDL7 3.9V 4.35V (4.15V) Level 8 VDL8 4.0V 4.45V (4.25V) Level 9 VDL9 4.1V 4.55V (4.35V)


5. Fujitsu countermeasure Revised versions of all affected MCUs with correct detection levels are available.


Limitation in using P13_5 and P13_7 as input pin




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Revision History



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16FXFL0040: Limitation in using P13_5 and P13_7 as input

1. Description of functional limitation Pin input enable register of pin P13_5 (PIER13_IE5) controls also pin input function of pin P13_7.

Pin input enable register of pin P13_7 (PIER13_IE7) does not have any effect on pin P13_7 and any other pin.

2. List of affected Devices MB96F378TSA, MB96F378TWA, MB96F379RSA, MB96F379RWA, MB96F379YSA,

MB96F379YWA, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB,

MB96384RSA, MB96384RWA, MB96384YSA, MB96384YWA, MB96385RSA,

MB96385RWA, MB96385YSA, MB96385YWA, MB96F378HSA, MB96F378HWA,

MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA,

MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB,

MB96F387YWA, MB96F387YWB, MB96F388HSA, MB96F388HWA, MB96F388TSA,

MB96F388TWA, MB96F389RSA, MB96F389RWA, MB96F389YSA, MB96F389YWA,

MB96V300BRB-ES, MB96V300RB-ES when emulating devices of MB96370, MB96380 series

3. Detailed explanation If ‘1’ is written to port input enable register of pin P13_5 (PIER13_IE5), then Input function of Pin P13_5 and P13_7 is enabled.

If ‘0’ is written to port input enable register of pin P13_5 (PIER13_IE5), then Input function of Pin P13_5 and P13_7 is disabled.

Writing to input enable register of pin P13_7 (PIER13_IE7) has no effect on input function of any pin.

4. Possible workaround If P13_7 is needed as input:

- Set PIER13_IE5 = 1 (enable input of pin P13_5 and P13_7)

- If P13_5 is unconnected:


of 185

1) Set PUCR13_PU5 = 1 (enable pull-up to avoid latch up).

or

2) Set PDR13_P5 to 0 or 1 (output data value) as required by application. Set DDR13_D5 = 1 (enable output driver). Enabling the pull-up or output driver avoids a latch-up on this pin that could occur if this pin is no driven.

- If any input or output function is used on P13_5: enabled input is no problem for port function

If P13_5 is needed as input:

- Set PIER13_IE5 = 1 (enable input of pin P13_5 and P13_7)

- If P13_7 is unconnected:

1) Set PUCR13_PU7 = 1 (enable pull-up to avoid latch up).

or

2) Set PDR13_P7 to 0 or 1 (output data value) as required by application. Set DDR13_D7 = 1 (enable output driver),

Enabling the pull-up or output driver avoids a latch-up on this pin that could occur if this pin is not driven.

- If any input or output function is used on P13_7: enabled input is no problem for port function


16-BIT MICROCONTROLLER

MB96300 SERIES

Chapter 0 16FXFL0040: Limitation in using P13_5 and P13_7 as input

© Fujitsu Microelectronics Europe GmbH- 149 - CI-300024-E-v11

Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt

(16FX functional limitation 16FXFL0041)

CUSTOMER INFORMATION



Revision History Date Issue

2008-09-02 V1.0 (UM) Initial version 2008-11-26 V1.1 (MFR) Reformatted, added MB96F336USA, MB96F336UWA

This document contains 185 pages.

Abbreviations:

FME Fujitsu Microelectronics Europe GmbH

MCU Microcontroller

Chapter 0 16FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt


16FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt

1. Problem Description The instructions to scan for occurrence of a bit pattern (SCEQ: character byte, SCWEQ: 16 bit word) in a field of data do not work reliable together with interrupts. Cases exist, where an existing match in a bit pattern may not be found.

The C-compiler and libraries provided with Softune Workbench (including all versions), do not make use of these instructions.

2. List of affected Devices MB96F326RWA, MB96F326YWA, MB96F326RSA, MB96F326YSA, MB96F326RWB, MB96F326YWB, MB96F326RSB, MB96F326YSB, MB96F336USA, MB96F336UWA, MB96F338RWA, MB96F338UWA, MB96F338YWA, MB96F338RSA, MB96F338USA, MB96F338YSA, MB96345RWA, MB96345YWA, MB96345RSA, MB96345YSA, MB96346RWA, MB96346YWA, MB96346RSA, MB96346YSA, MB96F346AWA, MB96F346RWA, MB96F346YWA, MB96F346ASA, MB96F346RSA, MB96F346YSA, MB96F346AWB, MB96F346RWB, MB96F346YWB, MB96F346ASB, MB96F346RSB, MB96F346YSB, MB96F347AWA, MB96F347RWA, MB96F347YWA, MB96F347ASA, MB96F347RSA, MB96F347YSA, MB96F347AWB, MB96F347RWB, MB96F347YWB, MB96F347ASB, MB96F347RSB, MB96F347YSB, MB96F348AWA, MB96F348RWA, MB96F348YWA, MB96F348ASA, MB96F348RSA, MB96F348YSA, MB96F348AWB, MB96F348RWB, MB96F348YWB, MB96F348ASB, MB96F348RSB, MB96F348YSB, MB96F348HWA, MB96F348TWA, MB96F348HSA, MB96F348TSA, MB96F348CWB, MB96F348HWB, MB96F348TWB, MB96F348CWB, MB96F348HSB, MB96F348TSB, MB96F348CWC, MB96F348HWC, MB96F348TWC, MB96F348CSC, MB96F348HSC, MB96F348TSC, MB96F356RWA, MB96F356YWA, MB96F356RSA, MB96F356YSA, MB96F356RWB, MB96F356YWB, MB96F356RSB, MB96F356YSB, MB96F378RWA, MB96F378YWA, MB96F378RSA, MB96F378YSA, MB96F379RWA, MB96F379YWA, MB96F379RSA, MB96F379YSA, MB96F386RWA, MB96F386YWA, MB96F386RSA, MB96F386YSA, MB96F387RWA, MB96F387YWA, MB96F387RSA, MB96F387YSA, MB96F386RWB, MB96F386YWB, MB96F386RSB, MB96F386YSB, MB96F387RWB, MB96F387YWB, MB96F387RSB, MB96F387YSB, MB96384RWA, MB96384YWA, MB96384RSA, MB96384YSA, MB96385RWA, MB96385YWA, MB96385RSA, MB96385YSA, MB96F388RWA, MB96F388YWA, MB96F388RSA, MB96F388YSA, MB96F389RWA, MB96F389YWA, MB96F389RSA, MB96F389YSA, MB96V300B, MB96V300

3. Details of the Failure The instructions to scan for occurrence of a bit pattern (character byte or 16 bit word) in a field of data do not work reliable together with interrupts.

Operands and specification of SCEQ/SCWEQ:

Chapter 0 16FXFL0041: Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt


AH Pointer to the actual position of an element in a field of data with automatic increment/decrement at each step of comparison

AL Compare value to be searched for (byte or word)

RW0 Number of elements to compare; will be decremented at each step of comparison

FLAGS NZVC will be influenced by the comparison. In case of the element was found, the zero flag (Z) will be set.

The instruction should finish if either the specified element was found or the end of the field of data was reached (RW0 = 0).

Affected are the following instructions:

Mnemonic First byte opcode Second byte opcode

SCEQI 0x6E 0x80, 0x81, 0x82, 0x83

SCEQD 0x6E 0x90, 0x91, 0x92, 0x93

SCWEQI 0x6E 0xA0, 0xA1, 0xA2, 0xA3

SCWEQD 0x6E 0xB0, 0xB1, 0xB2, 0xB3

All string instructions have the feature to suspend operation at interrupt occurrence.

The phenomenon happens, if the interrupt request is issued at the same time when the specified byte or word in AL is found in the field of data. In such a case the CPU branches to interrupt service and resumes operation of the string scan instruction.

The information that the specified byte or word was found is discarded. Effectively data in AH, RW0 and the Flags are wrong at the end of the execution of the string scan instructions. The match could not be found in some cases, if there is an IRQ occurring during the execution of SCEQ/SCWEQ. The instruction may stop either at the next occurrence of the specified element or it runs until the end without finding the element where the interrupt occurs.

4. Possible workaround A) Do not use SCEQ/SCWEQ instructions. Implement searching the element by using other instructions.

B) Do not allow interrupts during the use of SCEQ/SCWEQ instructions.

5. Fujitsu Countermeasure Under investigation. Existing devices will not be changed.

Failure of String Instructions and WBTC/WBTS Instructions



MB96300 SERIES

Failure of String Instructions and WBTC/WBTS Instructions (16FX functional limitation

16FXFL0042)





2008-09-02 V1.0; UMo; 1st version 2008-10-22 V1.1; MWi; Version from FJ document 16FX_MB963XX_report_E_2008294 2008-11-27 V1.2; MFR; Added MB96F336USA, MB96F336UWA


Abbreviations:


MCU Microcontroller



16FXFL0042: Failure of String Instructions and WBTC/WBTS Instructions

1. Problem Description We identified failure in string instructions (MOVS, MOVSD, SCEQ, SCEQD, FILS, MOVSW, MOVSWD, SCWEQ, SCWEQD, FILSW) and WBTC/WBTS instructions of the F2MC-16FX family, thus we would like to make a report about it. Note that the SCEQ, SCEQD, SCWEQ, SCWEQD, and WBTC/WBTS instructions are not used by Softune C compiler and library. The MOVS, MOVSD, FILS, MOVSW, MOVSWD, and FILSW instructions are used by Softune C compiler and library, but it is confirmed that any code pattern concerned with the failure is not generated.

In addition to that, the failure does not occur in the following cases.

• Only the C language is used for programming.

• The assembly language is used but any instruction concerned with the failure (see 1-2) is not used.

• Interrupt disabling (see 1-1) is performed only in interrupt processing routines.

• The instructions concerned with the failure are used but there is no interrupt disabling immediately before them (within 4 CPU clock cycles). (The MOVS and FILS instructions are used in start.asm usually supplied with Softune, but they are not used in a manner that causes the failure to occur.)

1.1 Interrupt Disabling Interrupt disabling refers to the following processes.

• Clear interrupt source flags of peripheral functions.

• Set interrupt enable/disable bits of peripheral functions.

• Set the interrupt level setting value of a peripheral function (ILR/ICR) to the ILM value or higher. [ILR/ICR value ≥ ILM value]

• Allow a peripheral function for which an interrupt setting has been configured to perform DMA transfer.

• (This means that the interrupt requested destination is changed from the CPU to DMA, thus it is regarded as interrupt request disabled status as viewed from the CPU.)

* Note that I flag/P flag clearing and interrupt mask processing by ILM change are not included in the interrupt disabling mentioned above.

1.2 Instructions concerned with the failure MOVS, MOVSD, SCEQ, SCEQD, FILS, MOVSW, MOVSWD, SCWEQ, SCWEQD, FILSW, WBTC, and WBTS



If you employed the assembly language, we would like to ask you to check the following.

2. List of affected Devices

Series Product name

MB96310 series MB96F313RWA, MB96F313YWA, MB96F313RSA, MB96F313YSA, MB96F315RWA, MB96F315YWA, MB96F315RSA, MB96F315YSA

MB96320 series MB96F326RWA, MB96F326YWA, MB96F326RSA, MB96F326YSA, MB96F326RWB, MB96F326YWB, MB96F326RSB, MB96F326YSB,

MB96330 series MB96F336USA, MB96F336UWA, MB96F338RWA, MB96F338UWA, MB96F338YWA, MB96F338RSA, MB96F338USA, MB96F338YSA,

MB96340 series MB96345RWA, MB96345YWA, MB96345RSA, MB96345YSA, MB96346RWA, MB96346YWA, MB96346RSA, MB96346YSA, MB96F346AWA, MB96F346RWA, MB96F346YWA, MB96F346ASA, MB96F346RSA, MB96F346YSA, MB96F346AWB, MB96F346RWB, MB96F346YWB, MB96F346ASB, MB96F346RSB, MB96F346YSB, MB96F347AWA, MB96F347RWA, MB96F347YWA, MB96F347ASA, MB96F347RSA, MB96F347YSA, MB96F347AWB, MB96F347RWB, MB96F347YWB, MB96F347ASB, MB96F347RSB, MB96F347YSB, MB96F348AWA, MB96F348RWA, MB96F348YWA, MB96F348ASA, MB96F348RSA, MB96F348YSA, MB96F348AWB, MB96F348RWB, MB96F348YWB, MB96F348ASB, MB96F348RSB, MB96F348YSB, MB96F348HWA, MB96F348TWA, MB96F348HSA, MB96F348TSA, MB96F348CWB, MB96F348HWB, MB96F348TWB, MB96F348CWB, MB96F348HSB, MB96F348TSB, MB96F348CWC, MB96F348HWC, MB96F348TWC, MB96F348CSC, MB96F348HSC, MB96F348TSC, MB96F345DS, MB96F345DW, MB96F345FS, MB96F345FW


MB96F355RWA, MB96F355YWA, MB96F355RSA, MB96F355YSA

MB96370 series MB96F378RWA, MB96F378YWA, MB96F378RSA, MB96F378YSA, MB96F379RWA, MB96F379YWA, MB96F379RSA, MB96F379YSA,

MB96380 series MB96F386RWA, MB96F386YWA, MB96F386RSA, MB96F386YSA, MB96F387RWA, MB96F387YWA, MB96F387RSA, MB96F387YSA, MB96F386RWB, MB96F386YWB, MB96F386RSB, MB96F386YSB, MB96F387RWB, MB96F387YWB, MB96F387RSB, MB96F387YSB, MB96384RWA, MB96384YWA, MB96384RSA, MB96384YSA, MB96385RWA, MB96385YWA, MB96385RSA, MB96385YSA, MB96F388RWA, MB96F388YWA, MB96F388RSA, MB96F388YSA, MB96F389RWA, MB96F389YWA, MB96F389RSA, MB96F389YSA,

Evaluation chip MB96V300B, MB96V300



3. Details of the Failure The details of the failure are as stated below.

This failure occurs when there is interrupt disabling immediately before the instructions concerned with the failure (within 4 CPU clock cycles); an interrupt that takes place during execution of the instruction concerned with the failure causes the execution of the instruction to end before completion and execution of the next instruction to start. In addition to that, due to this phenomenon, to the CPU program counter (PC), the instruction queue counter increases by 1. Consequently, it causes the microprocessor to start executing the next instruction without resuming the instruction concerned with the failure, and the CPU results in running, having inconsistency between the instruction code and PC. A relative branch in that situation causes the MCU to malfunction.

3.1. Instructions concerned with the failure and their faulty operations

In addition to that, this faulty phenomenon causes the instruction queue counter to incorrectly increase by 1.

The figure below shows the faulty operation in the CPU pipeline model.

Instructions concerned with the failure

Faulty operation

MOVS, MOVSD, MOVSW, MOVSWD

The next instruction is executed while array transfer remains imperfect.

FILS, FILSW The next instruction is executed while array initialization remains imperfect.

SCEQ, SCWEQ Array scan ends in imperfect state, and then the next instruction is executed.

WBTC, WBTS Bit wait status is cancelled, and then the next instruction is executed.



CLR IRQ

CLR IRQ

CLR IRQ

CLR IRQ

String Instruction

String Instruction

String Instruction

String InstructionStage 3 (WB)

Stage 2 (EX)

Stage 1 (D1)

Stage 0 (D0)

IRQ1

suspend next instruction

next

3

2

IRQacceptance

4

5

An interrupt event occurs and an IRQ is set. By the IRQ, the processing of the instruction concerned with the failure on Stage 0 (string instruction) is interrupted. The interrupt disabling immediately before (CLR IRQ) it reaches Stage 3 and this causes the IRQ to be cleared. The interrupt generated by that event is never accepted, but the string instruction remains interrupted. The instruction queue counter increases by 1 while the interrupted string instruction keeps on being not resumed, and then the next instruction is executed. A relative branch in that situation causes the MCU to malfunction.



4. Possible workaround If the instructions concerned with the failure are used in assembly language representation, please take any of the following measures to prevent the failure.

1. Write the program by not using the instructions concerned with the failure.

2. Perform interrupt disabling only in interrupt processing routines.

3. To perform interrupt disabling before an instruction concerned with the failure, secure a space of 4 instructions or more.

(Example) CLRB ENIR0:0 //interrupt disabling NOP // ↑

NOP //secure a space of 4 instructions or more. NOP //

NOP // ↓MOVS DTB, ADB //instruction concerned with the failure

* It is confirmed that any code pattern concerned with the failure is not generated by Softune C compiler and library. The MOVS and FILS instructions are used in start.asm usually supplied with Softune, but they are not used in a manner that causes the failure to occur.



5. Request for Confirmation We would like to solicitously ask you to immediately check whether there is the failure in your use and notify us of it by November 7, 2008. We are now examining permanent measures against the failure and planning to inform you of solution by the end of November. We would like to express our apology for your inconvenience due to the failure.

6. References This customer information relates to the FJ document 16FX_MB963XX_report_E_2008294 with equal content.


MB96300 SERIES

Limitations for IRQ clearing of LIN-USART and RTC


Limitations of clearing Interrupt at LIN-USART and RTC








2008-10-22 V1.0; MWi; Version from FJ document 16FX_MB963XX_report_E_2008323 2008-11-27 V1.1; MFR; Added MB96F336USA, MB96F336UWA


Abbreviations:


MCU Microcontroller





1. Problem Description We identified the delay in clear timing of interrupt cause bit of LIN-USART and RTC for the F2MC-16FX family. We inform you of the method of the clearness of the interrupt cause bit of LIN-USART and RTC, we would like to ask you to check the following.



2. List of affected Devices

Series Product name

MB96310 series MB96F313RWA, MB96F313YWA, MB96F313RSA, MB96F313YSA, MB96F315RWA, MB96F315YWA, MB96F315RSA, MB96F315YSA


MB96330 series MB96F336USA, MB96F336UWA, MB96F338RWA, MB96F338UWA, MB96F338YWA, MB96F338RSA, MB96F338USA, MB96F338YSA,

MB96340 series MB96345RWA, MB96345YWA, MB96345RSA, MB96345YSA, MB96346RWA, MB96346YWA, MB96346RSA, MB96346YSA, MB96F346AWA, MB96F346RWA, MB96F346YWA, MB96F346ASA, MB96F346RSA, MB96F346YSA, MB96F346AWB, MB96F346RWB, MB96F346YWB, MB96F346ASB, MB96F346RSB, MB96F346YSB, MB96F347AWA, MB96F347RWA, MB96F347YWA, MB96F347ASA, MB96F347RSA, MB96F347YSA, MB96F347AWB, MB96F347RWB, MB96F347YWB, MB96F347ASB, MB96F347RSB, MB96F347YSB, MB96F348AWA, MB96F348RWA, MB96F348YWA, MB96F348ASA, MB96F348RSA, MB96F348YSA, MB96F348AWB, MB96F348RWB, MB96F348YWB, MB96F348ASB, MB96F348RSB, MB96F348YSB, MB96F348HWA, MB96F348TWA, MB96F348HSA, MB96F348TSA, MB96F348CWB, MB96F348HWB, MB96F348TWB, MB96F348CWB, MB96F348HSB, MB96F348TSB, MB96F348CWC, MB96F348HWC, MB96F348TWC, MB96F348CSC, MB96F348HSC, MB96F348TSC, MB96F345DS, MB96F345DW, MB96F345FS, MB96F345FW


MB96F355RWA, MB96F355YWA, MB96F355RSA, MB96F355YSA

MB96370 series MB96F378RWA, MB96F378YWA, MB96F378RSA, MB96F378YSA, MB96F379RWA, MB96F379YWA, MB96F379RSA, MB96F379YSA,

MB96380 series MB96F386RWA, MB96F386YWA, MB96F386RSA, MB96F386YSA, MB96F387RWA, MB96F387YWA, MB96F387RSA, MB96F387YSA, MB96F386RWB, MB96F386YWB, MB96F386RSB, MB96F386YSB, MB96F387RWB, MB96F387YWB, MB96F387RSB, MB96F387YSB, MB96384RWA, MB96384YWA, MB96384RSA, MB96384YSA, MB96385RWA, MB96385YWA, MB96385RSA, MB96385YSA, MB96F388RWA, MB96F388YWA, MB96F388RSA, MB96F388YSA, MB96F389RWA, MB96F389YWA, MB96F389RSA, MB96F389YSA,

Evaluation chip MB96V300B, MB96V300



3. Details of the Failure

3.1. The timing of the clearing the interrupt causing of LIN-USART and RTC We identified the delay of one or two peripheral clock (CLKP1) by the time interrupt cause bit of LIN-USART and RTC in Table2 was actually cleared. Therefore, when the ratio of dividing frequency of CPU clock (CLKB) and CLKP1 is 1:16, 32хCPU clock is delayed at RTC, 16хCPU clock is delayed at LIN-USART in the maximum by the time interrupt cause bit is cleared. So, actually, it will transit to the interruption routine again when returning from the interruption routine before the interrupt cause bit is cleared.

This limitation is not concerned, because the interrupt cause bit is cleared within the read or write cycle of the instruction about the LIN-USART register, the bit and other resource in table3.

3.2 Content of specification limitation When the interrupt cause bit of LIN-USART and RTC in table2 is cleared, actually, to wait for the interrupt cause bit to be cleared, return from the interruption routine after dummy reading once the resource register connected with the peripheral bus1.

Resource Register Bit Delay

[CLKP1 cycle]

Comment

SSRx RDRF 1 RDRF is cleared by reading RDRx.

SCRx CRE 1 Bit that clears error flag (PE,ORE,FRE)

LIN-USART

SMRx UPCL or SRST

1 Reset bit of LIN-USART that clears all flags (TDRE,RDRF,LBD,PE,ORE,FRE)

WTCER INT4 2 0.5 second interrupt cause bit

WTCRH INT3 2 1day interrupt cause bit

WTCRH INT2 2 1hour interrupt cause bit

WTCRH INT1 2 1minute interrupt cause bit

RTC

WTCRH INT0 2 1second interrupt cause bit

Resource Register Bit Comment

SSRx TDRF TDRF of SSRx is cleared by writing the value in TDRx.

LIN-USART

ESCRx LBD Interrupt cause bit by SYNC BREAK generation of LIN



There is no problem when used by either of the following methods.

• It returns from the interruption routine after it accesses(read or write) the register of resource connected with peripheral bus 1 after clear processing of the concerned interruption cause at least once.

• For LIN-USART, it returns from the interruption routine after CLKP1/CLKB (dividing frequency ratio) [CPU clock cycle] or more passes after clear processing of the concerned interruption cause.

• For RTC, it returns from the interruption routine after 2хCLKP1/CLKB (dividing frequency ratio) [CPU clock cycle] or more passes after clear processing of the concerned interruption cause.



4. Example of interruption cause clear method for LIN-USART and RTC We show the example of the clear method of the interrupt cause bit of LIN-USART and RTC concerning this limitation as follows.

4.1. RDRF bit of SSRx register

(Example) __interrupt void IRQHandler (void) { volatile unsigned char tmp ;

rdbuf = UARTx_RDRx; /* Read RDRx register */ tmp = UARTx_SSRx; /* dummy read access */

/* interrupt service code */ }

4.2. CRE bit of SCRx register

(Example) __interrupt void IRQHandler (void) {

volatile unsigned char tmp ; UARTx_SCRx_CRE = 1; /* clear interrupt flag */ tmp = UARTx_SSRx; /* dummy read access */ /* interrupt service code */

}

4.3. UPCL bit of SMRx register


volatile unsigned char tmp ; UARTx_SMRx_UPCL = 1; /* clear interrupt flag */ tmp = UARTx_SSRx; /* dummy read access */ /* interrupt service code */

}



4.4. INT4 bit of WTCER register


volatile unsigned char tmp ; WTCER_INT4 = 0; /* clear interrupt flag */ tmp = WTCER; /* dummy read access */ /* interrupt service code */

}

4.5. INT3-0 bit of WTCRH register


volatile unsigned char tmp ; WTCRH_INT3 = 0; /* clear interrupt flag */

or WTCRH_INT2 = 0; /* clear interrupt flag */

or WTCRH_INT1 = 0; /* clear interrupt flag */

or WTCRH_INT0 = 0; /* clear interrupt flag */ tmp = WTCRH; /* dummy read access */ /* interrupt service code */

}

5. References This customer information relates to the FJ document 16FX_MB963XX_repotr_E_2008323 with the same content.


Limitation when using LCD segment 33

Chapter 0


MB96370/MB96380/MB96390 SERIES





16.10.08 V1.0; PKu; Initial Version


Abbreviations:


MCU Microcontroller


Chapter 0



Chapter 0 16FXFL0044: Limitation when using LCD segment 33


16FXFL0044: Limitation when using LCD segment 33

1. Problem Description We found a problem when using LCD segment 33 without LCD segment 32 being enabled. On devices of the MB96370, MB96380 and MB96390 series the segment enable for LCD segment 32 (LCDER4:SEG32) also influences the data output of the LCD Controller Display RAM for segment 33 (VRAM16:DH[3:0]).

2. Affected Devices Series Product name

MB96370 series MB96F378HSA, MB96F378HWA, MB96F378TSA, MB96F378TWA, MB96F379RSA, MB96F379RWA, MB96F379YSA, MB96F379YWA

MB96380 series MB96384RSA, MB96384RSB, MB96384RWA, MB96384RWB, MB96384YSA, MB96384YSB, MB96384YWA, MB96384YWB, MB96385RSA, MB96385RSB, MB96385RWA, MB96385RWB, MB96385YSA, MB96385YSB, MB96385YWA, MB96385YWB, MB96F385RSA, MB96F385RWA, MB96F385YSA, MB96F385YWA, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB, MB96F388HSA, MB96F388HWA, MB96F388TSA, MB96F388TWA, MB96F389RSA, MB96F389RWA, MB96F389YSA, MB96F389YWA

MB96390 series MB96F395RSA, MB96F395RWA, MB96F395YSA, MB96F395YWA

Evaluation chip MB96V300, MB96V300B when emulating devices of MB96370, MB96380 and MB96390 series




3. Detailed explanation If LCD segment 32 is not enabled by writing ‘1’ to LCDER4:SEG32 the data from the LCD Controller Display RAM for segment 33 in VRAM16:DH[3:0] are not output on the SEG33 pin (P02_5) of the affected device, even if LCD segment 33 is enabled by writing ‘1’ to LCDER:SEG33. Instead the outputted data from VRAM16:DH[3:0] to SEG33 is always ‘0’.

LCDER4: SEG33

LCDER4: SEG32

Port number Expected behaviour Actual behaviour (Bug)

P02_4/SEG32 GPP/Other resource GPP/Other resource 0 0

P02_5/SEG33 GPP/Other resource GPP/Other resource

P02_4/SEG32 SEG32 Output SEG32 Output 0 1

P02_5/SEG33 GPP/Other resource GPP/Other resource

P02_4/SEG32 GPP/Other resource GPP/Other resource 1 0

P02_5/SEG33 SEG33 Output SEG33 output (wrong value)

P02_4/SEG32 SEG32 Output SEG32 Output 1 1

P02_5/SEG33 SEG33 Output SEG33 Output




4. Workaround Depending on the application there might be the following workarounds:

a) If LCD segment 32 is used in the application and thus LCDER4:SEG32 is ‘1’, there is no limitation and no workaround required.

b) If LCD segment 32 is not used in the application, but none of the digital functions1 on the SEG32 pin (P02_4) is used LCDER4:SEG32 can be set to ‘1’ as workaround.

c) If it is not possible to enable LCD segment 32 as described in a) and b) segment 33 can not be used.

P02_5/SEG33 P02_4/SEG32 MB96370, MB96380 series MB96390 series

LCDER4:SEG32 bit=0 LCDER4:SEG32 bit : don’t care Use as a non LCD port

Use as a non LCD port LCDER4:SEG33 bit=0 LCDER4:SEG33 bit=0

LCDER4:SEG32 bit=1 LCDER4:SEG32 bit : don’t care Use as a non LCD port

Use as a LCD port LCDER4:SEG33 bit=0 LCDER4:SEG33 bit=0

LCDER4:SEG32 bit=0 LCDER4:SEG32 bit=1 Use as a LCD port

Use as a non LCD port SEG33 port doesn’t output

correct value LCDER4:SEG33 bit=1

LCDER4:SEG32 bit=1 LCDER4:SEG32 bit=1 Use as a LCD port

Use as a LCD port LCDER4:SEG33 bit=1 LCDER4:SEG33 bit=1

5. Corrective action by Fujitsu Future MCUs will not have this limitation.

1 e.g. P02_4 General Purpose Port input or output, relocated Sound Generator 0 amplitude output, External Bus address data 12 input or output



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USB: STALL response release specification limitation of enpoint0




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Revision History

Version Date Remark 1 2008-23-09 Initial version (SN) 2 2008-11-26 Added MB96F338UWA, MB96F336USA, MB96F336UWA


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16FXFL0045: USB: STALL response release specification limitation of endpoint0

1. Description of functional limitation This USB function was developed based on the USB 1.1 standard before the USB 2.0 standard was released. Therefore, the following specification limitation is found which has not been specified by the USB 1.1 standard.

For a device which does not support the newly added commands for High speed of USB 2.0 a STALL response is required for these commands. Therefore, even at normal communication, the STALL response might be required. It is necessary to clear the STAL bit (i.e EP0C: STAL) within a fixed time after detecting STALL response.

2. List of affected Devices MB96F336USA, MB96F336UWA, MB96F338USA, MB96F338UWA

3. Detailed explanation STALL response and release procedures for Endpoint0 are executed with STAL bit of EP0

Control Register (EP0C).

For STALL response, interpret the command after detecting UDCS: SETP bit equal to "1" in the Interrupt Service Routine (EP0OS: DRQ0 bit = 1 for interrupt) that indicates the set-up stage of control transfer. After setting EP0C: STAL bit, clear the interrupt cause bit (EP0OS:DRQ0).

For STALL release, clear the EP0C: STAL bit after detecting UDCS: SETP bit equal to "1" in the Interrupt Service Routine (EP0OS: DRQO bit = 1 for interrupt). (See Figure 1)


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Figure 1. STAL Bit Clear Timing

4. Possible workaround For STALL response release (STAL bit clear), clear EP0C: STAL bit in the period between

the time when UDCS: SETP bit equal to "1" (EP0OS: DRQ0 bit= 1 for interrupt) is detected and the time when the data packet transmission/reception of the next data stage has started. When EP0C: STAL bit is not cleared in the following period, execute STALL response with the handshake of data stage.

The period between the time when EP0OS: DRQ0 BIT of "1" is detected and the time when EP0C: STAL bit is cleared. (Transfer speed: at Full speed of 12Mbps):

Within idle time + 2.75 us

* When idle time is 2-bit transfer time (shortest period), the above period is within 2.9 us.

If the EP0C: STAL bit clear cannot be executed within the above period, take an appropriate countermeasure such as lengthening of the idle time with the USB host driver.


SETP bit


USB: specification limitation on isochronous transfer




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Revision History

Version Date Remark 1 2008-23-09 Initial version (SN) 2 2008-11-27 Added MB96F338UWA, MB96F336USA, MB96F336UWA


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16FXFL0046: USB: Specification of limitation on isochronous transfer

1. Description of functional limitation This USB function was developed based on the USB 1.1 standard before the USB 2.0 standard was released. Therefore, the following specification limitation is found which has not been specified by the USB 1.1 standard. In the isochronous transfer of USB 2.0, the item which specifies the initial settings where Alternate value is 0 and the number of maximum packets is 0 was added to the specification. In this USB function, STALL response is automatically given to the host when Alternate value is tried to set to a value other than 0 with the Alternate interface setting command (SetInterface) from the host. Therefore, the Alternate value cannot be changed. So, the number of maximum packets cannot be changed with the Alternate value.

2. List of affected Devices MB96F336USA, MB96F336UWA, MB96F338USA, MB96F338UWA

3. Detailed explanation

Interface descriptors have a bInterfaceNumber field specifying the Interface number and a bAlternateSetting which allows an interface to change settings on the fly. For example we could have a device with two interfaces, interface one and interface two. Interface one has bInterfaceNumber set to zero indicating it is the first interface descriptor and a bAlternativeSetting of zero. Interface two would have a bInterfaceNumber set to one indicating it is the second interface and a bAlternativeSetting of zero (default). We could then throw in another descriptor, also with a bInterfaceNumber set to one indicating it is the second interface, but this time setting the bAlternativeSetting to one, indicating this interface descriptor can be an alternative setting to that of the other interface descriptor two. When this configuration is enabled, the first two interface descriptors with bAlternativeSettings equal to zero is used. However during operation the host can send a SetInterface request directed to that of Interface one with an alternative setting of one to enable the other interface descriptor. As this USB function was designed according to the USB 1.1 standard, it will send a STALL response if the host tries to set bAlternateInterface setting to some other value than 0 with SetInterface command.


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5. Fujitsu countermeasure None.

16-bit MICROCONTROLLER MB96300 SERIES

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