16-BIT MICROCONTROLLER MB90980 Series HARDWARE …i PREFACE Purpose of This Manual and Intenders...

FUJITSU SEMICONDUCTORCONTROLLER MANUAL

F2MC-16LX16-BIT MICROCONTROLLER

MB90980 SeriesHARDWARE MANUAL

CM44-10138-2E

F2MC-16LX16-BIT MICROCONTROLLER

MB90980 SeriesHARDWARE MANUAL

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.

Be sure to refer to the “Check Sheet” for the latest cautions on development.

FUJITSU LIMITED

PREFACE

■ Purpose of This Manual and IntendersThank you very much for purchasing FUJITSU products.

MB90980 series is a 16-bit microcontroller designed for applications such as consumer devices requiring

high-speed real-time processing. MB90980 series functions are suitable for controlling PHS, cellular

phones, CD-ROMs, and VTRs.

This manual, intended for engineers developing products using the MB90980 series, explains the MB90980

series functions and operations. Read this manual first, before using the product.

For details on the instructions, refer to the "Instruction Manual".

Note: F2MC is the abbreviation of FUJITSU Flexible MIcrocontroller.

■ TrademarksThe company names and brand names herein are the trademarks or registered trademarks of their respective

owners.

■ License

Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these

components in an I2C system provided that the system conforms to the I2C Standard Specification as

defined by Philips.

■ Composition of This ManualThis manual consists of the following 26 chapters and an appendix.

CHAPTER 1 OVERVIEW OF MB90980 SERIES

This chapter gives an overview of MB90980 series, including its basic characteristics, block diagram,

and its functions.

CHAPTER 2 HANDLING THE DEVICE

This chapter provides precautions on handling the device.

CHAPTER 3 CPU

This chapter explains CPU specifications, memory, and the functions of registers to provide readers

with a better understanding of the MB90980 functions.

CHAPTER 4 INTERRUPT

This chapter explains interrupts and direct memory access (DMA).

CHAPTER 5 RESET

This chapter explains reset for the MB90980 series.

CHAPTER 6 CLOCKS

This chapter describes the clocks of the MB90980 series.

CHAPTER 7 LOW-POWER CONSUMPTION MODE

This chapter explains the low-power consumption mode of the MB90980 series.

CHAPTER 8 MEMORY ACCESS MODE

This chapter explains memory access mode and its operation.

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CHAPTER 9 I/O PORT

This chapter shows the configuration and explains the functions of the registers used for the I/O port.

CHAPTER 10 TIME-BASE TIMER

This chapter explains the function and operation of the time-base timer.

CHAPTER 11 WATCHDOG TIMER

This chapter describes the operation and function of the watchdog timer.

CHAPTER 12 WATCH TIMER

This chapter has an overview of the watch timer, describes the configuration and functions of the

register, and explains the operation of the watch timer.

CHAPTER 13 16-BIT INPUT/OUTPUT TIMER

This chapter has an overview of the 16-bit input/output timer, describes the configuration and function

of its register, and explains its operation.

CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER

This chapter has an overview of the 8/16-bit up/down counter/timer, describes the configuration and

functions of its registers, and explains its operation.

CHAPTER 15 16-BIT RELOAD TIMER

This chapter provides an overview of the 16-bit reload timer and its operation and explains the

configuration and functions of its registers.

CHAPTER 16 8/16-BIT PPG TIMER

This chapter provides an overview and interrupt of the 8/16-bit PPG timer and its operation and

explains the configuration and functions of its registers.

CHAPTER 17 DTP/EXTERNAL INTERRUPTS

This chapter provides an overview of the DTP/external interrupt, its operation, and notes on usage and


CHAPTER 18 8/10-BIT A/D CONVERTER

This chapter provides an overview of the 8/10-bit A/D converter, configuration and function of its

registers, operation, conversion data protection function, and precautions on use.

CHAPTER 19 EXPANDED I/O SERIAL INTERFACE

This chapter provides an overview, configuration, interrupt, and operation of the expanded I/O serial

interface and explains the configuration and functions of its registers.

CHAPTER 20 UART

This chapter provides an overview, configuration, interrupt, operation, precautions on use, and program

example of the UART and explains the configuration and functions of its registers.

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION

This chapter explains the overview of the address match detection function, its block diagram,

configuration of its register, its operation, and its sample program.

CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE

This chapter describes the overview of the ROM mirror function selection module and its register.

CHAPTER 23 1.5M BIT FLASH MEMORY

This chapter describes the functions and operations of the 1.5M bit flash memory.

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CHAPTER 24 EXAMPLES OF MB90F983 SERIAL PROGRAMMING CONNECTION

This chapter shows an example of a serial programming connection using the AF220/AF210/AF120/

AF110 flash microcontroller programmer by Yokogawa Digital Computer Corporation.

CHAPTER 25 PWC TIMER

This chapter provides an overview of the PWC timer, provides notes on its use, explains its

configuration, explains the configuration and functions of its registers, and explains its interrupt and

operation.

CHAPTER 26 I2C INTERFACE

This chapter provides an overview, configuration, interrupt, and operation of the I2C interface and


APPENDIX

The appendix provides the memory map and lists the instructions used in the F2MC-16LX.

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Copyright © 2007 FUJITSU LIMITED All rights reserved

• The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presented solely for thepurpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrantproper operation of the device with respect to use based on such information. When you develop equipment incorporating thedevice based on such information, you must assume any responsibility arising out of such use of the information. FUJITSUassumes no liability for any damages whatsoever arising out of the use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as licenseof the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or anythird party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using suchinformation. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third partieswhich would result from the use of information contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for general use, includingwithout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developedand manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical lifesupport system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersiblerepeater and artificial satellite).Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connectionwith above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from suchfailures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, andprevention of over-current levels and other abnormal operating conditions.

• If any products described in this document represent goods or technologies subject to certain restrictions on export under theForeign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for exportof those products from Japan.

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CONTENTS

CHAPTER 1 OVERVIEW OF MB90980 SERIES .............................................................. 11.1 Overview of MB90980 Series ............................................................................................................. 21.2 Block Diagram of MB90980 Series ..................................................................................................... 51.3 Package Dimensions .......................................................................................................................... 61.4 Pin Assignment ................................................................................................................................... 71.5 Pin Functions ...................................................................................................................................... 81.6 I/O Circuit Type ................................................................................................................................. 11

CHAPTER 2 HANDLING THE DEVICE .......................................................................... 152.1 Precautions on Handling the Device ................................................................................................. 16

CHAPTER 3 CPU ............................................................................................................ 193.1 Overview of CPU Specifications ....................................................................................................... 203.2 Memory Space .................................................................................................................................. 213.3 CPU Registers .................................................................................................................................. 25

3.3.1 Accumulator (A) ........................................................................................................................... 273.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... 283.3.3 Processor Status (PS) ................................................................................................................. 293.3.4 Program Counter (PC) ................................................................................................................. 323.3.5 Program Count Bank Register (PCB) .......................................................................................... 333.3.6 Direct Page Register (DPR) ........................................................................................................ 343.3.7 General-Purpose Register (Register Bank) ................................................................................. 35

3.4 Prefix Codes ..................................................................................................................................... 36

CHAPTER 4 INTERRUPT ............................................................................................... 394.1 Overview of Interrupt ........................................................................................................................ 404.2 Interrupt Factor and Interrupt Vector ................................................................................................ 424.3 Interrupt Control Register and Peripheral Function .......................................................................... 45

4.3.1 Interrupt Control Register (ICR00 to ICR15) ............................................................................... 464.4 Hardware Interrupt ............................................................................................................................ 49

4.4.1 Hardware Interrupt Operation ...................................................................................................... 524.4.2 Flow of Hardware Interrupt Operation ......................................................................................... 544.4.3 Procedure for Using Hardware Interrupt ...................................................................................... 554.4.4 Multiple Interrupts ........................................................................................................................ 574.4.5 Hardware Interrupt Processing Time ........................................................................................... 59

4.5 Software Interrupt ............................................................................................................................. 614.6 Interrupt by µDMAC .......................................................................................................................... 63

4.6.1 DMA Descriptor ........................................................................................................................... 664.6.2 Individual Registers of DMA Descriptor ....................................................................................... 684.6.3 µDMAC Processing Procedure .................................................................................................... 714.6.4 µDMAC Processing Time ............................................................................................................ 72

4.7 Interrupt by Extended Intelligent I/O Service (EI2OS) ....................................................................... 74

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4.7.1 EI2OS descriptor (ISD) ................................................................................................................ 764.7.2 Each Register of EI2OS Descriptor (ISD) .................................................................................... 784.7.3 Operation of EI2OS ...................................................................................................................... 814.7.4 Procedure for Use of EI2OS ........................................................................................................ 824.7.5 Processing Time of the Extended Intelligent I/O Service (EI2OS) ............................................... 83

4.8 Exception Processing Interrupt ......................................................................................................... 854.9 Stack Operation of Interrupt Processing ........................................................................................... 864.10 Sample Program of Interrupt Processing .......................................................................................... 884.11 Delay Interrupt Generation Module ................................................................................................... 89

4.11.1 Operation of Delay Interrupt Generation Module ......................................................................... 90

CHAPTER 5 RESET ........................................................................................................ 915.1 Overview of Reset ............................................................................................................................ 925.2 Reset Factors and Oscillation Stabilization Wait Time ..................................................................... 945.3 External-Reset Pin ............................................................................................................................ 965.4 Resetting ........................................................................................................................................... 975.5 Reset-Factor Bits .............................................................................................................................. 995.6 Condition of Pins as Result of Reset .............................................................................................. 101

CHAPTER 6 CLOCKS ................................................................................................... 1036.1 Overview of Clocks ......................................................................................................................... 1046.2 Block Diagram of Clock Generator ................................................................................................. 1066.3 Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) ......................... 1086.4 Clock Modes ................................................................................................................................... 1136.5 Oscillation Stabilization Wait Time .................................................................................................. 1176.6 Connecting Oscillator to External Clock ......................................................................................... 118

CHAPTER 7 LOW-POWER CONSUMPTION MODE ................................................... 1197.1 Overview of Low-Power Consumption Mode .................................................................................. 1207.2 Block Diagram of Low-Power Consumption Control Circuit ........................................................... 1237.3 Low-Power Consumption Mode Control Register (LPMCR) ........................................................... 1257.4 CPU Intermittent Operation Mode .................................................................................................. 1287.5 Standby Mode ................................................................................................................................. 129

7.5.1 Sleep Mode ............................................................................................................................... 1307.5.2 Time-base Timer Mode ............................................................................................................. 1327.5.3 Watch Mode .............................................................................................................................. 1347.5.4 Stop Mode ................................................................................................................................. 136

7.6 State Transition Diagram ................................................................................................................ 1387.7 Pin State in Standby Mode, Hold, and Reset ................................................................................. 1407.8 Caution on Using Low-Power Consumption Mode ......................................................................... 141

CHAPTER 8 MEMORY ACCESS MODE ...................................................................... 1458.1 Overview of Memory Access Mode ................................................................................................ 1468.2 Mode Pins (MD2 to MD0) ............................................................................................................... 1478.3 Mode Data ...................................................................................................................................... 148

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CHAPTER 9 I/O PORT .................................................................................................. 1519.1 Functions of I/O Port ....................................................................................................................... 1529.2 Registers for I/O Port ...................................................................................................................... 153

9.2.1 Port registers (PDR2 to PDR4, PDR6 to PDRA) ....................................................................... 1549.2.2 Port direction registers (DDR2 to DDR4, DDR6 to DDRA) ........................................................ 1559.2.3 Other registers ........................................................................................................................... 156

CHAPTER 10 TIME-BASE TIMER .................................................................................. 15910.1 Overview of Time-base Timer ......................................................................................................... 16010.2 Time-base Timer Configuration ...................................................................................................... 16210.3 Time-base Timer Control Register (TBTC) ..................................................................................... 16410.4 Time-base Timer Interrupt .............................................................................................................. 16610.5 Time-base Timer Operation ............................................................................................................ 16710.6 Notes on Using Time-base Timer ................................................................................................... 17010.7 Sample Programs of Time-base timer ............................................................................................ 171

CHAPTER 11 WATCHDOG TIMER ................................................................................ 17311.1 Overview of Watchdog Timer ......................................................................................................... 17411.2 Watchdog Timer Control Register (WDTC) .................................................................................... 17611.3 Watchdog Timer Configuration ....................................................................................................... 17811.4 Watchdog Timer Operation ............................................................................................................. 18011.5 Notes on Using Watchdog Timer .................................................................................................... 18211.6 Sample Programs of Watchdog Timer ............................................................................................ 183

CHAPTER 12 WATCH TIMER ........................................................................................ 18512.1 Overview of Watch Timer ............................................................................................................... 18612.2 Watch Timer Configuration ............................................................................................................. 18712.3 Watch Timer Control Register (WTC) ............................................................................................. 18812.4 Watch Timer Operation ................................................................................................................... 190

CHAPTER 13 16-BIT INPUT/OUTPUT TIMER ............................................................... 19313.1 Overview of 16-bit Input/Output Timer ............................................................................................ 19413.2 Configuration of 16-bit Input/Output Timer ..................................................................................... 19513.3 Configuration and Function of 16-bit Input/Output Timer Register ................................................. 199

13.3.1 Free-run timer ............................................................................................................................ 20013.3.2 Output compare ......................................................................................................................... 20513.3.3 Input capture .............................................................................................................................. 209

13.4 Interrupt of 16-bit Input/Output Timer ............................................................................................. 21113.5 16-bit Input/Output Timer Operation ............................................................................................... 213

13.5.1 Operation of free-run timer ........................................................................................................ 21413.5.2 Operation of output compare ..................................................................................................... 21613.5.3 Operation of input capture ......................................................................................................... 21813.5.4 Free-run timer timing ................................................................................................................. 21913.5.5 Output compare timing .............................................................................................................. 22013.5.6 Timing of input capture .............................................................................................................. 221

13.6 Program Example of 16-bit Input/Output Timer .............................................................................. 222

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CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 23514.1 Overview of 8/16-bit Up/Down Counter Timer ................................................................................ 23614.2 Configuration of 8/16-bit Up/Down Counter/Timer .......................................................................... 23714.3 Configuration and Functions of Registers for 8/16-bit Up/Down Counter/Timer ............................. 240

14.3.1 Counter Control Register (ch.0) Upper (CCRH0) ...................................................................... 24114.3.2 Counter Control Register (ch.1) Upper (CCRH1) ...................................................................... 24314.3.3 Counter Control Register (ch.0/ch.1) Lower (CCRL0/CCRL1) .................................................. 24514.3.4 Counter Status Register 0/1 (CSR0/CSR1) ............................................................................... 24714.3.5 Up/Down Count Register (ch.0/ch.1) (UDCR0/UDCR1) ............................................................ 24914.3.6 Reload/Compare Register (ch.0/ch.1) (RCR0/RCR1) ............................................................... 250

14.4 Interrupt of 8/16-bit Up/Down Counter/Timer .................................................................................. 25114.5 8/16-bit Up/Down Counter/Timer Operation ................................................................................... 253

14.5.1 Reload/Compare Function ......................................................................................................... 25614.5.2 Writing Data to Up/Down Count Register (UDCR) .................................................................... 259

14.6 Program Example of 8/16-bit Up/Down Counter/Timer .................................................................. 261

CHAPTER 15 16-BIT RELOAD TIMER ........................................................................... 26915.1 Overview of 16-Bit Reload Timer .................................................................................................... 27015.2 Configuration and Functions of 16-Bit Reload Timer Registers ...................................................... 274

15.2.1 Timer Control Status Register (TMCSR) ................................................................................... 27515.2.2 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) ................................................. 279

15.3 Interrupt of 16-Bit Reload Timer ..................................................................................................... 28115.4 Operations of the 16-Bit Reload Timer ........................................................................................... 282

15.4.1 State Transitions During Count Operation ................................................................................. 28315.4.2 Operations of Internal Clock Mode (Reload Mode) ................................................................... 28415.4.3 Internal Clock Mode (One-Shot Mode) ...................................................................................... 28715.4.4 Event Count Mode ..................................................................................................................... 290

15.5 Program Example of 16-Bit Reload Timer ...................................................................................... 292

CHAPTER 16 8/16-BIT PPG TIMER ............................................................................... 29916.1 Overview of 8/16-Bit PPG Timer ..................................................................................................... 30016.2 Configuration of 8/16-Bit PPG Timer .............................................................................................. 30116.3 Configuration and Functions of 8/16-Bit PPG Timer Registers ...................................................... 304

16.3.1 PPG0/PPG2 Operation Mode Control Register (PPGC0/PPGC2) ............................................ 30516.3.2 PPG1/PPG3 Operation Mode Control Register (PPGC1/PPGC3) ............................................ 30716.3.3 PPG0 to PPG3 Output Control Registers (PPG01, PPG23) ..................................................... 31016.3.4 Reload Registers (PRLL0 to PRLL3, PRLH0 to PRLH3) .......................................................... 312

16.4 Interrupt of 8/16-Bit PPG Timer ...................................................................................................... 31316.5 Operations of 8/16-Bit PPG Timer .................................................................................................. 31516.6 Program Example of 8/16-Bit PPG Timer ....................................................................................... 321

CHAPTER 17 DTP/EXTERNAL INTERRUPTS .............................................................. 32517.1 Overview of DTP/External Interrupt ................................................................................................ 32617.2 Configuration and Functions of DTP/external Interrupt Registers .................................................. 32817.3 DTP/External Interrupt .................................................................................................................... 33117.4 Operations of DTP/external Interrupt .............................................................................................. 33317.5 Notes on DTP/external Interrupt Usage .......................................................................................... 335

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17.6 Program Example of DTP/External Interrupt .................................................................................. 337

CHAPTER 18 8/10-BIT A/D CONVERTER ..................................................................... 34118.1 Overview of 8/10-Bit A/D Converter ................................................................................................ 34218.2 Configuration of 8/10-Bit A/D Converter ......................................................................................... 34318.3 Configuration of 8/10-Bit A/D Converter Registers ......................................................................... 345

18.3.1 Control Status Register 1 (ADCS1) ........................................................................................... 34618.3.2 Control Status Register 2 (ADCS2) ........................................................................................... 34918.3.3 Data Registers (ADCR2 and ADCR1) ....................................................................................... 352

18.4 Interrupt of 8/10-Bit A/D Converter ................................................................................................. 35318.5 Operations of 8/10-Bit A/D Converter ............................................................................................. 355

18.5.1 Example of µDMAC Start in Single Mode .................................................................................. 35818.5.2 Example of µDMAC Start in Continuous Mode ......................................................................... 36018.5.3 Example of µDMAC Start in Stop Mode .................................................................................... 362

18.6 Conversion Data Protection Function of 8/10-Bit A/D Converter .................................................... 36418.7 Precautions When Using the 8/10-Bit A/D Converter ..................................................................... 36618.8 Program Example of 8/10-Bit A/D Converter .................................................................................. 367

CHAPTER 19 EXPANDED I/O SERIAL INTERFACE .................................................... 37319.1 Overview of Expanded I/O Serial Interface ..................................................................................... 37419.2 Configuration of Expanded I/O Serial Interface .............................................................................. 37519.3 Configuration and Functions of Expanded I/O Serial Interface Registers ...................................... 377

19.3.1 Serial Mode Control Status Register 0/1 (SMCS0/SMCS1) ...................................................... 37819.3.2 Serial Data Register 0/1 (SDR0/SDR1) ..................................................................................... 38219.3.3 Communication Prescaler Control Register 0/1 (SDCR0/SDCR1) ............................................ 383

19.4 Interrupt of Expanded I/O Serial Interface ...................................................................................... 38519.5 Operation of Expanded I/O Serial Interface .................................................................................... 387

19.5.1 Shift Clock Modes ...................................................................................................................... 38819.5.2 Operational States of Serial I/O Units ........................................................................................ 38919.5.3 Start/Stop Timing and Input/Output Timing of Shift Operation .................................................. 39119.5.4 Interrupt Function ...................................................................................................................... 393

19.6 Program Example of Expanded I/O Serial Interface ....................................................................... 394

CHAPTER 20 UART ........................................................................................................ 39720.1 Overview of the UART .................................................................................................................... 39820.2 Configuration of UART .................................................................................................................... 39920.3 Configuration and Functions of UART Registers ............................................................................ 401

20.3.1 Serial Mode Register (SMR) ...................................................................................................... 40220.3.2 Serial Control Register (SCR) ................................................................................................... 40420.3.3 Serial Input/Output Register (SIDR/SODR) ............................................................................... 40720.3.4 Serial Status Register (SSR) ..................................................................................................... 40820.3.5 Communication Prescaler Control Register (CDCR) ................................................................. 411

20.4 Interrupt of UART ............................................................................................................................ 41320.5 UART Operations ........................................................................................................................... 415

20.5.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) ................................................. 42020.5.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 42320.5.3 Two-Way Communication Function (Normal Mode) .................................................................. 425

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20.5.4 Master/Slave Communication Function (Multiprocessor Mode) ................................................ 42720.6 Precautions on Using the UART ..................................................................................................... 43120.7 Program Example of UART ............................................................................................................ 432

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ......................................... 44121.1 Overview of Address Match Detection Function ............................................................................. 44221.2 Block Diagram of Address Match Detection Function .................................................................... 44321.3 Configuration of Registers for Address Match Detection Function ................................................. 444

21.3.1 Program Address Detection Control Status Register (PACSR) ................................................ 44521.3.2 Program Address Detection Registers (PADR0, PADR1) ......................................................... 447

21.4 Explanation of Operation of Address Match Detection Function .................................................... 44921.4.1 Example of using Address Match Detection Function ............................................................... 450

21.5 Program Example of Address Match Detection Function ............................................................... 455

CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ................................ 45722.1 Overview of ROM Mirror Function Selection Module ...................................................................... 45822.2 ROM Mirror Function Selection Register (ROMM) ......................................................................... 459

CHAPTER 23 1.5M BIT FLASH MEMORY ..................................................................... 46123.1 Overview of 1.5M Bit Flash Memory ............................................................................................... 46223.2 Sector Configuration of 1.5M Bit Flash Memory ............................................................................. 46423.3 Flash Memory Control Status Register (FMCS) ............................................................................. 46523.4 Method for Starting the Flash Memory's Automatic Algorithm ........................................................ 47223.5 Verifying the Execution State of the Automatic Algorithm .............................................................. 473

23.5.1 Data Polling Flag (DQ7) ............................................................................................................ 47423.5.2 Toggle Bit Flag (DQ6) ................................................................................................................ 47623.5.3 Timing Limit Excess Flag (DQ5) ................................................................................................ 47723.5.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 478

23.6 Flash Memory Write/Erase Operations ........................................................................................... 47923.6.1 Setting the Flash Memory to Read/Reset State ........................................................................ 48023.6.2 Writing Data to Flash Memory ................................................................................................... 48123.6.3 Erasing All Data in the Flash Memory (Chip Erase) .................................................................. 48323.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) ........................................................... 48423.6.5 Suspending Sector Erasure for the Flash Memory .................................................................... 48623.6.6 Resuming the Sector Erasure of Flash Memory ........................................................................ 487

CHAPTER 24 EXAMPLES OF MB90F983 SERIAL PROGRAMMING CONNECTION .......................................................................................... 489

24.1 Basic Configuration of Serial Programming Connection with MB90F983 ....................................... 49024.2 Example of Connection in Single-Chip Mode (When Using the User Power Supply) .................... 49324.3 Example of Connection with Flash Microcontroller Programmer

(When Using the User Power Supply) ............................................................................................ 495

CHAPTER 25 PWC TIMER ............................................................................................. 49725.1 Overview of PWC Timer ................................................................................................................. 49825.2 Configuration of PWC Timer ........................................................................................................... 49925.3 Configuration and Functions of PWC Timer Registers ................................................................... 501

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25.3.1 PWC Control/Status Register (PWCSR0, PWCSR1) ................................................................ 50225.3.2 PWC Data Buffer Register (PWCR0, PWCR1) ......................................................................... 50725.3.3 Divide Ratio Control Register (DIVR0, DIVR1) .......................................................................... 509

25.4 Interrupt of PWC Timer ................................................................................................................... 51025.5 Operations of PWC Timer ............................................................................................................... 512

25.5.1 Operations of the Timer Function .............................................................................................. 51325.5.2 Operations of the Pulse Width Measurement Function ............................................................. 51425.5.3 Selection of Count Clock and Operation Mode ......................................................................... 51625.5.4 Start and Stop of Timer/Pulse Width Measurement .................................................................. 51825.5.5 Timer Mode Operation ............................................................................................................... 52125.5.6 Operation in Pulse Width Measurement Mode .......................................................................... 524

25.6 Notes on PWC Timer Usage .......................................................................................................... 530

CHAPTER 26 I2C INTERFACE ....................................................................................... 53326.1 Overview of I2C Interface ................................................................................................................ 53426.2 Configuration of I2C Interface ......................................................................................................... 53526.3 Configuration and Functions of I2C Interface Registers ................................................................. 537

26.3.1 Bus Status Register (IBSR) ....................................................................................................... 53926.3.2 Bus Control Register (IBCR) ..................................................................................................... 54126.3.3 Clock Control Register (ICCR) .................................................................................................. 54826.3.4 Address Register (IADR) ........................................................................................................... 55026.3.5 Data Register (IDAR) ................................................................................................................. 551

26.4 Interrupt of I2C Interface ................................................................................................................. 55226.5 I2C Interface Operation ................................................................................................................... 554

APPENDIX ......................................................................................................................... 557APPENDIX A Memory Map ........................................................................................................................ 558APPENDIX B I/O Map ................................................................................................................................ 560APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register ....................................... 568APPENDIX D Instructions ........................................................................................................................... 570

D.1 Instruction Types ............................................................................................................................ 571D.2 Addressing ..................................................................................................................................... 572D.3 Direct Addressing ........................................................................................................................... 574D.4 Indirect Addressing ........................................................................................................................ 580D.5 Execution Cycle Count ................................................................................................................... 588D.6 Effective address field .................................................................................................................... 591D.7 How to Read the Instruction List .................................................................................................... 592D.8 F2MC-16LX Instruction List ............................................................................................................ 595D.9 Instruction Map ............................................................................................................................... 609

INDEX................................................................................................................................... 631

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Main changes in this edition

Page Changes (For details, refer to main body.)

- First edition

xiii

CHAPTER 1OVERVIEW OF MB90980

SERIES

This chapter gives an overview of MB90980 series, including its basic characteristics, block diagram, and its functions.

1.1 Overview of MB90980 Series

1.2 Block Diagram of MB90980 Series

1.3 Package Dimensions

1.4 Pin Assignment

1.5 Pin Functions

1.6 I/O Circuit Type

1


1.1 Overview of MB90980 Series

MB90980 series is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing.

■ MB90980 Series FeaturesThe MB90980 series has the following features:

• Minimum instruction execution time

• 40.0 ns/6.25 MHz oscillation multiplied by 4 (25 MHz/3.3 V ± 0.3 V for internal operation)

• 62.5 ns/4 MHz oscillation multiplied by 4 (16 MHz/3.0 V ± 0.3 V for internal operation)

• PLL clock multiply system

• Maximum memory space: 16 Mbytes

• Instruction system optimized for control applications

• Available data types: bit, byte, word, long word

• Standard addressing modes: 23 types

• Improved high-precision operation using a 32-bit accumulator

• Signed multiply and divide operations, extensive RETI instruction

• Instruction system supporting multitasking in high-level languages (such as C)

• Use of a system stack pointer

• Symmetry of instruction sets and barrel shift instructions

• Improved execution speed: 4-byte queue

• Improved interrupt function (priority is a programmable setting of up to 8 levels): 8 external interrupts

• Data transfer function (µDMAC): maximum of 16 channels

• Built-in ROM: FLASH version: 192 K bytes, MASK version: 128 K bytes

• Built-in RAM: FLASH version: 12 K bytes, MASK version: 10 K bytes

• General-purpose ports: maximum of 48 ports

Output open-drain settings available: 10 ports

• A/D converter (RC step-by-step compare type): 8 channels (resolution: 10 bits; conversion time: 3.68

µs (25 MHz operation))

• UART: 1 channel

• Extensive I/O serial interface (SIO): 2 channels

• 8/16-bit PPG: 2 channels (mode switching function of 8 bits x 4 channels and 16 bits x 2 channels)

2

• 8/16-bit up/down timer: 1 channel (8 bits x 2 channels or 16 bits x 1 channel with mode switching

function)

• 16-bit reload timer: 1 channel

• 16-bit input/output timer (input capture x 2 channels; output compare x 4 channels; free-run timer x 1

channel)

• Built-in dual-system clock generator

• Power-saving mode (stop mode, sleep mode, CPU intermittent operation mode, watch mode/time-base

timer mode)

• Package: LQFP64

• CMOS technology

• 3V single power supply (some port can be operated on 5V power supply.)

• I2C interface* 1 channel

P77 and P76 are N-ch open drain pins (without P-ch).

• 16bit PWC: 2 channels

2 channels have the function of input compare.

* : I2C license

Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these

components in an I2C system provided that the system conforms to the I2C Standard Specification as

defined by Philips.

■ Product ConfigurationTable 1.1-1 is an outline of the MB90980 series product configuration.

Table 1.1-1 MB90980 Series Product Configuration

MB90V485B MB90F983 MB90982

ROM capacity - FLASH 192K bytes 128K bytes

RAM capacity 16K bytes 12K bytes 10K bytes

Description

EVA product f=25MHz

3-V/5-V power supply*2

built-in PWC, I2C*4

FLASH product f=25MHz


built-in PWC, I2C*4

MASK product f=25MHz


built-in PWC, I2C*4

Emulator dedicated

power supply*1Yes No No

*1: The setting of the jumper switch (TOOL VCC) when using the emulator (MB2147-01).For detailed information, refer to MB2147-01 or MB2147-20 Hardware Manual (switching of 3.3 emulator dedicated power supply).

*2: 3-V/5-V: I/F Pin : P20 to P27, P30 to P37, P40 to P47 and P70 to P77. The other pins are for 3-V power supply.

*3: 3-V/5-V: I/F pins (P24 to P27, P30 to P37, P40 to P42, P70 to P74, and P76 to P77) The power supply for the other pins is 3 V.

*4: If I2C is set, P76/P77 pins are N-ch open drain pin (without P-ch).

3


■ The Packages of the Corresponding Products

● Package

Table 1.1-2 shows the differences of the package.

❍: Usable✕: Unusable

● Memory area

Refer to the memory map in appendix for the differences of memory area.

● Current dissipation

Refer to "Electrical Characteristics" in Data Sheet for the differences of the current dissipation.

Table 1.1-2 Product List of MB90980 Series

MB90V485B MB90F983 MB90982

FPT-64P-M03 ✕ ❍ ❍

PGA-299C ❍ ✕ ✕

4

1.2 Block Diagram of MB90980 Series

This section has a block diagram of the MB90980 series.

■ Block Diagram of MB90980 SeriesFigure 1.2-1 is a block diagram of the MB90980 series.

Figure 1.2-1 Block Diagram of MB90980 Series

Note:

In the Figure 1.2-1, the I/O port shares a pin with each built-in function block. The pin cannot be usedas an I/O port if it is used as built-in module pin.

RAM

ROM

8

2

222

8

X0, X1, RSTX0A, X1AMD2, MD1, MD0

SIN0SOT0SCK0

SIN1, SIN2SOT1, SOT 2SCK1, SCK2

AVCCAVRHAVSSADTGAN0 to AN7

AIN0, AIN1BIN0, BIN1ZIN0, ZIN1

PPG0, PPG1

PPG2, PPG3

4 8 3 8 5 2 8 4 2

P24

P07

P30

P37

P40

P42

P60

P67

P70

P74

P76,P77

P80

P87

P90

P93

P96,P97

4

PA0

PA3

IN0, IN1

OUT0, OUT1,OUT2, OUT3

TIN0TOT0

IRQ0 to IRQ78

SCLSDA

PWC0

PWC1

Clock controlCircuit

CPUF2MC16LX core

Interrupt controller

8/16-bit PPG

8/16-bitup/down counter

Input/output timer

16-bit input capture × 2 channels

16-bit output compare × 4 channels16-bit free-run timer

16-bit reload timer

I2C interface

External interrupt

UART

I/O extended serial interface × 2 channels

A/D converter( 10 bits )

PWC × 2 channels

I/O port

to to to to to to to to

Communication prescaler

F2 M

C-1

6LX

Bus

2

2

222

2

4

P40 to P42 (x3): With register for open drain settingsP76/P77 pins of I2C are N-ch open drain terminal (without P-ch)

5


1.3 Package Dimensions

MB90980 series has one type of package.

■ Package Dimensions (LQFP-64)Figure 1.3-1 is a diagram for the package dimensions of the LQFP-64 type.

Figure 1.3-1 Package Dimensions of LQFP-64 Type

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

64-pin plastic LQFP Lead pitch 0.50 mm

Package width ×package length

10.0 × 10.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 0.32g

Code(Reference)

P-LFQFP64-10×10-0.50

64-pin plastic LQFP(FPT-64P-M03)

(FPT-64P-M03)

LEAD No.

Details of "A" part

0.25(.010)

(Stand off)(.004±.004)0.10±0.10

(.024±.006)0.60±0.15

(.020±.008)0.50±0.20

1.50+0.20–0.10

+.008–.004.059

0˚~8˚

"A"

0.08(.003)

(.006±.002)0.145±0.055

0.08(.003) M(.008±.002)0.20±0.050.50(.020)

12.00±0.20(.472±.008)SQ

10.00±0.10(.394±.004)SQ

INDEX

49

64

3348

17

32

161

2003 FUJITSU LIMITED F64009S-c-5-8C

(Mounting height)

*

Dimensions in mm (inches).Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.

6

1.4 Pin Assignment

This section shows the MB90980 series pin assignments.

■ Pin Assignment Diagram (LQFP-64)Figure 1.4-1 is a pin assignment diagram for the LQFP-64 type.

Figure 1.4-1 Pin Assignment Diagram of MB90980 Series (LQFP-64)

12345678910111213141516

VssX1X0MOD2MOD1MOD0P84/IRQ4P85/IRQ5P86/IRQ6P87/IRQ7P90/SIN1P91/SOT1P92/SCK1P93/FRCK/ADTGP96/IN0Vss

48474645444342414039383736353433

AVccAVR

P27/PPG3P26/PPG2P25/PPG1P24/PPG0P37/PWC1P36/PWC0

P35/ZIN1P34/BIN1P33/AIN1P32/ZIN0P31/BIN0P30/AIN0

P42/SCK2Vcc5

Vss

P41

/SO

T2

P40

/SIN

2P

77/S

DA

P76

/SC

LP

74/T

OT

0P

73/T

IN0

P72

/SC

K0

P71

/SO

T0

P70

/SIN

0P

A3/

OU

T3

PA

2/O

UT

2P

A1/

OU

T1

PA

0/O

UT

0P

97/IN

1V

cc3

AV

ssP

60/A

N0

P61

/AN

1P

62/A

N2

P63

/AN

3P

64/A

N4

P65

/AN

5P

66/A

N6

P67

/AN

7P

80/IR

Q0

P81

/IRQ

1P

82/IR

Q2

P83

/IRQ

3R

ST

X0A

X1A

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49LQFP-64P

(TOP VIEW)

- P77 and P76 are N-ch open drain pin (without P-ch).- P24 to P27, P30 to P37, P40 to P42, P70 to P74 and P76, P77 are 3V/5V I/F pin.

7


1.5 Pin Functions

This section explains the MB90980 series pin functions.

■ Pin FunctionsTable 1.5-1 explains MB90980 series pin function.

Table 1.5-1 Pin Functions (1 / 3)

Pin No.Pin name

I/O Circuit Type

Function FPT-64P-M03

46 X0 A Oscillator pin

47 X1 A Oscillator pin

50 X0A A 32 kHz oscillator pin

49 X1A A 32 kHz oscillator pin

51 RST B Reset input pin

3 to 6 P24 to P27 E

(CMOS/H)

These are general purpose I/O port.

PPG0 to PPG3 PPG timer output pins.

14 P30 E

(CMOS/H)

This is a general purpose I/O port.

AIN0 8/16-bit up/down counter input pin (channel 0).

13 P31 E

(CMOS/H)


BIN0 8/16-bit up/down counter input pin (channel 0).

12 P32 E

(CMOS/H)


ZIN0 8/16-bit up/down counter input pin (channel 0).

11 P33 E

(CMOS/H)


AIN1 8/16-bit up/down counter input pin (channel 1).

10 P34 E

(CMOS/H)


BIN1 8/16-bit up/down counter input pin (channel 1).

9 P35 E

(CMOS/H)


ZIN1 8/16-bit up/down counter input pin (channel 1).

7, 8 P36, P37 E

(CMOS/H)

These are general purpose I/O ports.

PWC0, PWC1 These are PWC input pins.

19 P40 G

(CMOS/H)


SIN2 Simple serial I/O 2 input pin.

18 P41 F

(CMOS)


SOT2 Simple serial I/O 2 output pin.

8

15 P42 G

(CMOS/H)


SCK2 Simple serial I/O 2 clock input/output pin.

60 to 63 P60 to P63 H

(CMOS)


AN0 to AN3 These are the analog input pins.

56 to 59 P64 to P67 H

(CMOS)


AN4 to AN7 These are the analog input pins.

26 P70 G

(CMOS/H)


SIN0 This is the UART data input pin.

25 P71 F

(CMOS)


SOT0 This is the UART data output pin.

24 P72 G

(CMOS/H)


SCK0 This is the UART clock I/O pin.

23 P73 G

(CMOS/H)


TIN0 This is the 16-bit reload timer event input pin.

22 P74 F

(CMOS)


TOT0 This is the 16-bit reload timer output pin.

21

P76 I

(NMOS/H)


SCL Serves as the I2C interface clock I/O pin. During operation of the

I2C interface, leave the port output in a high impedance state.

20

P77 I

(NMOS/H)


SDAServes as the I2C interface data I/O pin. During operation of the

I2C interface, leave the port output in a high impedance state.

52 to 55 P80 to P83 E

(CMOS/H)


IRQ0 to IRQ3 External interrupt input pins.

39 to 42 P84 to P87 E

(CMOS/H)


IRQ4 to IRQ7 External interrupt input pins.

38 P90 E

(CMOS/H)


SIN1 Simple serial I/O 1 data input pin.

37 P91 D

(CMOS)


SOT1 Simple serial I/O 1 data output pin.


Pin No.Pin name

I/O Circuit Type


9


36 P92 E

(CMOS/H)


SCK1 Simple serial I/O 1 data input/output pin.

35

P93

E(CMOS/H)


FRCK When the free run timer is in use, this pin functions as the external clock input pin.

ADTG When the A/D converter is in use, this pin functions as the external trigger input pin.

34 P96 E

(CMOS/H)


IN0 Input capture channel 0 trigger input pin.

31 P97 E

(CMOS/H)


IN1 Input capture channel 1 trigger input pin.

27 to 30 PA0 to PA3 D

(CMOS)


OUT0 to OUT3 Output compare event output pins.

1 AVcc ___ A/D converter power supply pin.

2 AVRH ___ A/D converter external reference voltage supply pin.

64 AVss ___ A/D converter power supply pin.

43 to 45 MD0 to MD2 J

(CMOS/H)Operating mode selection input pins.

32 VCC3 ___ 3.3 V ± 0.3 V power supply pins (VCC3).

16 VCC5 ___

3 V/5 V power supply pin.5 V power supply pin when P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 to P77 are used as 5 V I/F pins.Usually, use VCC = VCC3 = VCC5 as a 3 V power supply (when the 3 V power supply is used alone).

17, 48 VSS ___ power supply input pin (GND).


Pin No.Pin name

I/O Circuit Type


10

1.6 I/O Circuit Type

This section explains the I/O circuit type of MB90980 series pins.

■ I/O Circuit TypeTable 1.6-1 summarizes the I/O circuit type of MB90980 series pins.

Table 1.6-1 I/O Circuit Type (1 / 3)

Type Circuit Remarks

A

• Oscillation feedback resistor:• X1, X0: about 1 MΩ• X1A, X0A: about 10 MΩ

• Use of standby control

B

• Hysteresis input with pull-up

C

• Use of input pull-up resistor control• CMOS level input/output

X1,X1A

X0,X0A

Standby control signal

clock input

Hysteresis input

Control

CMOS input

Digital outputP-ch P-ch

N-ch Digital output

11


D

CMOS level input/output

E

• Hysteresis input• CMOS level output

F

• CMOS level input/output• Use of open-drain control

G

• CMOS level output• Hysteresis input• Use of open-drain control



CMOS input

Digital output

Digital outputP-ch

N-ch

CMOS Hysteresis input

Digital output

Digital outputP-ch

N-ch

CMOS input

Open-drain control signal

Digital output

P-ch

N-ch


Open-drain control signal

Digital output

P-ch

N-ch

12

H

• CMOS level input/output• Analog input

I

• Hysteresis input• N-ch open drain output

J

(FLASH product)• CMOS level input• High-voltage control provided for

FLASH test

(Mask product)• CMOS Hysteresis input



CMOS input

Analog input

P-ch

N-ch

Hysteresis input

Digital outputN-ch

Control signal

Mode input

Dispersion resistor

(FLASH product)

N-ch

N-ch

N-ch

N-ch

N-ch


(Mask product)

13


14

CHAPTER 2HANDLING THE DEVICE

This chapter provides precautions on handling the device.

2.1 Precautions on Handling the Device

15


2.1 Precautions on Handling the Device

This section summarizes the precautions on the device’s power supply voltage and pin treatment.

■ Device Handing Precautions

● Preventing Latch-up

Latch-up may occur if voltage higher than VCC or lower than VSS is applied to input and output pins other

or if the power supply for AVCC is applied before VCC or if higher than the maximum rating voltage is

applied between VCC pin and VSS pin.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements.

Be sure to apply the voltage to analog system at the same time of VCC or after turning on the digital power

supply (If power is OFF, turn off the analog system power supply in advance or at the same time).

● Treatment of Unused Pin

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent

damage.

Unused input pins should always be pulled up or down through resistance of at least 2KΩ.

Connect to be AVCC=AVRH=VCC, AVSS=VSS if the A/D converter is not in use.

● Power Supply Pins (VCC pin or VSS pins)

In products with multiple VCC or VSS pins, connect all power supply pins to external power supply and a

ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the VCC and VSS pins of this device at the low

impedance.

It is also advisable to connect a capacitor of approximately 0.1µF between VCC and VSS pins near thisdevice.

● Crystal oscillation circuit

Noise near the X0, X1 pins and X0A, X1A pins may cause the device to malfunction. Design printed

circuit boards so that the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are

located as close to these pins as possible. In addition, design the printed circuit boards so that the wiring of

them does not cross the other wirings as much as possible.

It is also strongly recommended that the printed circuit board artwork surrounds these pins with ground to

promote stable operation.

Please ask the crystal maker to evaluate the oscillation characteristics of the crystal and this device.

16

● Precautions for Use of External Clock

If using an external clock, drive only X0 pin and open X1 pin.

Figure 2.1-1 shows how to use the external clock.

Figure 2.1-1 Example of Using External Clock

● Precautions in PLL clock mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops

while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its

operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such

failure occurs.

■ Power Supply Handling Precautions

● Stable Supply Voltage

Supply voltage should be stabilized.

A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating

range of the VCC power-supply voltage.

For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range

(50/60Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the

transient variation rate does not exceed 0.1V/ms during a momentary change such as when the power

supply is switched.

Flash serial programming must be performed with operational voltage is VCC=3.13V to 3.6V.

Flash programming must be performed with operational voltage is VCC=3V to 3.6V.

● When using the single system product

When using the MB90980 series as a single system product, use it with X0A=VSS, X1A=open.

● Precautions when using the dual power supplies

MB90980 series usually uses 3V power supply. However, setting VCC3=3V system/VCC5=5V system

enables P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 as 5V power supplies separately from

the main 3V power supply.

Analog power supply (AVCC, AVRH) at the time of A/D conversion is used only as a 3V system.

X0

X1Open

17


18

CHAPTER 3CPU

This chapter explains CPU specifications, memory, and the functions of registers to provide readers with a better understanding of the MB90980 functions.

3.1 Overview of CPU Specifications

3.2 Memory Space

3.3 CPU Registers

3.4 Prefix Codes

19

CHAPTER 3 CPU

3.1 Overview of CPU Specifications

This section gives an overview of the CPU specifications.

■ Overview of CPU Specifications

The F2MC-16LX CPU core is a 16-bit CPU designed for devices such as consumer devices that requires

high-speed real-time processing. The F2MC-16LX instruction set is designed for controller applications,

providing high-speed and high-efficiency control processes.

In addition to 16-bit data processing, the F2MC-16LX CPU core can provide 32-bit data processing with an

installed internal 32-bit accumulator (some instructions perform 32-bit data processing). Memory spaces

are a maximum of 16 M bytes (expandable) and can be accessed by using a linear pointer or bank. Based

on the F2MC-8L AT architecture, its instruction system is improved because of increasing the instructions

supporting high-level languages, expanding addressing modes, improving multiply and divide operation

instructions, and enhancing bit processing. The F2MC-16LX CPU has the following features:

● Minimum instruction execution time

• 40.0 ns/6.25 MHz oscillation multiplied by 4 (25 MHz/3.3 V ± 0.3 V for internal operation)

• 62.5 ns/4 MHz oscillation multiplied by 4 (16 MHz/3.0 V ± 0.3 V for internal operation)

• PLL clock multiply scheme

● Maximum memory space: 16 M bytes, accessing by using a linear pointer or bank

● Instruction system optimized for control applications

• Data types available: bit, byte, word, long word

• Standard addressing mode: Use of 23-type, 32-bit accumulator for enhancing high-precision operation

• Signed multiply and divide operations, expanded RETI instruction

● Enhanced interrupt function: 8 priority levels (programmable)

● CPU independent automatic transfer function: µDMAC up to 16 channels

● Multitasking-compatible instruction system in high-level language (C)

Use of system stack pointers, symmetrical instruction set, and barrel shift instruction

● Improved execution speed: 4-byte queue

20

3.2 Memory Space

The F2MC-16LX CPU has a 16-M bytes memory space, to which all input to and output

from the F2MC-16LX CPU controlled data program is allocated. CPU has a 24-bit address bus to access each resource.

■ Memory Map

Figure 3.2-1 shows the F2MC-16LX system and the associated memory map.

Figure 3.2-1 Example Showing Correspondence Between F2MC-16LX System and Memory Map

■ Address Generation Type

The F2MC-16LX CPU has two types of address generation. One is linear addressing that specifies all 24-

bit addresses with instructions. The other is bank addressing that specifies upper 8-bit addresses with

appropriate bank registers and lower 16-bit addresses with instructions.

Linear addressing has two types: one uses operands to directly specify 24-bit addresses; the other refers to

contents of the lower 24 bits in a 32-bit general-purpose register as addresses.

● Linear addressing (specified with 24-bit operand)

Figure 3.2-2 shows an example of linear addressing scheme specified with 24-bit operands.

Figure 3.2-2 Linear Addressing (Specified with 24-bit Operand)

F2MC-16LX

CPU

[Device]

Program

Data

Interrupt

Peripheral circuit

General-purpose port

Program area

Data area

Interrupt controller

Peripheral circuit

General-purpose port

FFFFFFHFF8000H

810000H

800000H

0000C0H

0000B0H

000020H000000H

17

12

452D

3456

17452DH

123456H

JMPP 123456H

New program counter

Next instruction

JMPP 123456H

Previous program counter

21

CHAPTER 3 CPU

● Linear addressing (indirectly specified using 32-bit register)

Figure 3.2-3 shows an example of linear addressing scheme indirectly specified using a 32-bit register.

Figure 3.2-3 Linear Addressing (Indirectly Specified Using 32-bit Register)

■ Addressing Type by BankBank addressing divides a 16-M bytes space into 256 banks of 64 K bytes each, using five bank registers to

specify banks for each space.

• Program bank register (PCB)

• Data bank register (DTB)

• User stack bank register (USB)

• System stack bank register (SSB)

• Additional bank register (ADB)

A 64-K bytes bank specified with PCB is called the program (PC) space. The PC space includes such

information as instruction codes, vector tables, and immediate data.

A 64-K bytes bank specified with DTB is called the data (DT) space. The DT space includes writable data,

and internal and external resource control/data registers.

A 64-K bytes bank specified with USB or SSB is called the stack (SP) space. The SP space is accessed if a

stack access occurs by saving the push/pop instruction or interrupt register. The stack space to be accessed

is determined by the S-flag in the condition code register.

A 64-K bytes bank specified with ADB is called the additional (AD) space. The AD space includes, for

example, data that cannot be included in the DT space.

As shown in Table 3.2-1, each addressing mode uses a default space defined in advance to improve the

efficiency of coding instructions. If an addressing mode uses a space other than the default space, a prefix

code corresponding to the bank must be specified prior to the instruction code, enabling access to any bank

space corresponding to the prefix code.

After resetting, DTB, USB, SSB and ADB are initialized to 00H, and PCB is initialized to the value

specified by a reset vector. After resetting, each space for DT, SP and AD is allocated to bank 00H(000000H to 00FFFFH), and each PC space is allocated to the bank specified by the reset vector.

XXXX

+7

RL1

3AOld AL

New AL

(Upper 8 bits are ignored)

MOV A, @RL1+7

240906F9

090700H

003A

22

Figure 3.2-4 shows an example of a memory space divided for a register bank.

Figure 3.2-4 Physical Address in Each Space

Table 3.2-1 Default Space

Default space Addressing mode

Program space PC indirect, program access, branch instruction

Data space Addressing mode using @RW0,@RW1, @RW4, and @RW5; @A; addr16; dir

Stack space Addressing mode using PUCHW, POPW, @RW3, and @RW7

Additional space Addressing mode using @RW2 and @RW6

FEH

B3H

92H

68H

4BH

FFFFFFH

FF0000H

B3FFFFH

920000H

68FFFFH

680000H

4BFFFFH

4B0000H

000000H

Program space

Additional space

User stack space

Data space

System stack space

: PCB (Program bank register)

: ADB (Additional bank register)

: USB (User stack bank register)

: DTB (Data bank register)

: SSB (System stack bank register)

92FFFFH

B30000H

Phy

sica

l add

ress

23

CHAPTER 3 CPU

■ Allocation for Data of Multi-byte Length in Memory SpaceFigure 3.2-5 shows the configuration of data of a multi-byte length in memory. The lower 8 bits of a data

item are stored at address n, then address n+1, address n+2, address n+3, etc.

Figure 3.2-5 Example for Allocating Data of Multi-byte Length in Memory

Data is written to memory in sequence starting from the lower addresses. Thus, the lower 16 bits of a 32-

bit data item is transferred first, followed by the upper 16 bits. If a reset signal is input immediately after

writing the lower bit, writing the upper bit may fail.

■ Access to Data of Multi-byte LengthFigure 3.2-6 shows an example for accessing data of a multi-byte length.

In this example, MOVW A, 030FFFFH is executed.

Figure 3.2-6 Example for Accessing Data of Multi-byte Length

H

L

Address n

01010101

11001100

11111111

00000000

MSB LSB

01010101 1100110 11111111 00000000

L

H

80FFFFH

800000H

01H

23H

?? ??

23H 01H

AL before execution

AL after execution

···

24

3.3 CPU Registers

The F2MC-16LX registers are divided into special registers inside CPU and general-purpose registers on memory. The former is dedicated hardware inside the CPU, and its use is limited because of the CPU architecture. The latter shares CPU address spaces with RAM. A general-purpose register can be accessed without specifying an address, and a user can specify the use of a general-purpose register, which is the same as for memory spaces.

■ Dedicated Registers

The F2MC-16LX has the following 11 types of dedicated registers:

• Accumulator (A = AH: AL): Two 16-bit accumulators

(used as single 32-bit accumulator)

• User stack pointer (USP): 16-bit pointer pointing to user stack area

• System stack pointer (SSP): 16-bit pointer pointing to system stack area

• Processor status (PS): 16-bit register indicating system status

• Program counter (PC): 16-bit register containing a program address

• Direct page register (DPR): 8-bit register indicating a direct page

• Program bank register (PCB): 8-bit register indicating a PC space

• Data bank register (DTB): 8-bit register indicating a DT space

• User stack bank register (USB): 8-bit register indicating a user stack space

• System stack bank register (SSB): 8-bit register indicating a system stack space

• Additional bank register (ADB): 8-bit register indicating an AD space

Figure 3.3-1 shows the configuration of the dedicated registers.

Figure 3.3-1 Configuration of Dedicated Registers

Accumulator

User stack pointer

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

AH AL

USP

SSP

PS

PC

DPR

PCB

DTB

USB

SSB

ADB

8 bits16 bits

32 bits

Processor status

System stack pointer

Program counter

25

CHAPTER 3 CPU

■ General-purpose Register

The F2MC-16LX general-purpose register resides on the main memory addresses: 000180H to 00037FH(maximum configuration). It uses a register bank register (RP) to indicate which part of addresses are

currently used for register banks. Each bank has the three types of registers listed below. They are

dependent on one another, as shown in Figure 3.3-2.

• R0 to R7: 8-bit general-purpose register

• RW0 to RW7: 16-bit general-purpose register

• RL0 to RL3: 32-bit general-purpose register

Figure 3.3-2 shows the configuration of a general-purpose register.

Figure 3.3-2 Configuration of General-purpose Register

The relationship between upper and lower bytes in a byte register and word register is represented with the

following formula: RW(i + 4) = RW(i x 2 + 1) x 256 + R(i x 2) [i = 0 to 3]. The relationship of upper and

lower bytes in RLi is represented with the following formula:

RW(i) = RW(i x 2 + 1) x 65536 + RW(i x 2) [i = 0 to 3].

000180H RP × 10H

MSB LSB

RW0

RW1

RW2

RW3

R1

R3

R5

R7

R2

R4

R6

RW4

RW5

RW6

RW7

RL0

RL1

RL2

16 bits

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3.3.1 Accumulator (A)

This section explains the accumulator (A) functions.

■ Accumulator (A)An accumulator (A) consists of two 16-bit arithmetic operation registers (AH/AL) that are used to store

operation results and temporarily store data transfer results. For 32-bit data processing, AH is connected

with AL. For word processing in the 16-bit data processing mode and for byte processing in the 8-bit data

processing mode, only AL is used. Data stored in an accumulator (A) is used together with that in memory

and registers (Ri, Rwi, Rli); and similar to F2MC-8L operations, the data item with a smaller word length is

transferred to AL. This enables data items in AL before the transfer to be automatically transferred to AH

(data hold function). The data hold function and operation between AL-AH support improvements in

processing efficiency.

During a transfer of a data item with a lower byte length to AL, a sign extension or zero extension is added

to the data, and the data is saved in AL as a 16-bit data item. Also, data in AL is handled in either word

lengths or byte lengths.

If an arithmetic operation instruction of byte processing is executed in AL, the upper 8 bits in AL before

the operation is ignored, and the upper 8 bits of operation results are reset to zero. Resetting an

accumulator (A) does not initialized it, and it has an undefined value after the reset.

Figure 3.3-3 shows 32-bit data transfer processing, and Figure 3.3-4 shows AL-AH transfer processing.

Figure 3.3-3 32-bit Data Transfer

Figure 3.3-4 AL-AH Transfer

XXXXH XXXXH

8F74H 2B52H

DTB A6H +6

RW1

A61540H

A6153EH

MSB

8FH

2BH

15H

74H

52H

38H

MOVL A,@RW1+6

A before execution

A after execution

LSB

+6

RW1

A61540H

A6153EH

XXXXH 1234H

1234H 2B52H

DTB A6H

8FH

2BH

15H

74H

52H

38H

MSB LSBMOVW A,@RW1+6

A before execution

A after execution

27

CHAPTER 3 CPU

3.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP)

This section explains the functions of the user stack pointer (USP) and system stack pointer (SSP).

■ User Stack Pointer (USP) and System Stack Pointer (SSP)The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers indicating the push/pop

instruction or the memory address to which data is saved or restored at subroutine execution. The USP

register and SSP register are used in stack-type instructions. If the S-flag in the processor status register is

set to "0", the USP register is enabled. If the S-flag is set to "1", SSP register is enabled (see Figure 3.3-5). If

an interrupt is accepted, the S-flag is set and then the register value is saved in the memory area indicated by

SSP in interrupt processing. SSP is used to execute stack processing of interrupt routines, and USP is used

to execute stack processing other than interrupt routines. Only SSP is used if stack space is not divided.

In stack processing, the address of upper 8 bits is indicated with SSP -> SSB and USP -> USB. Resetting

USP and SSP does not initialize them, but each then has an undefined value.

Figure 3.3-5 shows the relationship between stack operation instructions and the stack pointer where the S-

flag is set to "0" and "1".

Figure 3.3-5 Relationship Between Stack Operation Instructions and Stack Pointer

Note:

Use an even-numbered address for a stack pointer, in principle.

AL A624H USB USP

SSPSSB0

C6H

56H

F328H

1234H

C6F326H

MSB LSB

XXXX

AL A624H USB USP

SSPSSB0

C6H

56H

F328H

1234H C6F326H 24HA6H

Before execution

After execution

Before execution

After execution

S-flag

S-flag

Use of user stack because S-flag is set to "0"

AL A624H USB USP

SSPSSB

C6H

56H

F328H

1234H

561232H XXXX

1

AL A624H USB USP

SSPSSB1

C6H

56H

F328H

1232H

561232H 24HA6H

Use of system stack because S-flag is set to "1"

S-flag

S-flag

Example 1: PUCHW A where S-flag is set to "0"

Example 2: PUCHW A where S-flag is set to "1"

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3.3.3 Processor Status (PS)

This section explains the processor status (PS) functions.

■ Processor Status (PS)Processor status (PS) consists of bits used to execute CPU operations and bits indicating the CPU state. As

shown in Figure 3.3-6, the upper byte in the PS register consists of a register bank pointer (RP) and

interrupt level mask register (ILM). RP indicates the header address of a register bank. The lower byte of

PS register is the condition code register (CCR) that includes a flag that is set and reset depending on

execution results or interrupt events.

Figure 3.3-6 shows the configuration of processor status (PS).

Figure 3.3-6 Configuration of Processor Status (PS)

■ Condition Code Register (CCR)Figure 3.3-7 shows the configuration of the condition code register.

Figure 3.3-7 Configuration of Condition Code Register

● I: Interrupt permission flag

An interrupt other than software interrupt is permitted if the I-flag is set t

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