15EE305J - MICROCONTROLLER LAB REFERENCE MANUAL

15EE305J - MICROCONTROLLER LAB

REFERENCE MANUAL

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING FACULTY OF ENGINEERING & TECHNOLOGY

SRMUNIVERSITY, Kattankulathur – 603 203

SRM Institute of Science and Technology

Department of Electrical and Electronics Engineering

VISION AND MISSION OF THE DEPARTMENT

Vision

To impart quality education in the field of Electrical and Electronics Engineering and to produce globally

competent engineers to serve the society.

Mission

To educate the student to become better practicing engineers to meet global excellence.

To provide better environment through latest developments in electrical engineering involving

problem solving, design, practice and training.

To motivate the graduates to become a good leader, designer and researcher through industry-oriented

trainings with social and ethical responsibilities.

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

PEO1: Graduates are in a position to apply their knowledge acquired in Mathematics, Basic Sciences and

Electrical and Electronics Engineering courses, to the solution of complex problems encountered in

the modern Engineering practice.

PEO2: Graduates learn and adapt themselves to the constantly evolving technology by pursuing higher

studies.

PEO3: Graduates are better employable and achieve success in their chosen areas of Electrical and

Electronics Engineering and related fields.

PEO4: Graduates are good leaders and managers by effectively communicating at both technical and

interpersonal levels.

PROGRAM OUTCOMES (POs)

Engineering Graduates will be able to: PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals,

and an engineering specialization to the solution of complex engineering problems.

PO2: Problem analysis: Identify, formulate, review research literature, and analyze complex engineering

problems reaching substantiated conclusions using first principles of mathematics, natural sciences,

and engineering sciences.

PO3: Design/development of solutions: Design solutions for complex engineering problems and design

system components or processes that meet the specified needs with appropriate consideration for the

public health and safety, and the cultural, societal, and environmental considerations.

PO4: Conduct investigations of complex problems: Use research-based knowledge and research methods

including design of experiments, analysis and interpretation of data, and synthesis of the information

to provide valid conclusions.

PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern

engineering and IT tools including prediction and modelling to complex engineering activities with

an understanding of the limitations.

PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal,

health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional

engineering practice.

PO7: Environment and sustainability: Understand the impact of the professional engineering solutions in

societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable

development.

PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of

the engineering practice.

PO9: Individual and team work: Function effectively as an individual, and as a member or leader in

diverse teams, and in multidisciplinary settings.

PO10: Communication: Communicate effectively on complex engineering activities with the engineering

community and with society at large, such as, being able to comprehend and write effective reports

and design documentation, make effective presentations, and give and receive clear instructions.

PO11: Project management and finance: Demonstrate knowledge and understanding of the engineering

and management principles and apply these to one’s own work, as a member and leader in a team, to

manage projects and in multidisciplinary environments.

PO12: Life-long learning: Recognize the need for, and have the preparation and ability to engage in

independent and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO 1 Ability to perform in a Global & Industrial Perspective

PSO 2 Ability to acquire Skills and are Career ready

PSO 3 Ability to Utilize Energy, Safety and Practices

Mapping of Student Outcomes (SOs) and Program Outcomes (POs)

Program

Outcomes

(2018R)

Student Outcomes (2015R)

PO-1 (a) an ability to apply knowledge of mathematics, science, and engineering

PO-2 (e) an ability to identify, formulate, and solve engineering problems

PO-3

(c) an ability to design a system, component, or process to meet desired needs within realistic

constraints such as economic, environmental, social, political, ethical, health and safety,

manufacturability, and sustainability

PO-4 (b) an ability to design and conduct experiments, as well as to analyze and interpret data

PO-5 (k) an ability to use the techniques, skills, and modern engineering tools necessary for

engineering practice.

PO-6 (h) the broad education necessary to understand the impact of engineering solutions in a global,

economic, environmental, and societal context

PO-7 (j) a knowledge of contemporary issues

PO-8 (f) an understanding of professional and ethical responsibility

PO-9 (d) an ability to function on multidisciplinary teams

PO-10 (g) an ability to communicate effectively

PO-11 (d) an ability to function on multidisciplinary teams

PO-12 (i) a recognition of the need for, and an ability to engage in life-long learning

Mapping of Program Educational Objectives (PEOs) with Student Outcomes (SOs) and

Program Specific Outcomes (PSOs)

CRITERION 3 (a–k OUTCOMES)

PROGRAM EDUCATIONAL OBJECTIVES

1 2 3 4

(a) an ability to apply knowledge of mathematics, science, and engineering

X

(b) an ability to design and conduct experiments, as well as to analyze and interpret data

X

(c) an ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability

X

(d) an ability to function on multidisciplinary teams

X X

(e) an ability to identify, formulate, and solve engineering problems

X

(f) an understanding of professional and ethical responsibility

X

(g) an ability to communicate effectively in both verbal and written form.

X

(h) the broad education necessary to understand the impact of engineering solutions in a global perspective.

X

(i) a recognition of the need for, and an ability to engage

in life-long learning

X

(j) a knowledge of contemporary issues

X

(k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

X X

PSO1: Global and industrial perspective X X X

PSO2: Skills and Career ready X X X

PSO3: Energy, safety and practices X X

Syllabus

15EE305J

Microcontrollers

L T P C

3 0 2 4

Co-requisite: Nil

Prerequisite: Nil

Data Book / Codes/Standards

Nil

Course Category P PROFESSIONAL CORE INTELLIGENT SYSTEMS

Course designed by Department of Electrical and Electronics Engineering

Approval 32ndAcademic Council Meeting ,2016

PURPOSE To acquire knowledge on Microcontrollers, Processors and interfacing devices.

INSTRUCTIONAL OBJECTIVES STUDENT OUTCOMES

At the end of the course, the student will be able to

1. Gain knowledge in INTEL 8085 architecture, interrupt and programming structures.

a

2. Design ARM processor based systems along with I/O interfacing. a c

3. Understand the impact of 8051 and PIC microcontrollers in Engineering applications.

a

c

e

k

Session

Description of Topic

Contact

hours C-D-I-

O

IOs

Reference

UNIT I: PROCESSOR BASED SYSTEM 9

1.

Evolution of Microprocessors, Microcontrollers and Computers, Microprocessor based system design – need and steps-Advantages and limitations.

2

C

1

1, 2

2.

Intel 8085, Pentium Architecture Bus system – Decoders – Tri state logic.

2

C

1

1, 2

3.

Memory devices: classifications, Mapping and its interfacing- Data Transfer.

3

C,D

1

1, 2

4.

Concepts, Methods – Parallel I/O interfacing – Serial I/O interfacing concepts –DMA method of transfer.

2

C

1

1, 2

UNIT II: INTERFACING DEVICES 9

5.

8255 programmable peripheral interface - 8257/8237 programmable DMA controller, 8279 keyboard/display interfacing – 8253/8254

programmable Timer.

4

C

1

1, 2

6. Need of Interrupts – 8259 programmable interrupt controller. 5 C 1 1, 2

UNIT III: HIGH PERFORMANCE RISC ARCHITECTURE- ARM PROCESSORS

9

7.

The ARM (nuvoTon –NU-LB-NUC140) architecture - ARM organization and implementation – ARM instruction set.

3

C,I

2

1, 2

8.

Basic ARM ALP (32-bit addition, subtraction, multiplication, binary sorting),ARM memory interface – AMBA bus architecture.

2

C

2

1, 2,

9. Hardware system prototyping tools - the ARMulator. 4 C,D 2 1, 2

UNIT IV: INTEL 8051 MICROCONTROLLERS 9

10. Role of microcontrollers – 8 bit microcontrollers. 3 C 3 1, 2,

11. Architecture of Intel 8031/8051/8751 –hardware description memory organization.

3

C

3

1, 2,

12.

Addressing modes – overview of instruction set – simple programs.

3

D,I

3

1, 2

UNIT V: PIC MICROCONTROL LE RS and APPLICATIONS 9

13. Introduction - PIC microcontroller- Architecture-memory organization – I/O ports – Reset circuits – Instruction set.

3

C

3

1, 2

14. Compare/capture/PWM- Application and introduction to MPLAB. 2 C 3 1, 2

15.

Stepper motor control – Speed control of DC motor – Waveform Generator – Frequency counter - Real time clock– Generation of Gating Signals for Converters and Inverters.

4

C, D

3

1, 2

Total contact hours 45 Sl. No.

Description of experiments

Contact hours

C-D- I-O

IOs

Reference

PART-A: GENERAL PURPOSE PROGRAMMING EXERCISES

(Minimum Five experiments to be conducted)

1. Introduction of Microprocessor and Microcontroller Kit.

3

I

1-3

1-3

2 Addition, Subtraction, Multiplication and Division. 3 C 1,2 1

3. Finding the maximum value in an array. 3 D 1,2 2

4. Sorting of data. 3 I 1-3 1-3

5. Finding number of positive / negative elements in a block of data.

3

C

1-3

1

6. BCD-to-Hex conversion and Hex-to-BCD conversion. 3 D 1-3 2

7. Binary-to-ASCII and ASCII-to-Binary conversion. 3 I 1-3 1-3

8. Square Root of a given data. 3 C 1-3 1

9. LCM and GCD 3 D 1-3 2

PART-B: INTERFACING WITH APPLICATION BOARDS ({8051, ARM}) (Minimum Five experiments to be conducted)

10. 8255 PPI. 3 C 1-3 1-3

11. Transfer data serially between two kits (Study of 8253/8251).

3

D

1-3

1

12. 8279 Keyboard & display using 8051 controller. 3 I 1-3 2

13. Seven segment display 3 C 1-3 1-3

14. LCD Display using 8051 3 I 1-3 1-3

15. Traffic light. 3 C 1-3 1

16. 8259 programmable interrupt controller. 3 D 1-3 2

17. 8257/8237 DMA controller. 3 I 1-3 1-3

18. 8 bit ADC and 8 bit DAC. 3 C 1-3 1

19. Stepper motor control using 8051 controller. 3 D 1-3 2

20. DC motor speed measurement and control module. 3 I 1-3 1-3

21. Real Time Clock 3 C 1-3 1-4

Total contact hours 30 LEARNING RESOURCES

Sl. No. TEXT BOOKS

1. Gaonkar.R.S, “Microprocessor Architecture, Programming and Applications”, Wiley Eastern Limited, New Delhi, 5th Edition, 1997.

2. Kenneth Ayala, “Intel 8051 – Microcontrollers”, Prentice hall, Second Edition, 2005.

REFERENCE BOOKS/OTHER READING MATERIAL 3. Mazidi and Mazidi, “8051 Microcontrollers”, Pearson Education India, 2006.

4. Peatman, “Microcomputer Hardware”, McGraw Hill Book Company.,1995.

5. Douglas V. Hall, “Microprocessor and Interfacing”, Tata McGraw Hill, 2006.

6. John Peatman, “Design with PIC Microcontrollers”, Pearson Education Asia, 2001.

7. Steve Furber, “ARM System-on-chip architecture”, Pearson Education, India, 2000.

8. Andrew N Sloss, Symes.D, Wright.C, “ARM system developers guide”, Morgan Kauffman/Elsevier, 2007.

9. Steve Furber, “ARM Systems-on-Chip architecture” Addison Wesley, Reprint, 2012.

10. Michael J. Pont, “Embedded C”, Addison Wesley, 2002.

11. David Seal, “ARM Architecture Reference Manual”, Pearson Education, 2007.

12. Satish Shah,” 8051 Microcontrollers- Mcs 51 family and its variants” Oxford University press,1st edition, 2010.

Course nature Theory + Practical

Assessment Method – Theory Component (Weightage 50%)

In-

semester

Assessment tool Cycle test I Cycle test II Cycle Test III Surprise Test Quiz Total

Weightage 10% 15% 15% 5% 5% 50%

End semester examination Weightage : 50%

Assessment Method – Practical Component (Weightage 50%)

In-

semester

Assessment

tool

Experiments

Record

MCQ/Quiz/Viva Voce

Model examination

Total

Weightage 40% 5% 5% 10% 60%

End semester examination Weightage : 40%

Course Design

IO-SO MAPPING

PURPOSE To acquire knowledge on Microcontrollers, Processors and interfacing devices.

INSTRUCTIONAL OBJECTIVES STUDENT OUTCOMES

At the end of the course, the student will be able to

1. Gain knowledge in INTEL 8085 architecture, interrupt

and programming structures. a PSO1

2. Design ARM processor-based systems along with I/O

interfacing. a c PSO2

3. Understand the impact of 8051 and PIC

microcontrollers in Engineering applications. a c e k PSO2

CO-PO MAPPING

Course

Code

Course

Outcome

(CO)

PO

1

PO

2

PO

3

PO

4

PO

5

PO

6

PO

7

PO

8

PO

9

PO

10

PO

11

PO

12

PS

O1

PS

O2

PS

O3

15

EE

30

5J

15EE305J.1 3 - - - - - - - - - - - 3 - -

15EE305J.2 3 - 2 - - - - - - - - - - 3 -

15EE305J.3 3 2 2 - 2 - - - - - - - - 3 -

15EE305J 3 2 2 - 2 - - - - - - - 3 3 -

CO-PO MAPPING JUSTIFICATION

15EE305J

CO1 PO1 3 Mapped strongly as all the students acquire knowledge in

INTEL 8085 architecture, interrupt and programming structures.

CO2

PO1 3 Mapped substantially as all the students gain knowledge in ARM

processor-based systems along with I/O interfacing.

PO3 2 Mapped substantially as all the students gain ability to design

ARM processor-based systems along with I/O interfacing.

CO3

PO1 3

Mapped substantially as all the students gain knowledge on

impact of 8051 and PIC microcontrollers in Engineering

applications.

PO2 2

Mapped strongly as all the students acquire the ability to analyze

the impact of 8051 and PIC microcontrollers in Engineering

applications.

PO3 2 Mapped strongly as all the students acquire the ability to design

8051 and PIC microcontrollers based Engineering applications.

PO5 2

Mapped modestly as students get ability to use the 8051 and PIC

microcontrollers for engineering practice in Engineering

applications.

CO-PSO MAPPING JUSTIFICATION

15EE305J

CO1 PSO1 3

Mapped strongly as all the students gain knowledge in INTEL

8085 architecture, interrupt and programming structures in a

Global and Industrial perspective.

CO2 PSO2 3

Mapped strongly as all the students acquire skills in designing

ARM processor-based systems along with I/O interfacing get

ready for career.

CO3 PSO2 3

Mapped strongly as all the students understand the impact of 8051

and PIC microcontrollers in Engineering applications get ready

for career.

For the laboratory component of the microcontroller course, the attainment of PSO1 and PSO2 were

achieved based on viva taken in the class. The viva questions are related to latest trends in the

industry, interview questions, questions from competitive exams, etc. A sample set of questions and

their mapped PSOs are given below

S.No Question PSO

mapping

1 Which microcontroller is right for IoT needs? PSO1

2 List Microcontroller types for IoT devices. PSO1

3 List few key factors to be considered when choosing a

microcontroller.

PSO1

4 Expand GPIO and elaborate its need PSO1

5 Name few communication standards used in industrial networks PSO1

6 8051 series has _________ number of 16 bit registers? PSO2

7 A) PC pushed to stack

B) Generate Lcall to ISR

C) Complete execution of instruction in progress

D) Clear interrupt flag

E) Set interrupt in progress

Correct order of execution of action taken by 8051 MC when an

interrupt occurs is _________________

PSO2

8 Which instructions affect the PC?

A) Call & Return B) Call and Jump C) Push and pop D) Return

and jump

PSO2

9 In a microprocessor wait states are used to ____________ PSO2

10 When CPU is interrupted, it _______

A) Stops execution of instructions

B) Acknowledges an interrupt and branches to subroutine.

C) Acknowledges an interrupt and continues

D) Acknowledges an interrupt and waits for the next instruction

from the interrupt device

PSO2

LAB EXPERIMENT EVALUATION

Experiments : 40 Marks

Pre lab : 5 marks

Program : 25 marks

Execution : 15 marks

Post lab : 5 marks

Total : 50marks (converted to 40 marks)

Record : 05 Marks

Viva : 05 Marks

Model Practical : 10 Marks

Total (Internal): 60 Marks

External : 40 Marks

LABORATORY EXPERIMENTS MAPPED WITH IO, SO, PSO

Sl.No. Name of the Experiments Reference

to

IO

Reference to

student

outcome

1 Introduction to Microprocessor and

Microcontroller Kit 1,3 a, PSO1, PSO2

2

Arithmetic operation

a) Addition of 2 - 8 bit numbers

b) Subtraction of 2 - 8 bit numbers

c) Multiplication of 2 - 8 numbers

d) Division of 2 - 8 bit numbers

3 a ,e, PSO2

3 Finding maximum value in an array 3 a,e, PSO2

4 Sorting of data 3 a,e, PSO2

5 Finding number of positive / negative elements in

a block of data. 3 a,e, PSO2

6 BCD-to-Hex conversion and Hex-to-BCD

conversion 3 a,e, PSO2

7 Binary-to-ASCII and ASCII-to-Binary

conversion 3 a,e, PSO2

8 Square root of a given data 3 a,e, PSO2

9 LCM and GCD 3 a,e, PSO2

10 Transfer data serially between two kits (Study of

8253/8251). 2,3 a,c,e, PSO2

11 Seven segment display 2,3 a,c,e, PSO2

12 8-bit ADC 2,3 a,c,e, PSO2

13 8-bit DAC 2,3 a,c,e, PSO2

14 Internal Interrupt generation 1,2,3 a,c,e, PSO2

15 Stepper motor control using 8051 microcontroller 2,3 a,c,e, PSO2

16 Traffic light controller 2,3 a,c,e, PSO2

17 Study of interrupt controller 1, 2 a,c,e, PSO2

18 Study of 8255 PPI 2 a,c,e, PSO2

19 Demo on DC motor control using ARM processor 2 a,c,e,k, PSO2

20 8257/8237 DMA controller. 2,3 a,c,e, PSO2

21 Real time clock 2,3 a,c,e,k, PSO2

PRE LAB QUESTION & ANSWERS

1. What is microprocessor?

It is a general purpose program controlled semiconductor device (IC), which fetches,

Decodes and execute instructions.

2. What is the function of program counter?

a) Program counter is the 16 bit counter.

b) Sequentially program run.

c) If contain the memory address of the instruction which is next fetched.

3. What is the function of stack pointer?

Stack pointer is the 16 bit register

1. It indicates the top location of stack memory.

2. While executing the interrupt and subroutine program it uses the

microprocessor stack pointer.

4. What is an operating system?

A set of programs that manages interaction between hardware and software. It is responsible

primarily for storing information on disks and for communication between microprocessor,

memory and peripherals.

5. What is the function of ALE, and S0, S1 pin?

ALE- this is the high output signal gives the information about content on multiplexed

address/data line. If the ALE=1 it indicate that the content on multiplexed line are address

and ALE=0 multiplexed line are data. S0, S1 are status signals which give the information

about the operation of microprocessor.

POST LAB QUESTION & ANSWERS

1. What are the advantages of an assembly language in comparison with high level

language?

Sl.No Assembly language High level Language

1. There is one to one

correspondence between the

assembly language mnemonics

and the machine code. Thus

assembly programs are compact

and require less memory space.

Compliers and interpreters require large

memory space because an instruction in

English requires several machine codes to

translate it into binary.

2. More efficient than high level

language

Less efficient

3. Debugging large programs are

difficult

Debugging is easy task

4. For Real time application

assembly language is more

suitable. For eg., applications such

traffic ligh control and appliance

control, where programs are

compact, assembly language is

suitable.

For applications in which programs are

large and memory is not a limitation, high

language are desirable.

2. What is the function of HOLD and HLDA signal?

HOLD- if an external controller want to transmit a large amount of data to microprocessor it

first activate HOLD pin. HLDA-if microprocessor sense HOLD=1 it set address and data bus

in tri-state condition then acknowledge the controller.

3. What is the function of TRAP, RST7.5, RST6.5, RST5.5 interrupt?

TRAP- It is a non maskable, vectored, edge and level triggered interrupt signal. It is used for

emergency purpose like power failure, smoke detector etc. If TRAP signal is activated by any

peripheral device, control is transfer to the memory location PC=0024H.

RST7.5- it is a maskable, vectored, edge triggered interrupted signal. If RST7.5 is activated

then value of PC is set to 003CH.

RST6.5- it is a maskable, vectored, level triggered signal. When RST6.5 is activated the value

of PC is 0034H.

RST5.5- it is the maskable, vectored, edge interrupt signal. If RST5.5 activated the value of

PC is set to 002CH.

4. What is the function of timing and control unit?

It receives binary information from the instruction decoder and generates timing and control

signal.

5. What is the function of SID and SOD pin?

SID pin- SID pin is used by the microprocessor to accept one bit data under software control.

SOD pin- SOD pin is used by microprocessor to transmit one bit data under software control.

EX. NO:1a STUDY OF 8085 MICROPROCESSOR

Aim

To study the microprocessor 8085

Architecture of 8085 Microprocessor

a) General purpose register

It is an 8 bit register i.e. B,C,D,E,H,L. The combination of 8 bit register is known as register

pair, which can hold 16 bit data. The HL pair is used to act as memory pointer is accessible to

program.

b) Accumulator

It is an 8 bit register which hold one of the data to be processed by ALU and stored the result

of the operation.

c) Program counter (PC)

It is a 16 bit pointer which maintain the address of a byte entered to line stack.

d) Stack pointer (Sp)

It is a 16 bit special purpose register which is used to hold line memory address for line next

instruction to be executed.

e) Arithmetic and logical unit

It carries out arithmetic and logical operation by 8 bit address it uses the accumulator content

as input the ALU result is stored back into accumulator.

f) Temporary register

It is an 8 bit register associated with ALU hold data, entering an operation, used by the

microprocessor and not accessible to programs.

g) Flags

Flag register is a group of fire, individual flip flops line content of line flag register will

change after execution of arithmetic and logic operation. The line states flags are

i) Carry flag (C)

ii) Parity flag (P)

iii) Zero flag (Z)

iv) Auxiliary carry flag (AC)

v) Sign flag (S)

h) Timing and control unit

Synchronous all microprocessor, operation with the clock and generator and control signal

from it necessary to communicate between controller and peripherals.

i) Instruction register and decoder

Instruction is fetched from line memory and stored in line instruction register decoder the

stored information.

j) Register Array

These are used to store 8 bit data during execution of some instruction.

PIN Description

Address Bus

1. The pins Ao – A15 denote the address bus.

2. They are used for most significant bit

Address / Data Bus

1. AD0 – AD7 constitutes the address / Data bus

2. These pins are used for least significant bit

ALE: (Address Latch Enable)

1. The signal goes high during the first clock cycle and enables the lower order address bits.

IO / M

1. This distinguishes whether the address is for memory or input.

2. When this pins go high, the address is for an I/O device.

S0 – S1

S0 and S1 are status signal which provides different status and functions.

RD

1. This is an active low signal

2. This signal is used to control READ operation of the microprocessor.

WR

1. WR is also an active low signal

2. Controls the write operation of the microprocessor.

HOLD

1. This indicates if any other device is requesting the use of address and data bus.

HLDA

1. HLDA is the acknowledgement signal for HOLD

2. It indicates whether the hold signal is received or not.

INTR

1. INTE is an interrupt request signal

2. IT can be enabled or disabled by using software

INTA

1. Whenever the microprocessor receives interrupt signal

2. It has to be acknowledged.

RST 5.5, 6.5, 7.5

1. These are nothing but the restart interrupts

2. They insert an internal restart junction automatically.

TRAP

1. Trap is the only non-maskable interrupt

2. It cannot be enabled (or) disabled using program.

RESET IN

1. This pin resets the program counter to 0 to 1 and results interrupt enable and HLDA flip

flops.

X1, X2

These are the terminals which are connected to external oscillator to produce the necessary

and suitable clock operation.

SID

This pin provides serial input data

SOD

This pin provides serial output data

VCC and VSS

1. VCC is +5V supply pin

2. VSS is ground pin

Specifications

1. Processors

Intel 8085 at E144 MHz clock

2. Memory

Monitor RAM: 0000 – IFFF

EPROM Expansion: 2000 – 3FFF’s

0000 – FFF

System RAM: 4000 – 5FFF

Monitor data area 4100 – 5FFF

RAM Expansion 6000 – BFFF

3. Input / Output

Parallel: A8 TTL input timer with 2 number of 32-55 only input timer available in -85 EBI.

Serial: Only one number RS 232-C, Compatible, crucial interface using 8281A

Timer: 3 channel -16 bit programmable units, using 8253 channel ‘0’ used for no band late. Clock

generator. Channel ‘1’ is used for single stopping used program.

Display: 6 digit – 7 segment LED display with filter 4 digit for adder display and 2 digit for data

display.

Key board: 21 keys, soft keyboard including common keys and hexa decimal keys.

RES: Reset keys allow to terminate any present activity and retain to - 85 its on initialize state.

INT: Maskable interrupt connect to CPU’s RST 7.5 interrupt

DEC: Decrement the adder by 1

EXEC: Execute line particular value after selecting address through go command.

NEXT: Increment the address by 1 and then display its content.

IC’s Used

8085 - 8 bit p 8253 - programmable internal timer

8255 - programmable peripheral interface

8279 - programmable key boards / display interface

8251 - programmable communication interface

2764 - 8 KV VV EPROM

6264 - 8K STATIC PROM

7414 - Hex inverter

7432 - Quad 21/p OR GATE

7409 - Quad 21/p AND GATE

7400 - NAND Gate

7404 - Dual D-FF

74373 - Octal ‘D’ Latch

74139 - Dual 2 to 4 line decoder

74138 - 3 to 8 line decoder

In Enter Program into Trainer Kit

1. Press ‘RESET’ key

2. Sub (key processor represent address field)

3. Enter the address (16 bit) and digit in hex

4. Press ‘NEXT’ key

5. Enter the data

6. Again press “NEXT”

7. Again after taking the program, are use HLT instruction its Hex

code

8. Press “NEXT”

How to executive program

1. Press “RESET”

2. Press “GO”

3. Enter the address location in which line program was executed

4. Press “Execute” key

Result:

Thus 8085 microprocessor was studied successfully.

EX. NO:1b STUDY OF 8051 MICROCONTROLLER

Aim

To study the microcontroller 8051

Architecture of 8051 Microcontroller

Architecture of 8051 microcontroller has following features

4 Kb of ROM is not much at all.

128b of RAM (including SFRs) satisfies the user's basic needs.

4 ports having in total of 32 input/output lines are in most cases sufficient to make all

necessary connections to peripheral environment.

The whole configuration is obviously thought of as to satisfy the needs of most programmers

working on development of automation devices. One of its advantages is that nothing is missing and

nothing is too much. In other words, it is created exactly in accordance to the average user‘s taste

and needs. Other advantages are RAM organization, the operation of Central Processor Unit (CPU)

and ports which completely use all recourses and enable further upgrade.

Pin out Description

Pins 1-8: Port 1 each of these pins can be configured as an input or an output.

Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most

registers. In other words, the positive voltage on this pin resets the microcontroller. By applying logic

zero to this pin, the program starts execution from the beginning.

Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output. Besides,

all of them have alternative functions:

Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication

output.

Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication

clock output.

Pin 12: INT0 Interrupt 0 inputs.

Pin 13: INT1 Interrupt 1 input.

Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM.

Pin 17: RD Read from external RAM.

Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies operating

frequency is usually connected to these pins. Instead of it, miniature ceramics resonators can also be

used for frequency stability. Later versions of microcontrollers operate at a frequency of 0 Hz up to

over 50 Hz.

Pin 20: GND Ground.

Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured

as general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses

A8-A15 will appear on this port. Even though memory with capacity of 64Kb is not used, which

means that not all eight port bits are used for its addressing, the rest of them are not available as

inputs/outputs.

Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every

time the microcontroller reads a byte from memory.

Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte

(A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external

register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a

memory chip address. Immediately after that, the ALU pin is returned its previous logic state and P0

is now used as a Data Bus. As seen, port data multiplexing is performed by means of only one

additional (and cheap) integrated circuit. In other words, this port is used for both data and address

transmission.

Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission

with no regard to whether there is internal memory or not. It means that even there is a program

written to the microcontroller, it will not be executed. Instead, the program written to external ROM

will be executed. By applying logic one to the EA pin, the microcontroller will use both memories,

first internal then external (if exists).

Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general

inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven

high (1) or as data output (Data Bus) when the ALE pin is driven low (0).

Pin 40: VCC +5V power supply.

Input/Output Ports (I/O Ports)

All 8051 microcontrollers have 4 I/O ports each comprising 8 bits which can be configured as inputs or outputs. Accordingly, in total of 32 input/output pins enabling the microcontroller to be connected

to peripheral devices are available for use.

Pin configuration, i.e. whether it is to be configured as an input (1) or an output (0), depends on its

logic state. In order to configure a microcontroller pin as an input, it is necessary to apply a logic zero

(0) to appropriate I/O port bit. In this case, voltage level on appropriate pin will be 0.

Similarly, in order to configure a microcontroller pin as an input, it is necessary to apply a logic one

(1) to appropriate port. In this case, voltage level on appropriate pin will be 5V (as is the case with

any TTL input). This may seem confusing but don't loose your patience. It all becomes clear after

studying simple electronic circuits connected to an I/O pin.

Memory Organization

The 8051 has two types of memory and these are Program Memory and Data Memory. Program Memory (ROM) is used to permanently save the program being executed, while Data Memory

(RAM) is used for temporarily storing data and intermediate results created and used during the

operation of the microcontroller. Depending on the model in use (we are still talking about the 8051

microcontroller family in general) at most a few Kb of ROM and 128 or 256 bytes of RAM is used.

All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb memory.

It is neither a mistake nor a big ambition of engineers who were working on basic core development.

It is a matter of smart memory organization which makes these microcontrollers a real “programmers’

goody“.

Special Function Registers (SFRs)

Special Function Registers (SFRs) are a sort of control table used for running and moni toring the operation of the microcontroller. Each of these registers as well as each bit they include, has its name,

address in the scope of RAM and precisely defined purpose such as timer control, interrupt control,

serial communication control etc. Even though there are 128 memory locations intended to be

occupied by them, the basic core, shared by all types of 8051 microcontrollers, has only 21 such

registers. Rest of locations is intentionally left unoccupied in order to enable the manufacturers to

further develop microcontrollers keeping them compatible with the previous versions. It also enables

programs written a long time ago for microcontrollers which are out of production now to be used

today.

Program Status Word (PSW) Register

PSW register is one of the most important SFRs. It contains several status bits that reflect the current state of the CPU. Besides, this register contains Carry bit, Auxiliary Carry, two register bank select

bits, Overflow flag, parity bit and user-definable status flag.

P - Parity bit. If a number stored in the accumulator is even then this bit will be automatically set

(1), otherwise it will be cleared (0). It is mainly used during data transmit and receive via serial

communication.

- Bit 1. This bit is intended to be used in the future versions of microcontrollers.

OV Overflow occurs when the result of an arithmetical operation is larger than 255 and cannot be

stored in one register. Overflow condition causes the OV bit to be set (1). Otherwise, it will be cleared

(0).

RS0, RS1 - Register bank select bits. These two bits are used to select one of four register banks of

RAM. By setting and clearing these bits, registers R0-R7 are stored in one of four banks of RAM.

RS1 RS2 Space in RAM

0 0 Bank0 00h-07h

0 1 Bank1 08h-0Fh

1 0 Bank2 10h-17h

1 1 Bank3 18h-1Fh

F0 - Flag 0. This is a general-purpose bit available for use.

AC - Auxiliary Carry Flag is used for BCD operations only.

CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical operations and shift instructions.

Data Pointer Register (DPTR)

DPTR register is not a true one because it doesn't physically exist. It consists of two separate registers:

DPH (Data Pointer High) and (Data Pointer Low). For this reason it may be treated as a 16-bit register

or as two independent 8-bit registers. Their 16 bits are primarly used for external memory addressing.

Besides, the DPTR Register is usually used for storing data and intermediate results.

Stack Pointer (SP) Register

A value stored in the Stack Pointer points to the first free stack address and permits stack availability.

Stack pushes increment the value in the Stack Pointer by 1. Likewise, stack pops decrement its value

by 1. Upon any reset and power-on, the value 7 is stored in the Stack Pointer, which means that the

space of RAM reserved for the stack starts at this location. If another value is written to this register,

the entire Stack is moved to the new memory location.

P0, P1, P2, P3 - Input/Output Registers

If neither external memory nor serial communication system are used then 4 ports with in total of 32

input/output pins are available for connection to peripheral environment. Each bit within these ports

affects the state and performance of appropriate pin of the microcontroller. Thus, bit logic state is

reflected on appropriate pin as a voltage (0 or 5 V) and vice versa, voltage on a pin reflects the state

of appropriate port bit.

As mentioned, port bit state affects performance of port pins, i.e. whether they will be configured as

inputs or outputs. If a bit is cleared (0), the appropriate pin will be configured as an output, while if

it is set (1), the appropriate pin will be configured as an input. Upon reset and power-on, all port bits

are set (1), which means that all appropriate pins will be configured as inputs.

Counters and Timers

As you already know, the microcontroller oscillator uses quartz crystal for its operation. As the

frequency of this oscillator is precisely defined and very stable, pulses it generates are always of the

same width, which makes them ideal for time measurement. Such crystals are also used in quartz

watches. In order to measure time between two events it is sufficient to count up pulses coming from

this oscillator. That is exactly what the timer does. If the timer is properly programmed, the value

stored in its register will be incremented (or decremented) with each coming pulse, i.e. once per each

machine cycle. A single machine-cycle instruction lasts for 12 quartz oscillator periods, which means

that by embedding quartz with oscillator frequency of 12MHz, a number stored in the timer register

will be changed million times per second, i.e. each microsecond.

The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their main

purpose is to measure time and count external events. Besides, they can be used for generating clock

pulses to be used in serial communication, so called Baud Rate.

Timer T0

As seen in figure below, the timer T0 consists of two registers – TH0 and TL0 representing a low

and a high byte of one 16-digit binary number.

Accordingly, if the content of the timer T0 is equal to 0 (T0=0) then both registers it consists of will contain 0. If the timer contains for example number 1000 (decimal), then the TH0 register (high byte)

will contain the number 3, while the TL0 register (low byte) will contain decimal number 232.

Formula used to calculate values in these two registers is very simple: TH0 × 256 + TL0 = T

Matching the previous example it would be as follows:

3 × 256 + 232 = 1000

Since the timer T0 is virtually 16-bit register, the largest value it can store is 65 535. In case of

exceeding this value, the timer will be automatically cleared and counting starts from 0. This

condition is called an overflow. Two registers TMOD and TCON are closely connected to this

timer and control its operation.

TMOD Register (Timer Mode)

The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to the timer 1.

There are 4 operational modes and each of them is described herein.

Bits of this register have the following function:

GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin (P3.3):

o 1 - Timer 1 operates only if the INT1 bit is set.

o 0 - Timer 1 operates regardless of the logic state of the INT1 bit.

C/T1 selects pulses to be counted up by the timer/counter 1:

o 1 - Timer counts pulses brought to the T1 pin (P3.5).

o 0 - Timer counts pulses from internal oscillator.

T1M1,T1M0 These two bits select the operational mode of the Timer 1.

T1M1 T1M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-

reload

1 1 3 Split mode

GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2):

o 1 - Timer 0 operates only if the INT0 bit is set.

o 0 - Timer 0 operates regardless of the logic state of the INT0 bit.

C/T0 selects pulses to be counted up by the timer/counter 0:

o 1 - Timer counts pulses brought to the T0 pin (P3.4).

o 0 - Timer counts pulses from internal oscillator.

T0M1,T0M0 These two bits select the oprtaional mode of the Timer 0.

T0M1 T0M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

Timer Control (TCON) Register

TCON register is also one of the registers whose bits are directly in control of timer operation. Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt control

to be discussed later.

TF1 bit is automatically set on the Timer 1 overflow. TR1 bit enables the Timer 1.

o 1 - Timer 1 is enabled.

o 0 - Timer 1 is disabled.

TF0 bit is automatically set on the Timer 0 overflow.

TR0 bit enables the timer 0.

o 1 - Timer 0 is enabled.

o 0 - Timer 0 is disabled.

Timer 1

Timer 1 is identical to timer 0, except for mode 3 which is a hold-count mode. It means that they

have the same function, their operation is controlled by the same registers TMOD and TCON and

both of them can operate in one out of 4 different modes.

Result:

Thus the architecture of 8051 has been studied.

PRELAB QUESTIONS AND ANSWERS

1. What do you mean by Arithmetic group instruction?

These groups of instructions perform arithmetic operations such as addition, subtraction,

increment and decrement etc.

2. What is compiler?

A compiler is software which converts high level language into its equivalent machine

language. A compiler will take a program as one & compile it.

3. What is interpreter?

Software which converts high level language into its equivalent program line by line. The

instructions with error is found & checked.

4. Classification of 8051 Instruction set.

Data Transfer set

Arithmetic Instruction set

Logic Instruction set

Branching Instruction set

5. What is the function of accumulator?

1. Accumulator is the 8 bit register. During arithmetical and logical operation microprocessor

used this register.

2. After arithmetic and logical operation the output result data bus store through accumulator.

POST LAB QUESTIONS AND ANSWERS

1. Define OPCODE and Operand, and specify the opcode and the operand in the

instruction MOV A, B.

Opcode is the operation to be performed and operand is the data to be operated on.

In MOV H,L MOV is the opcode and A,B is the operand. A is the destination and B is the

source register.

2. What is the function of ADC A, source byte?

This will add the source byte to A, in addition to the CY flag (A=A+byte+CY).

3. What is the function of SUBB A, source-byte?

This subtracts the source byte and the carry flag from the accumulator and puts the result in

the accumulator.

4. What is the function of MOVX @DPTR,A?

This instruction copies the data of A to the pointed location of Data Pointer.

5. What is PSW?

The program status word register is a 8bit register. It is also referred to as the flag register.

Although the PSW register is 8 bits wide, only 6 bits of it are used by the 8051.

EX.NO:2 ARTHMETIC OPERATIONS USING 8051

Aim:

To do the arithmetic operations using 8051 microprocessor

Apparatus required:

8085 microprocessor kit

DAC interface kit

Keyboard

Algorithm:

Addition / Subtraction

Step 1 : Move 1st data to memory

Step 2 : Add or subtract 1H data with 2nd data

Step 3 : Initialize data pointer.

Step 4 : Move result to memory pointed by DPTR.

Multiplication / Division

Step 1 : Get 1st data and 2nd data to memory

Step 2 : Multiply or divide 1st data with 2nd data

Step 3 : Initialize data pointer.

Step 4 : Move result to memory pointed by DPTR (first port)

Step 5 : Increment DPTR

Step 6 : Move 2nd part of result to register A

Step 7 : Move result to 2nd memory location pointer by DPTR

START

Out 1s data in memory

Add or subtract 1st and 2st data

Initialize DPTR

Stop

Move result to memory preset by DPTR

Program: 8-bit Addition:

Memory

Location

Label Opcode Mnemonics Comments

4100 74 01 MOV A, #01 Moves data 1 to register

A

4102 24 02 ADD A, #02 Add content of A and

data 2 and store in A

4104 90 45 00 MOV DPTR,#4500 Moves data 4500 to

DPTR

4107 F0 MOVX @DPTR,A Moves control of A to

location pointed DTPR

4108 80 FE SJMP 4109 Short jump to 4109

Execution:

Addition:

ML Input

4101 01

4103 02

ML Output

4500 03

START

Get data into the register

Complement the data

Move the data to pointer by DPTR

Stop

Increment data

Increment DPTR

Move data into paste location

Short jump to preset location

Program: 8-bit Subtraction:

Memory

Location


4100 74 05 MOV A,#05 Moves data 1 to register

A

4102 94 02 SUBB A,#02 Subtract data 2 from

content of A and store

result in A

4104 90 45 00 MOV DPTR,#4500 Moves 4500 to DPTR

4107 F0 MOVX @DPTR,A Moves result by

location by DTPR

4108 80 FE SJMP 4109 Short jump to 4109

Execution:

Subtraction:

ML Input

4101 05

4103 02

Flow Chart Multiplication:

ML Output

4500 03

Start

Move the 1st data to A and the 2nd to B register

Multiply A and B

Initialise DPTR as 4500H

Move the product to location 4500H

Increment DPTR & move the value of carry

Stop

Program: 8-bit Multiplication:

Memory

Location


4100 Start 74 03 MOV A,#03 Move immediate data

to accumulator

4101 75 F0 02 MOV B,#02 Move 2nd data to B

register

4105 A4 MUL AB Get the product in A &

B

4106 90 45 00 MOV DPTR, # 4500 Load data in 4500

location

4109

F0 MOVX @DPTR,A

Move A t ext RAM

410A A3 INC DPTR

410B E5 F0 MOV A,B Move 2nd data in A

410D F0 MOVX @DPTR,A Same the ext RAM

410E 80 FE SJMP 410E Remain idle in infinite

loop

Execution:

Multiplication:

ML Input

4101 03

4103 02

Flowchart Division:

Output Address Value

4500 06

Start

Move the 1st data to A and the 2nd to B register

Divide A and B

Initialise DPTR as 4500H

Move the quotient to location 4500H

Increment DPTR & move the value of remainder

Stop

Program: 8-bit Division:

Memory

Location


4100 Start 74 04 MOV A,#04 Move immediate data

to accumulator

4102 75 F0 02 MOV B,#02 Move immediate to B

reg.

4105 84 DIV AB Divide content of A &

B

4106 90 45 00 MOV DPTR, # 4500 Load data pointer with

4500 location

4109 F0 MOVX @DPTR,A Move A to ext RAM

410A A3 INC DPTR Increment data pointer

410B E5 F0 MOV A,B Move remainder to A

410D F0 MOVX @DPTR,A Move A to ext RAM

410E 80 FE SJMP 410E Remain idle in infinite

loop

Execution:

Division:

ML Input

4101 04

4103 02

Result:

Thus 8-bit addition, subtraction, multiplication and division is performed using 8051.

Output Address Value

4500 02

PRELAB QUESTIONS AND ANSWERS

1. What is a bus?

A Group of lines used to transfer bits between the microprocessor and peripherals or memory.

2. What is Assembler directive?

ORG (origin)

The ORG directive is used to indicate the beginning of the address. The number that

comes after ORG can be either in hex or in decimal.

EQU (equate)

This is used to define a constant without occupying a memory location. The EQU

directive does not set aside storage for a data item.

3. Compare 8051 family members.

Feature 8051 8052 8031

ROM(On Chip) 4K 8K 0K

RAM 128 256 128

Timers 2 3 2

I/O pins 32 32 32

Serial Ports 1 1 1

Interrupts Sources 6 8 6

4. How many address lines are necessary to address 2048K memory?

2x = 2048 X 1024

X log (2) = log (2048 X 1024)

X = 21 address lines

5. What do you mean by T-state, instruction cycle, and machine cycle?

T-state: Each clock period of clock signal is called T- state.

Instruction cycle: The time taken by the microprocessor to read an instruction from memory.

It takes 1 to 6 machine cycle to read an instruction from memory.

Machine cycle: The time taken to decode data/ opcode / operand from memory/ peripheral

devices. It takes 1to 6 T-states.


1. Why is the data bus bidirectional?

Because data flows in both direction between MPU, memory and peripheral devices.

2. Why are program counter 16 bit register and stack pointer 8 bit register?

Since PC holds the 16 bit address which access external RAM memory and while SP

holds 8 bit address which refers to internal RAM location(since it is only 128 bytes).

3. What is assembler?

An assembler translates a file of assembly language statements into a file of binary machine

instructions and binary data.

4. What is the function of DJNZ byte, target?

Decrement jump if not equal to zero. In this instruction a byte is decremented, and if

the result is not zero it will jump to target address.

5. What do you mean by Indirect addressing Mode addressing mode?

Indirect addressing Mode – In indirect addressing mode the address of the data is not given

by the instruction but a memory pointer indicate were the data is present.

EX.NO: 3 FINDING MAXIMUM VALUE IN AN ARRAY

Aim:

Write an assembly language program to find the biggest number in an array of 8-bit unsigned

numbers of predetermined length.

Apparatus required:

8051 microcontroller kit

(0-5V) DC battery

Algorithm:

1. Initialize pointer and counter.

2. Load internal memory location 40H as zero.

3. Move the first element of an array to r5 register.

4. Compare the data stored in memory location 40H is equal to or less than the value

of first element of an array.

5. If it is lesser, then move the data of first element to 40H memory location ELSE

increment pointer and decrement counter.

6. Check the counter. If counter is not equal to zero, repeat from the 2nd step else

Move the R5 register to 40H memory location.

7. Stop the program.

Start

Initialize DPTR

Initialize temporary register to store maximum value

Assign the size of array

Get data from array to reg A

Compare reg A and temp reg

Stop

Is reg A>= temp reg Move reg A to temp reg

Increment data pointer & Decrement the array size

Is

Array size = 0

Move temp register to

memory

YES

NO

NO

YES

Program:

Memory

Location


4100 90 42 00 MOV DPTR,#4200H

4103 75 40 00

MOV 40H,#00H

4106 7D 0A MOV R5,#05H

Give the number of inputs for

finding the largest number.

4108 LOOP2: E0 MOVX A,@DPTR

Moves into accumulator a byte

from external memory

4109 B5 40 08 CJNE A,40H,LOOP1

Compare and jump not equal to

‘A’

410C LOOP 3 A3 INC DPTR

410D DD F9 DJNZ R5,LOOP2

Decrement and Jump not equal to

Zero

410F E5 40 MOV A,40H

4111 F0 MOVX @DPTR,A

4112 HLT 80 FE SJMP HLT

4114 LOOP1 40 F6 JC LOOP3

4116 F5 40 MOV 40H,A

4118 80 F2 SJMP LOOP3

SAMPLE INPUT AND OUTPUT:

INPUT:

Memory address Data

4200 05

4201 06

4203 07

4204 08

4205 09

OUTPUT:

Memory address Data

4206 09

RESULT:

Thus the assembly language program was written to find the largest element in an array and

executed using 8051 microcontroller.

PRELAB QUESTION & ANSWER

1. What do you mean by Resister addressing mode addressing mode?

Resister addressing mode – In this addressing mode the data is present in any general purpose

resister. It is 1 Byte instruction.

2. What do you mean by Implicit addressing mode addressing mode?

Implicit/Inherent addressing mode – In this addressing mode the memory location of

data/Operant is not given in the instruction, the instruction define itself in a program.

3. What is the function of INC?

This instruction adds 1 to the register or memory location specified by the operand.

4. When the AC flag will be set?

If there is a carry from D3 to D4 during an ADD or SUB operation, this bit is

set; otherwise, it is cleared.

5. What is the function of JNC?

This instruction examines the carry flag CY and it is zero it will jump to the target

address.

POST LAB QUESTION & ANSWER

1. What bits of PSW is responsible for selection of the register bank?

PSW.4(RS1) and PSW.3(RS0) are responsible for bank selection

2. Name the flags & the condition when each flag will be set.

The five flag bits give the status of the microprocessor after and ALU operation.

The carry (C) flag bit is set if the parity of the accumulator is even.

The Auxiliary Carry (AC) flag bit indicates overflow out of bit –3 (lower nibble) in the same

manner, as the C-flag indicates the overflow out of the bit-7.

The Zero (Z) flag bit is set if the content of the accumulator after any ALU operations is zero.

The Sign(S) flag bit is set to the condition of bit-7 of the accumulator as per the sign of the

contents of the accumulator (positive or negative)

3. What is the function CJNE instruction?

The magnitude of the source byte and destination byte are compared. If they are not equal, it

jumps to the target address.

4. What is need for PSEN pin?

This is an output pin. PSEN stands for “program store enable”. In an 8031 based

system in which an external ROM holds the program code, this pin is connected to the OE

pin of the ROM.

5. What is ALE?

Address Latch Enable is an output pin and is active high. The 8031 multiplexes address and

data through port 0 to save pins. The ALE is used for demultiplexing the address and data by

connecting to G pin of the 74LS373 chip.

EX.NO: 4 SORTING OF DATA-ASCENDING ORDER-DESCEDING

AIM:

To arrange an array of 8-bit unsigned numbers of known length in an ascending order.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Initialize the register and data pointer.

2. Get first two elements in registers A &B.

3. Compare the two elements of data. If value of B register is high then exchange A & B

data else increment pointer and decrement register R3.

4. Check R3 is zero, and then move the register R5 & R6.

5. Again increment pointer and decrement R4,

6. Check R4 is zero. If no repeat the process from step 2.

7. Otherwise stop the program.

Flowchart:

START

Load count in accumulator and move it to register R4

Decrement register R4

Load starting address in DPTR register pair

Using data pointer load the number of counts in register R3


Increment DPTR pointer

Move memory content to accumulator

Increment data pointer

Is

A<M ? Exchange content of memory and

accumulator

Decrement register R4 Is

R4= 0?


R3= 0?

END

NO

NO

NO

YES

YES

YES

Memory

Location


4100 7B 04 MOV R3,#4

4102 7C 04 MOV R4,#4

4104 90 45 00 MOV DPTR,#4500

4107 REPT 1: AD 82 MOV R5,DPL

4109 AE 83 MOV R6, DPH

410B E0 MOVX A,@DPTR

410C F5 FO MOV B,A

410E REPT A3 INC DPTR

410F E0 MOVX A,@DPTR

4110 F8 MOV R0,A

4111 C3 CLR C

4112 95 F0 SUBB A,B

4114 50 13 JNC CHKNXT

4116 EXCH C0 82 PUSH DPL

4118 C0 83 PUSH DPH

411A 8D 82 MOV DPL,R5

411C 8E 83 MOV DPH,R6

411E E8 MOV A,R0

411F F0 MOVX @DPTR,A

4120 D0 83 POP DPH

4122 D0 82 POP DPL

4124 E5 F0 MOV A,B


4127 88 F0 MOV B,R0

Algorithm Descending:

1. Initialize the register and data pointer.

2. Get first two elements in registers A &B.

3. Compare the two elements of data. If value of B register is low then exchange A & B data else

increment pointer and decrement register R3.

4. Check R3 is zero, and then move the register R5 & R6.

5. Again increment pointer and decrement R4,

6. Check R4 is zero. If no repeat the process from step 2.

7. Otherwise stop the program.

4129 CHKNXT: DBE3 DJNZ R3,REPT

412B 1C DEC R4

412C EC MOV A,R4

412D FB MOV R3,A

412E OC INC R 4

412F 8D 82 MOV DPL,R5

4131 8E 83 MOV DPH,R6

4133 A3 INC DPTR

4134 DC D1 DJNZ R4,REPT1

4136 80 FE SJMP HLT

Flowchart:

START

Load count in accumulator and move it to register R4


Load starting address in DPTR register pair

Using data pointer load the number of counts in register

R3


Increment DPTR pointer

Move memory content to accumulator

Increment data pointer

Is

A<M? Exchange content of memory

and accumulator


R4= 0?


R3= 0?

END

NO

NO

NO

YES

YES

YES

Program for Descending:

Memory

Location


4100 7B 04 MOV R3,#4

4102 7C 04 MOV R4,#4

4104 90 45 00 MOV DPTR,#4500

4107 REPT 1: AD 82 MOV R5,DPL

4109 AE 83 MOV R6, DPH

410B E0 MOVX A,@DPTR

410C F5 FO MOV B,A

410E REPT A3 INC DPTR

410F E0 MOVX A,@DPTR

4110 F8 MOV R0,A

4111 C3 CLR C

4112 95 F0 SUBB A,B

4114 40 13 JC CHKNXT

4116 EXCH C0 82 PUSH DPL

4118 C0 83 PUSH DPH

411A 8D 83 MOV DPL,R5

411C 8E 83 MOV DPH,R6

411E E8 MOV A,R0

411F F0 MOVX @DPTR,A

4120 D0 83 POP DPH

4122 D0 82 POP DPL

4124 E5 F0 MOV A,B


4127 88 F0 MOV B,R0

4129 CHKNXT: DBE3 DJNZ R3,REPT

412B 1C DEC R4

412C EC MOV A,R4

412D FB MOV R3,A

412E OC INC R 4

412F 8D 82 MOV DPL,R5

4131 8E 83 MOV DPH,R6

4133 A3 INC DPTR

4134 DC D1 DJNZ R4,REPT1

4136 80 FE SJMP HLT

SAMPLE INPUT AND OUTPUT ASCENDING

INPUT:

Memory address Data

4500 05

4501 04

4502 03

4503 01

4504 02

OUTPUT:

Memory address Data

4500 01

4501 02

4502 03

4503 04

4504 05

SAMPLE INPUT AND OUTPUT DESCENDING

INPUT:

Memory address Data

4500 03

4501 02

4502 01

4503 04

4504 05

OUTPUT:

Memory address Data

4500 05

4501 04

4502 03

4503 02

4504 01

RESULT:

Thus the assembly language program was written to sort the data in an ascending order and

executed using 8051 microcontroller.

PRE LAB QUESTIONS AND ANSWERS

1. What is DA instruction?

Decimal Adjust Accumulator after addition. This instruction is used after addition of

BCD numbers to convert the result back to BCD.

2. What is BCD number?

Binary coded decimal is a system of writing numerals that assigns a four-digit binary

code to each digit 0 through 9 in a decimal (base-10) numeral.

3. Find the CY and AC flags for each of the following.

a) MOV A, #3FH

ADD A, #45H

b) MOV A, #99H

ADD A, #58H

4. Explain the difference between the CY and OV flags and where each one is used.

CY Flag.

The Carry flag is set when there is a carry from D7 out in 8 bit(D0 to D7).

OV Flag.

This flag is set for signed addition and negative numbers based on two rules.

1. If there is a carry from D6 to D7 and no carry from D7 out.

2. If there is a carry from D7 out and no carry from D6 to D7.

And also this is in MUL and DIV instruction predominantly to indicate in multiplication that

the multiplied value is greater than FFH the OV flag is set and also in DIV if the B register

value is zero then the OV flag is set.

5. If the memory chip size is 256 X 1 bits, how many chips are required to make up 1K

(1024) bytes of memory?

32 chips.


6. The memory address of the last location of an 8K byte memory chip is FFFFH. Find the

starting address.

F000H

7. ASCII stands for ------------------------. And give the ASCII equivalent hex value for the

characters B, C and D.

AMERICAN STANDARD CODE FOR INFORMATION INTERCHANGE.

42, 43 and 44 are the Hex values for the ASCII characters B, C and D.

8. What is ROM address space for 8052?

8K

9. How stacks are accessed in the 8051?

When the 8051 is powered up, the SP register contains value 07. This means that RAM

location 08 is the first location being used for the stack by the 8051. The storing of a CPU

register in the stack is called PUSH and loading the contents of the stack back into CPU

register is called a POP.

EX.NO: 5 FINDING NUMBER OF POSITIVE / NEGATIVE ELEMENTS IN A

BLOCK OF DATA

Aim:

Write an assembly language program to find the number of positive / negative elements in a

block of data.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Initialize pointer and counter.

2. Load internal memory location 0AH as zero.

3. Move the first element of an array to r5 register.

4. Compare the data stored in memory location 40H is equal to or less than the value

of first element of an array.

5. If it is lesser, then move the data of first element to 40H memory location ELSE

increment pointer and decrement counter.

6. Check the counter. If counter is not equal to zero, repeat from the 2nd step else

Move the R5 register to 40H memory location.

7. Stop the program.

Start

Initialize DPTR

Initialize temporary register to store

Assign the size of array

Get data from array to reg A

Compare reg A and temp reg

Stop

Is reg A>= temp reg Move reg A to temp reg

Increment data pointer & Decrement the array size

Is

Array size = 0

Move temp register to

memory

YES

NO

NO

YES

Program:

Memory

Location


4100 90 0A MOV DPTR,#0AH

An external address

4102 78

MOV R0,#0AH

Array counter

4104 loop A7 MOV R1,#0h To count positive numbers

4106 E0 MOV A,@DPTR

4107 33 RLC

4108 40 JC neg

410A A3 INC R1

410B D5 DJNZ R0,loop

410E neg 80 SJMP end

4111 end D5 DJNZ R0, loop

4114 00 NOP


INPUT:

Memory address Data

4100 05

4101 06

4103 07

4104 08

4105 F7

OUTPUT:

Memory address Data

4106 4

4107 1

RESULT:

Thus the assembly language program was written to find the number of positive / negative elements

in a block of data.

EX.NO: 6a HEX TO ASCII CONVERSION

Aim:

Write an assembly language program to convert a HEX to its equivalent ASCII code and

display the result in the address field.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Get the ASCII characters in the range 0 to 9 or A to F as input

2. Compare whether it falls in the range 0 to 9 or A to F

3. If it falls in the range 0 to 9 add 30H or add 37H

4. Display the result in the address field.

FlowChart:

Store the result in memory

Start

Get the Hex input

Subtract Hex input and 0AH

Add 30 to Hex input

Stop

Is

Result <0

YES

NO

Add 37 to Hex input

Program:

Hint: 0 to 9 in ASCII equivalent Hex value is 30H to 39H and for A to F in ASCII is 41H to

46H

Memory

Location


4100 90 42 00 MOV DPTR,#4200H Input a HEX Value

4103 E0 MOVX A, @DPTR

4104 F8 MOV R0,A

4105 94 0A SUBB A, #0AH Compare Value 0-9

4107 50 05 JNC LOOP1 Values A-F go to Loop 1

4109 E8 MOV A,R0

410A 24 30 ADD A,#30H 0-9 Add 30H

410C 80 03 SJMP LOOP

410E LOOP 1 E8 MOV A, R0

410F 24 37 ADD A, #37H A-F Add 37H

4111 LOOP 90 45 00 MOV DPTR, #4500H

4114 F0 MOVX @DPTR, A Output Hex Value Equivalent to

ASCII Character

4115 80 FE SJMP 4115


INPUT:

Memory address Data

4200 Hex=9

OUTPUT:

Memory address Data

4500 ASCII equivalent Hex Value =39

Result:

Thus the assembly language program was written to convert HEX to ASCII and executed using

8051 microcontroller.

EX.NO: 6b ASCII TO BINARY CONVERSION

Aim:

Write an ALP to convert a ASCII to its equivalent BINARY number and display the result in

the data field.

Apparatus required:


(0-5V) power supply

Algorithm:

Step1: Get the Ascii code.

Step2: Clear carry bit

Step3: Subtract with borrow 30h from the input

Step4: Subtract Accumulator with 0AH

Step5: Display Hexadecimal Value at 4300H

Step6: Display Binary Value at 4500H

Program:

Memory

Location


4100 90 42 00 MOV DPTR#4200H Get an Input

4103 E0 MOVX A,@DPTR

4104 C3 CLR C

4105 94 30 SUBB A,#30H Convert ASCII

4107 C3 CLR C

4108 94 0A SUBB A, #0AH

410A 40 04 JC LOOP

410C 74 FF MOV A, #FFH

410E 80 02 SJMP L1

4110 LOOP 24 0A ADD A,#0AH

4112 L1 90 43 00 MOV DPTR, #4300H


4116 F5 F0 MOV B,A

4118 79 08 MOV R1,#08H

411A 90 45 00 MOV DPTR,#4500H BINARY OUTPUT

411D LOP 13 RRC A

411E F5 F0 MOV B,A

4120 40 05 JC LOOP1

4122 74 00 MOV A,#00H


4125 80 03 SJMP RESULT

4127 LOOP1 74 01 MOV A, #01H

4129 F0 MOVX @DPTR, A

412A RESULT 05 82 INC DPL

412C E5 F0 MOV A,B

412E D9 ED DJNZ R1, LOP

4130 80 FE SJMP 4130

Address Sample1 Sample2

Input (ASCII) 4200 39

Hexa Decimal Value 4300 09(hex value)

Output (BINARY)in

the data field

4500 01(binary value)

4501 00

Result:

Thus the assembly language program was written to converter ASCII number to equivalent Binary

Value and executed using 8051 microcontroller.

EX.NO: 7a BCD TO HEX CONVERSION

Aim:



Apparatus required:


(0-5V) DC battery

Algorithm:

1. Enter a program. 2. Enter an input BCD value in location 4200h & 4201h. 3. Execute the program. 4. The output HEX value stored in a location 4500h.

FlowChart:


Start

Get the BCD input

Multiply 10 to MSB

Add Hex Value

Stop

Get Second input data

Program:

Memory

Location


4100 90 42 00 MOV DPTR,#4200H Get input data (MSB)


4104 75 F0 0A MOV B, #0AH

4107 A4 MUL AB Multiply 10 to MSB

4108 F9 MOV R1, A

4109 90 42 01 MOV DPTR, #4201H Get input data(LSB)

410C E0 MOVX A, @DPTR

410D 29 ADD A, R1 Add to hex value

410E 90 45 00 MOV DPTR, #4500H

4111 F0 MOVX @DPTR, A Store the output

4112 HLT: 80 FE SJMP HLT


INPUT:

Memory address Data

4200 02

4201 09

OUTPUT:

Memory address Data

4500 1D(hex value)=29 decimal

Result:

Thus the assembly language program was written to convert HEX to ASCII and executed using

8051 microcontroller.

EX.NO: 7b HEX TO BCD CONVERSION

Aim:



Apparatus required:


(0-5V) DC battery

Algorithm:

1.Enter a program.

2.Enter an input HEX value in location 4200h.

3.Execute the program.

4.The output BCD value stored in a location 4500h.

FlowChart:


Start

Get the Hex input

Multiply 10 to MSB

Add Hex Value

Stop

Get Second input data

Program:

Memory

Location


4100 90 42 00 MOV DPTR,#4200H Get a hex value.


4104 75 F0 64 MOV B, #64H calculate no of 100’S

4107 84 DIV AB

4108 90 45 00 MOV DPTR, #4500H store 1st BCD digit

410B F0 MOVX @DPTR, A

410C E5 F0 MOV A,B

410E 75 F0 0A MOV B, #0AH calculate no of 10’S

4111 84 DIV AB

4112 A3 INC DPTR store 2nd BCD digit


4114 A3 INC DPTR store 3rd BCD digit

4115 E5 F0 MOV A,B




INPUT:

Memory address Data

4200 Hex= FE

OUTPUT:

Memory address Data

4500 02

4501 05

4502 04

Result: Thus the assembly language program was written to convert HEX to BCD and

executed using 8051 microcontrollers.

PRE LAB QUESTION AND ANSWERS

1. Show the stack and stack pointer for each line of the following program.

MOV R0, #66H

MOV R3, #7FH

MOV R7, #5DH

PUSH 0

PUSH 3

PUSH 7

CLR A

MOV R3, A

MOV R7, A

POP 3

POP 7

POP 0

Mnemonic Stack (Default) Stack Pointer pointed to 07h

intially

PUSH 0 Bank 1 08

PUSH 3 Bank 1 09

PUSH 7 Bank 1 0A

POP 3 Bank 1 0A

POP 7 Bank 1 09

POP 0 Bank 1 08

2. What is the function of LCALL instruction?

LCall is a three byte instruction used to transfer program control to subroutine the starting

address is specified instruction.

3. What is the function of RETURN instruction?

Return instruction is a 1 byte instruction used to transfer program control back to main

program to implement this transfer is takes back the store contain of PC from stack and next

instruction executed will be from main program

POST LAB QUESTION AND ANSWERS

1. Name the different JUMP instructions

Opcode Description Flag Status

JC Jump on Carry CY = 1

JNC Jump on no Carry CY = 0

DJNZ Decrement and Jump if A! = 0

JB Jump on Bit

JZ Jump on zero Z = 1

JNZ Jump on no zero Z = 0

CJNEZ A, byte Jump if A! = byte

CJNEZ reg, #data Jump if byte != # data

2. What do you mean by CONDITIONAL/ UN-CONDITIONAL CALL instruction?

When conditional call instruction is executed, the condition is checked. If true then a call at

address is made else it will proceed for next instruction after it.

When unconditional call instruction is executed the program sequence is transfer to the

address specified in the instruction.

3. What is NOP instruction? When do we use it?

No operation is performed. The instruction is fetched and decoded. However no operation is

executed. This instruction is used in time delays.

EX.NO: 8 FIND THE SQUARE ROOT OF A GIVEN DATA

Aim:

To write an assembly language program to find the square root of a given data

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Enter a program.

2. Enter the input hex value to location 4200h.

3. Execute the program.

4. The output square root value stored in a location 4500h.

FlowChart:

Store the quotient to memory

Start

Get the input

Subtract quotient and count

Count = count +1

Stop

Is

Result = 0

YES

NO

Divide input data by count

Initialise count = 1

PROGRAM:

Memory

Location


4100 Origin: 90 42 00 MOV DPTR,#4200h Get a input data

4103 E0 MOVX A,@DPTR

4104 F9 MOV R1,a

4105 7A 01 MOV R2, #01h Initialize counter

4107 L1: E9 MOV A,R1

4108 8A F0 MOV B,R2

410a 84 DIV AB divide the given value

and counter

410b FB MOV R3,A

410c AC F0 MOV R4,B

410e 9A SUBB A ,R2 compare

410f 60 03 JZ RESULT Dividend and counter

4111 0A INC R2

4112 80 F3 SJMP L1

4114 Result: 90 45 00 MOV DPTR, #4500H Square Root

4117 EB MOV A,R3

4118 F0 MOVX @DPTR,A Stored

4119 HLT 80 FE SJMP HLT


Result: Thus an assembly language program is written to find the square root of a given data and executed

successfully

ML Input

4200 40(hex

value)=64(decimal)

ML Output

4500 8

EX.NO:9 LCM and GCD

Aim:

To write an assembly language program to find the LCM and GCD

Apparatus required:


(0-5V) DC battery

Algorithm:

1.Enter the program.

2.Enter the two inputs value in location 4200 & 4201h.

3.Execute the program.

4.The output LCM value stored in a location 4500h(msb)& 4501h(lsb).

PROGRAM:

Memory

Location


4100 79 01 MOV R1, 01H initialize

counter

4102 90 42 00 MOV DPTR, #4200H get a 1st input


4106 FA MOV R2, A

4107 90 42 01 MOV DPTR, #4201H get a 2nd input


410B FB MOV R3, A

410C L1: EA MOV A, R2

410D 89 70 MOV B, R1 multiply 2nd value to

410F A4 MUL AB counter

4110 FE MOV R6, A

4111 AF F0 MOV R7, B

4113 8B F0 MOV B, R3

4115 84 DIV AB output divide by

4116 E5 F0 MOV B, A

4118 60 03 JZ RESULT remainder store

411A 09 INC R1

411B 80 EF SJMP L1 go to loop

411D RESULT: 90 45 00 MOV DPTR, #4500H output msb value

4120 EF MOV A, R7


4122 90 45 01 MOV DPTR, #4501H output lsb value

4125 EE MOV A, R6




PROGRAM:

Memory

Location


4100 90 42 00 MOV DPTR, #4200H Get a 1st input


4104 FB MOV R0, A

4105 90 42 01 MOV DPTR, #4201H get a 2nd


4109 F9 MOV R1, A

410A 70 00 MOV R5, #00H

410C 7A 01 MOV R2, #01H

410E TOP1: C3 CLR C clear the carry

410F EA MOV A, R2 check given

data’s

4110 98 SUBB A, R0 are equal to 1

4111 60 1B JZ TOPY

4113 EA MOV A, R2 if yes go to

TOPY.

4114 99 SUBB A, R1

4115 60 17 JZ TOPY

4117 E8 MOV A, R0

4118 8A F0 MOV B, R2

411A 84 DIV AB

411B E5 F0 MOV A, B

411D B4 00 0B CJNE A, #00H, TOPX

4120 E9 MOV A, R1

4121 8A F0 MOV B. R2

4123 84 DIV AB

4124 E5 F0 MOV A, B

4126 B4 00 02 CJNE A, #00H, TOPX

4129 EA MOV A, R2

412A FD MOV R5. A

412B TOPX: 0A INC R2

412C 80 E0 SJMP TOP1

412E TOPY: ED MOV A, R5

412F 90 45 00 MOV DPTR, #4500H

4132 F0 MOVX @DPTR, A Output


ML Input

4200 09

4201 0C(hex)= 12 (decimal)

ML Output

4500 8

4501 24 (hex)

=36(decimal)


Result: Thus an assembly language program is written to find LCM and GCD of a given data and executed

successfully

ML Input

4200 04

4201 02

ML Output

4500 02


1. What is advantage of serial communication?

The fact that in serial communication a single data line is used instead of the 8-bit data

line of parallel communication makes it not only much cheaper but also makes it possible for

two computers located in two different cities to communicate over the telephone.

2. What is the purpose of modem?

When the distance is short, the digital signal can be transferred as it is on a simple

wire and requires no modulation. However for long distance data transfers using

communication lines such as telephone, serial data communication requires modem to

modulate ( converts from 0s and 1s to audio tones) and demodulate (converting from audio

tones to 0s and 1s).

3. What is Half duplex and Full duplex transmission?

Duplex transmissions can be half or full duplex, depending on whether or not the data

transfer can be simultaneous. If data is transmitted one way at a time, it is referred to as half

duplex. If the data can go both ways at the same time, it is full duplex.


1. Define baud rate.

The rate of data transfer in serial data communication is stated in bps( bits per second).

Another widely used terminology for bps is baud rate.

2. What is RS 232?

RS232 is the most widely used serial I/O interfacing standard. This standard is used

in PCs and numerous types of equipment.

3. What is SBUF register?

SBUF register is an 8-bit register used solely for serial communication in the 8051.

For a byte of data to be transferred via TXD line, it must be placed in the SBUF register. Similarly,

SBUF holds the byte of data when it is received by the 8051’s RxD line.

EX.NO: 10 TRANSFER DATA SERIALLY BETWEEN TWO KITS

Aim:

To write an assembly language program Transmitting and Receiving the data between two kits.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Initialize TMOD with 20H

2. Set the values for TCON and SCON

3. Set the input address to DPTR

4. Based on the bit value on SCON store the data in SBUF

5. Increment DPTR and check for the loop end value

PROGRAM FOR RECEIVER.

Memory

Location


4100 75 89 20 MOV TMOD, #20H

4103 75 8D A0 MOV TH1, #0A0H

4106 75 8B 00 MOV TL1, #00H

4109 75 88 40 MOV TCON, #40H

410C 75 98 58 MOV SCON, #58H

410F 90 45 00 MOV DPTR, #4500H Output

4112 RELOAD 7D 05 MOV R5, #05H

4114 CHECK 30 98 FD JNB SCON.0, CHECK

4117 C2 98 CLR SCON.0

4119 E5 99 MOV A, SBUF


411C A3 INC DPTR

411D B4 3F F2 CJNE A, #3FH,

RELOAD

4120 DD F2 DJNZ R5, CHECK

4122 E4 CLR A

4123 12 00 20 LCALL 0020H

Algorithm for Transmitter:

1. Initialize TMOD with 20H

2. Set the values for TCON and SCON

3. Set the input address to DPTR

4. Based on the bit value on SCON store the data in SBUF and move the data to

register ‘A’.

5. Increment DPTR and check for the loop end value

PROGRAM FOR TRANSMITTER.

Memory

Location


4100 75 89 20 MOV TMOD, #20H

4103 75 8D A0 MOV TH1, #0A0H

4106 75 8B 00 MOV TL1, #00H

4109 75 88 40 MOV TCON, #40H

410C 75 98 58 MOV SCON, #58H

410F 90 45 00 MOV DPTR, #4500H Input

4112 RELOAD 7D 05 MOV R5, #05H

4114 REPEAT E0 MOVX A, @DPTR

4115 F5 99 MOV SBUF, A

4117 CHECK 30 99 FD JNB SCON.1, CHECK

411A C2 99 CLR SCON.1

411C A3 INC DPTR

411D B4 3F F2 CJNE A, #3FH,

RELOAD

4120 DD F2 DJNZ R5, REPEAT

4122 E4 CLR A

4123 12 00 20 LCALL 0020H


Sl.No Transmitter Input (Hex

Values) Input Address 4500

Receiver Output (Hex Values)

1 00 00

2 11 11

3 22 22

4 33 33

Result: Thus an assembly language program displaying characters on seven segment display has been

executed.

PRE LAB QUESTIONS AND ANSWERS

1. What is EPROM and UV-EPROM?

EPROM was invented to allow making changes in the contents of PROM after it is burned.

UV-EPROM is Ultra –Violet EPROM chips have window that is used to shine UV radiation

to erase its contents.

2. Define SRAM.

Storage cells in static RAM memory are made of flip-flops and therefore do not require

refreshing in order to keep their data.

3. Define DRAM.

In DRAM storage cells are made up of capacitors hence it need refreshing circuitry due to

leakage. In contrast to SRAM which made up of flip flops it is capacitor.


1. What is USART?

It is a programmable device. Its function and specification for serial I/O can be determined

by writing instructions in its internal registers. The Intel 8251A USART is a device widely

used in serial I/O

2. Write the features of 8255A.

The 8255A has 24 I/O pins that can be primarily grouped primarily in two 8-bit Parallel ports:

A and B, with eight bits as port C. The 8-bits of port C can be used as two 4-bit ports: CUPPER

CU and CLOWER CL.

3. What is BSR mode?

All functions of 8255 are classified according to 2 modes. In the controlword, if D7 = 0, then

it represents bit set reset mode operation. The BSR mode is used to set or reset the bits in port

C.

EX.NO: 11 SEVEN SEGMENT DISPLAY

Aim:

To write an assembly language program to display characters on a seven display interface.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Enter a program.

2. Initialize number of digits to Scan

3. Select the digit position through the port address C0

4. Display the characters through the output at address C8.

5. Check whether all the digits are display.

6. Repeat the Process.

PROGRAM:

Memory

Location


4100 START 90 41 2B MOV DPTR, #TABLE Display message

4103 AA 82 MOV R2, DPL

4105 AB 83 MOV R3, DPH

4107 78 07 MOV R0, #07H

4109 7F 08 MOV R7, #08H Initialize no.of digits to

scan

410B L1 E8 MOV A, R0 Select digit position

410C 90 FF C0 MOV DPTR, #FFC0H

410F F0 MOVX @DPTR, A

4110 8A 82 MOV DPL, R2

4112 8B 83 MOV DPH, R3


4115 90 FF C8 MOV DPTR, #FFC8H


4119 12 41 22 LCALL DELAY

411C 0A INC R2

411D 18 DEC R0 Check if 8 digits are

displayed

411E DF EB DJNZ R7, L1 If not repeat

4120 21 00 AJMP START Repeat from the 1st digit

4122 DELAY 7C 02 MOV R4, #02H

4124 L3 7D FF MOV R5, #FFH

4126 L2 DD FE DJNZ R5, L2

4128 DC FA DJNZ R4, L3

412A 22 RET

412B TABLE 3E 06 00 55 DB 3EH, 06H, 00H, 55H

412F 06 39 50 3F DB 06H, 39H, 50H, 3FH

4133 END


Input (hex Values) Output (Characters)

79 E

79 E

79 E

Result:

Thus an assembly language program displaying characters on seven segment display has been

executed.


1. Explain the various steps involved when executing CALL instruction.

The Call instruction is used to transfer the program control to a subroutine or subprogram.

There are 4 internal steps are performed when this instruction is

executed.

CALL 16 bit addr: This instruction transfers the program sequence to a subroutine

address unconditionally. The internal operations performed are:

i. saves the contents of program counter on stack.

ii. decrements the stack pointer register by 2.

iii. Jumps unconditionally to memory location specified by the second and

third byte.

2. What is the use of PUSH and POP instruction?

PUSH rp: This instruction copies the contents of specified register pair on the stack.

POP rp: This instruction is used to retrieve the contents of specified register pair from

stack.

3. What is a subroutine program?

A subroutine is a group of instructions written separately from the main program to

perform a function that occurs repeatedly in the main program. Thus subroutines avoid

the repetition of same set of instructions in the main program.


1. How the instructions are classified according to word size?

i. one-word or one byte instructions

ii. two-word or two byte instructions

iii. three-word or three byte instructions

2. What is mode 0 operation of 8255.

In this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-bit

ports. Each port can be programmed to function as an input port or an output port. The input/

output features in mode 0 as follows: i. outputs are latched ii. inputs are not latched iii. ports

do not have handshake or interrupt capability.

3. What are the modes of operation supported by 8255?

i. Bit set reset mode(BSR) ii. I/O mode Mode 0 Mode1 Mode2

EX.NO:12 8-BIT DIGITAL TO ANALOG CONVERTER

Aim:

To write an assembly language program to display Characters on a seven display interface.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Move the Port Address of DAC 2 FFC8 to the DPTR.

2. Move the Value of Register A to DPTR and then Call the delay.

3. Move the Value of Register A (FFh) to DPTR and the call the dalay.

4. Repeat the steps 2 and 3.

SQUARE WAVEFORM

START

Initialize A as 00

Output the control word through 8-bit port address

Initialize A as FF

Output the control word through 8-bit port address

Call Delay

Call Delay

PROGRAM TO GENERATE SQUARE WAVEFORM

Memory

Location



4103 START: 74 00 MOV A, #00H



4109 74 FF MOV A, #FFH


410C 12 41 12 LCALL DELAY

410F 02 41 03 LJMP STTART

4112 Delay 79 05 MOV R1, #05H

4114 Loop 7A FF MOV R2, #FFH

4116 Here DA FE DJNZ R2, HERE

4118 D9 FA DJNZ R1, LOOP

411A 22 RET

411B 80 E6 SJMP START

DELAY

Decrement reg B contents by 01

Initialize reg R1 as FFH

Initialize R2 reg as 05H

If R2=0?

Decrement R1 reg contents by 01

If

R1=0?

RET

Yes

No

Yes

No

SQUARE WAVE

SAW-TOOTH WAVEFORM

PROGRAM TO GENERATE SAW-TOOTH WAVEFORM

Memory

Location



4103 74 00 MOV A, #00H


4106 04 INC A

4107 80 FC SJMP LOOP

SAW TOOTH WAVE

START

Initialize the accumulator as ‘00’

output control word through 8-bit port address

Decrement the accumulator contents by 01

If

A=0

No Yes

TRIANGULAR WAVEFORM

PROGRAM TO GENERATE TRIANGULAR WAVEFORM

Memory

Location



4103 74 00 MOV A, #00H


4106 04 INC A

4107 70 FC JNZ LOOP1

4109 74 FF MOV A, #FFH


410C 14 DEC A

410D 70 FC JNZ LOOP2

410F 02 41 03 LJMP START

START

Initialize the value of ‘L’reg as ‘00’

Move the values of ‘L’reg to ‘A’

Output the control word for control signal

Increment the value of ‘L’ by 01

L =0?

Set the value of ‘L’ as ‘FF’

Move the ‘L’reg value to accumulator

Output the control word

No Yes

L =0?

Decrement reg L contents by 01

Yes

No

TRIANGULAR WAVE

Result: Thus an assembly language program for Digital to Analog has been executed.


1. What is NV-RAM?

Like other RAMs, it allows the CPU to read and write to it, but when the power is turned

off the contents are not lost. It combines the best of RAM and ROM : the read and write

ability of RAM, plus non-volatility of ROM.

2. What is the use of PUSH and POP instruction?

PUSH rp: This instruction copies the contents of specified register pair on the stack.

POP rp: This instruction is used to retrieve the contents of specified register pair from

stack.

3. What is a subroutine program?

A subroutine is a group of instructions written separately from the main program to

perform a function that occurs repeatedly in the main program. Thus subroutines avoid

the repetition of same set of instructions in the main program.


1. How the instructions are classified according to word size?

i. one-word or one byte instructions

ii. two-word or two byte instructions

iii. three-word or three byte instructions

2. What is mode 0 operation of 8255.

In this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-bit

ports. Each port can be programmed to function as an input port or an output port. The input/

output features in mode 0 as follows: i. outputs are latched ii. inputs are not latched iii. ports

do not have handshake or interrupt capability.

3. What are the modes of operation supported by 8255?

i. Bit set reset mode(BSR) ii. I/O mode Mode 0 Mode1 Mode2

EX.NO:13 8-BIT ANALOG TO DIGITAL CONVERTER

Aim:

To write an assembly language program to display Characters on a seven display interface.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Make ALE low/high by moving the respective data from A register to DPTR.

2. Move the SOC( Start Of Conversion) data to DPTR from FFD0

3. Check for the End Of Conversion and read data from Buffer at address FFC0

4. End the Program.

START

Load the control word necessary for generation of ALE signal to control register

Initialize A as 01h and output through 8-bit port address

Perform NOP in order to access the channel of ADC

Perform AND operation on contents of A reg with 01H

Initialize A as 00h and output through 8-bit port address

Get the input from 8-bit port address

If A

=0?

Get input from 8-bit port address

Move content of reg A to reg B

Perform AND operation on contents of A reg with 0FH

Store the content of A in memory

Move content of reg B to reg A

Perform AND operation on contents of A reg with F0H

Rotate content of A such that upper and lower nibbles get exchanged

Store the content of A in memory

Initialize reg A as 03H and C as 08H

Load HL reg pair with address of MSB

Call service Subroutine

YES

NO

PROGRAM:

Port Address for 74LS174 Latch: FFC8

Port Address for SOC: FFD0

Port Address for EOC 1: FFD8

Port Address for 74LS 244 Buffer: FFC0

Memory

Location


4100 90 FF C8 MOV DPTR, #FFC8

4103 74 10 MOV A, #10 Select Channel 0

4105 F0 MOVX @DPTR, A Make ALE Low

4106 74 18 MOV A, #18 Make ALE High


4109 90 FF D0 MOV DPTR, #FFD0

410C 74 01 MOV A, #01 SOC Signal High

410E F0 MOVX @DPTR, A

410F 74 00 MOV A, #00 SOC Signal Low


4112 90 FF D8 MOV DPTR, #FFD8


4116 30 E0 FC JNB E0, WAIT Check For EOC

4119 90 FF C0 MOV DPTR, #FFC0 Read ADC Data

411C E0 MOVX A, @DPTR

4110 90 41 50 MOV DPTR, #4150 Store the Data


4121 90 FE SJMP HERE

Result: Thus an assembly language program is executed for analog to digital conversion.


1. What is an interrupt?

In the interrupt method, whenever any device needs its service, the device notifies the

microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal, the

microcontroller interrupts whatever it is doing and serves the device.

2. Define Polling.

In polling, the microcontroller continuously monitors the status of a given device;

when condition is met, it performs the service. After that, it moves on to monitor the next

device until everyone is serviced.

3. What is the disadvantage of polling?

It is not possible to assign priority since it checks all devices in a round robbin fashion.

The polling method wastes much of the microcontroller’s time by polling devices that do

not need service.


1. What is advantage of interrupts?

The advantage of interrupts is that the microcontroller can serve many devices. Each

device can get the attention of the microcontroller based on the priority assigned to it. Most

importantly in the interrupt method the microcontroller can also ignore a device request for

service.

2. What is interrupt vector table?

For every interrupt, there must be an interrupt service service routine (ISR), or

interrupt handler. For every interrupt, there is fixed location in memory that holds the address

of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called

interrupt vector table.

3. How many interrupts are in 8051?

6 interrupts.

Reset

Two interrupts are set aside for timers

Two interrupts are set aside for hardware external hardware interrupts.

Serial communication has single interrupt that belongs to both receive and transfer

data.

EX.NO:14 INTERNAL INTERRUPT GENERATION

Aim:

To write an assembly language program for Internal Interrupt.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Move the value 081H to the Interrupt Enable pin to enable it.

2. Press INT0 interrupt is enabled. LED’s are on.

3. End the Program.

PROGRAM:

Memory

Location


4100 75 89 10 MOV TMOD, #10H TIMER 1 MODE 0

4103 MOV IE, #88H TIMER 1 Overflow

Interrupt

4106 MOV TH1,#00H

4109 MOV TL1,#00H

410C SETB TR1 Start the timer

410E L1: JNB TF1,L1 check the timer overflow

4111 CLR TR1 clear the timer overflow

4113 CLR TF1

4115 L2: SJMP L2

Interrupt Service Routine

5030 74 12 MOV A,#12

5032 90 45 00 MOV DPTR,#FF20H



Result: Thus an assembly language program for the internal interrupt has been done.


1. What is stepper motor?

Stepper motors are electromagnetic incremental devices that convert electric pulses

to shaft motion (rotation). These motors rotate a specific number of degrees as a respond

to each input electric pulse.

2. Define Step angle.

The angle through which the motor shaft rotates for each command pulse is called

step angle.

3. What are the applications of stepper motor?

Computer peripherals, textile industry, IC fabrication, robotics etc.,


1. What are the types of stepper motor?

VR Stepper motor( Single Stack and Multi Stack)

Permanent Magnet stepper motor

Hybrid Stepper Motor

2. Brief 2-phase on mode?

EX.NO:15 SPEED CONTROL OF STEPPER MOTOR

Aim:

To write an assembly program to make the stepper motor run in forward and reverse direction.

Apparatus required:

Stepper motor

8051 microprocessor kit

(0-5V) power supply

Algorithm:

1. Fix the DPTR with the Latch Chip address FFC0

2. Move the values of register A one by one with some delay based on the 2-Phase

switching Scheme and repeat the loop.

3. For Anti Clockwise direction repeat the step 3 by reversing the value sequence.

4. End the Program

START

Load ‘DPTR’ register pair with port address FFC0.

Move the accumulator value to port address FFC0

Set the delay by using LCALL

(R1) = 0?

Decrement ‘R0’ register content by one.

Decrement ‘R1’ by one

R0 = 0?

Move immediate value one by one 09, 05, 06, 0A to accumulator for every LCALL.

NO

YES

YES

NO

Memory

Location


4100 90 FF C0 MOV DPTR, #FFC0

4103 74 09 MOV A, #09



4109 74 05 MOV A, #05



410F 74 06 MOV A, #06



4115 74 0A MOV A, #0A



412B 80 FE SJMP 4100

DELAY:

4500 78 55 MOV R0, #55

4502 L2 79 FF MOV R1, #FF

4504 L1 D9 FE DJNZ R1, L1

4507 D8 FA DJNZ R0, L2

450A 22 RET

Forward Direction

Value

0A

06

05

09

Reverse Direction

Value

09

05

06

0A

Result:

Thus an assembly language program to control of stepper motor was executed successfully

using 8051 Microcontroller kit.


1. What is control word?

The contents of this register, called the control word, specify an I/O function for each

port.

2. How many modes of operation are available for 8255 ?

There are three modes of operation Mode0,1 and 2.

3. What is BSR mode in 8255?

The BSR mode is concerned only with the eight bits of port C, which can be set or

reset by writing an appropriate control word in the control register. The control word with

bit D7 = 0 is recognized as a BSR control word and it does not alter any previously

transmitted control word bit D7=1.


1. What is 8254?

The 8254 is a programmable timer/counter is functionally similar to the software

designed counters and timers. It generates accurate time delays and can be used for

applications such as real time clock.

2. What is 8259A?

It is a programmable interrupt controller designed to work with intel microprocessors

8085,8086 and 8088. It is used for managing interrupts.

3. What is 8237?

It is a programmable Direct Memory Access controller (DMA controller) housed in a

40 pin package. It has four independent channels with each channel capable of transferring

64K bytes.

EX.NO:16 TRAFFIC LIGHT CONTROLLER

Aim:

To write an assembly language program to interface and program a traffic light controller.

Apparatus required:


(0-5V) DC battery

Algorithm:

1. Fix the control the control and move the control word to control register.

2. Move the Traffic Light LED Position values to Port A, Port B and Port C

respectively based on the logic.

3. Fix the delay based on the requirement.

3. Execute the program.

PROGRAM:

4100 ORG 4100

CONTRL EQU 0FF0FH

PORT A EQU 0FF0CH

PORT B EQU 0FF0DH

PORT C EQU 0FF0EH

Memory

Location


4100 74 80 MOV A, #80H

4102 90 FF 0F MOV DPTR, #CONTRL


4106 START 7C 04 MOV R4, #04H

4108 90 41 9B MOV DPTR, #LOOK1

410B AA 83 MOV R2, DPH

410D AB 82 MOV R3, DPL

410F 90 41 8F MOV DPTR, #LOOK

4112 A8 83 MOV R0, DPH

4114 A9 82 MOV R1, DPL

4116 GO E0 MOVX A, @DPTR

4117 A8 83 MOV R0, DPH

4119 A9 82 MOV R1, DPL

411B 90 FF 0C MOV DPTR, #PORT A

411E F0 MOVX @DPTR, A

411F 09 INC R1

4120 88 83 MOV DPH, R0

4122 89 82 MOV DPL, R1


4125 A8 83 MOV R0, DPH

4127 A9 82 MOV R1, DPL

4129 90 FF 0D MOV DPTR, #PORT B

412C F0 MOVX @DPTR, A

412D 09 INC R1

412E 88 83 MOV DPH, R0

4130 89 82 MOV DPL, R1


4133 A8 83 MOV R0, DPH

4135 A9 82 MOV R1, DPL

4137 90 FF 0E MOV DPTR, #PORT C

413A F0 MOVX @DPTR, A

413B 09 INC R1


413F 8A 83 MOV DPH, R2

4141 8B 82 MOV DPL, R3


4144 AA 83 MOV R2, DPH

4146 AB 82 MOV R3, DPL

4148 90 FF 0C MOV DPTR, #PORT A


414C 0B INC R3

414D 8A 83 MOV DPH, R2

414F 8B 82 MOV DPL, R3




4156 90 FF 0D MOV DPTR, #PORT B


415A 0B INC R3

415B 8A 83 MOV DPH, R2

415D 8B 82 MOV DPL, R3

415F E0 MOVX A, @DPTR



4164 90 FF 0E MOV DPTR, #PORT C


4168 0B INC R3

4169 12 41 82 LCALL DELAY1

416C 88 83 MOV DPH, R0

416E 89 82 MOV DPL, R1

4170 DC A4 DJNZ R4, GO

4172 12 41 06 LCALL START

4175 DELAY 7D 12 MOV R5, #12H

4177 L3 7E FF MOV R6, #0FFH

4179 L2 7F FF MOV R7, #0FFH

417B L1 DF FE DJNZ R7, L1

417D DE FA DJNZ R6, L2

417F DD F6 DJNZ R5, L3

4181 22 RET

4182 DELAY1 7D 12 MOV R5, #12H

4184 L6 7E FF MOV R6, #0FFH

4186 L5 7F FF MOV R7, #0FFH

4188 L4 DF FE DJNZ R7, L4

418A DE FA DJNZ R6, L5

418C DD F6 DJNZ R5, L6

418E 22 RET

418F LOOK 44 27 12 DB 44H, 27H, 12H

4192 92 2B 10 DB 92H, 2BH, 10H

4195 84 9D 10 DB 84H, 9DH, 10H

4198 84 2E 48 DB 84H, 2EH, 48H

419B LOOK1 48 27 12 DB 48H, 27H, 12H

419E 92 4B 10 DB 92H, 4BH, 10H

41A1 84 9D 20 DB 84H, 9DH, 20H

41A4 04 2E 49 DB 04H, 2EH, 49H

Result: Thus an assembly language program for the Traffic Light Control has been executed.

EX.NO:17 STUDY OF INTERRUPT

Real Time Embedded System design requires that I/O devices receive servicing in an

efficient manner so that large amounts of the total system tasks can be assumed by the processor

with little or no effect on throughput. The most common method of servicing such devices is the

polled approach. This is where the processor must test each device in sequence and in effect

“ask” each one if it needs servicing. It is easy to see that a large portion of the main program is

looping through this continuous polling cycle and that such a method would have a serious,

detrimental effect on system throughput, thus, limiting the tasks that could be assumed by the

microcomputer and reducing the cost effectiveness of using such devices. A more desirable method

would be one that would allow the microprocessor to be executing its main program and only stop

to service peripheral devices when it is told to do so by the device itself. In effect, the method

would provide an external asynchronous input that would inform the processor that it should

complete whatever instruction that is currently being executed and fetch a new routine that will

service the requesting device. Once this servicing is complete, however, the processor would

resume exactly where it left off. This can be effectively handled by interrupts.

A signal informing a program or a device connected to the processor that an event has occurred.

When a processor receives an interrupt signal, it takes a specified action depending on the priority

and importance of the entity generating the signal. Interrupt signals can cause a program to suspend

itself temporarily to service the interrupt by branching into another program called Interrupt

Service Subroutines (ISS) for the specified device which has caused the interrupt.

Types of Interrupts

Interrupts can be broadly classified as

- Hardware Interrupts: These are interrupts caused by the connected devices.

- Software Interrupts: These are interrupts deliberately introduced by software instructions

to generate user defined exceptions

- Trap: These are interrupts used by the processor alone to detect any exception such as divide

by zero

http://www.webopedia.com/TERM/I/program.html

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http://www.webopedia.com/TERM/I/event.html

http://www.webopedia.com/TERM/I/event.html

Depending on the service the interrupts also can be classified as

- Fixed interrupt

• Address of the ISR built into microprocessor, cannot be changed

• Either ISR stored at address or a jump to actual ISR stored if not enough bytes available

- Vectored interrupt

• Peripheral must provide the address of the ISR

• Common when microprocessor has multiple peripherals connected by a system bus

• Compromise between fixed and vectored interrupts

– One interrupt pin

– Table in memory holding ISR addresses (maybe 256 words)

– Peripheral doesn’t provide ISR address, but rather index into table

• Fewer bits are sent by the peripheral

• Can move ISR location without changing peripheral

Maskable vs. Non-maskable interrupts

– Maskable: programmer can set bit that causes processor to ignore interrupt

• This is important when the processor is executing a time-critical code

– Non-maskable: a separate interrupt pin that can’t be masked

• Typically reserved for drastic situations, like power failure requiring immediate backup

of data to non-volatile memory

Example: Interrupt Driven Data Transfer (Fixed Interrupt)

Fig.1(a) shows the block diagram of a system where it is required to read data from a input port

P1, modify (according to some given algorithm) and send to port P2. The input port

generates data at a very slow pace. There are two ways to transfer data

(a) The processor waits till the input is ready with the data and performs a read operation from

P1 followed by a write operation to P2. This is called Programmed Data Transfer (b) The

other option is when the input/output device is slow then the device whenever is ready interrupts

the microprocessor through an Int pin as shown in Fig.1. The processor which may be otherwise

busy in executing another program (main program here) after receiving the interrupts calls an

Interrupt Service Subroutine (ISR) to accomplish the required data transfer. This is known as

Interrupt Driven Data Transfer.

Interrupts in a Typical Microcontroller (8051)

The 8051 has 5 interrupt sources: 2 external interrupts, 2 timer interrupts, and the serial port

interrupt.

These interrupts occur

because of

1. timers overflowing

2. receiving character via the serial port

3. transmitting character via the serial port

4. Two “external events”

Interrupt Enables

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in a

Special Function Register (SFR) named IE (Interrupt Enable). This register also contains a

global disable bit, which can be cleared to disable all interrupts at once.

Interrupt Priorities

Each interrupt source can also be individually programmed to one of two priority levels

by setting or clearing a bit in the SFR named IP (Interrupt Priority). A low-priority interrupt

can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A

high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt

requests of different priority levels are received simultaneously, the request of higher priority

is serviced. If interrupt requests of the same priority level are received simultaneously, an

internal polling sequence determines which request is serviced. Thus within each priority

level there is a second priority structure determined by the polling sequence. In operation, all

the interrupt flags are latched into the interrupt control system during State 5 of every

machine cycle. The samples are polled during the following machine cycle. If the flag for

an enabled interrupt is found to be set (1), theinterrupt system generates a CALL to the

appropriate location in Program Memory, unless some other condition blocks the interrupt.

Several conditions can block an interrupt, among them that an interrupt of equal or higher

priority level is already in progress. The hardware-generated CALL causes the contents

of the Program Counter to be pushed into the stack, and reloads the PC with the beginning

address of the service routine.

INT0: External Interrupt0

INT1: External

Interrupt 1

TF0: Timer 0 Interrupt

TF1: Timer 1

Interrupt

RI,TI: Serial Port Receive/Transmit

Interrupt

The service routine for each interrupt begins at a fixed location (fixed address interrupts).

Only the Program Counter (PC) is automatically pushed onto the stack, not the Processor

Status Word (which includes the contents of the accumulator and flag register) or any other

register. Having only the PC automatically saved allows the programmer to decide how

much time should be spent saving other registers. This enhances the interrupt response time,

albeit at the expense of increasing the programmer’s burden of responsibility. As a result,

many interrupt functions that are typical in control applications toggling a port pin for

example, or reloading a timer, or unloading a serial buffer can often be completed in less time

than it takes other architectures to complete.

Interrupt Number

Interrupt Vector Address

Description

0 0003h EXTERNAL 0

1 000Bh TIMER/COUNTER 0

2 0013h EXTERNAL 1

3 001Bh TIMER/COUNTER 1

4 0023h SERIAL PORT

Simultaneously occurring interrupts are serviced in the following order:

1. External 0 Interrupt

2. Timer 0 Interrupt 3. External 1 Interrupt

4. Timer 1 Interrupt

5. Serial Interrupt

The Bus Arbitration

When there is more than one device need interrupt service then they have to be connected in

specific manner. The processor responds to each one of them. This is called Arbitration.

The method can be divided into following

• Priority Arbiter

• Daisy Chain Arbiter

Let us assume that the Priority of the devices are Device1 > Device

2 …

1. The Processor is executing its program.

2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so

asserts

Ireq2.

3. Priority arbiter sees at least one Ireq input asserted, so asserts Int.

4. Processor stops executing its program and stores its state.

5. Processor asserts Inta.

6. Priority arbiter asserts Iack1 to acknowledge Peripheral1.

7. Peripheral1 puts its interrupt address vector on the system bus

8. Processor jumps to the address of ISR read from data bus, ISR executes and returns

(and completes handshake with arbiter).

Thus in case of simultaneous interrupts the device with the highest priority will be

served.

Daisy Chain Interrupts

In this case the peripherals needing interrupt service are connected in a chain as shown in

Fig.15.6. The requests are chained and hence any device interrupting shall be transmitted to

the CPU in a chain.

Let us assume that the Priority of the devices are Device1 > Device 2 …

1. The Processor is executing its program.

2. Any Peripheral needs servicing asserts Req out. This Req out g o e s to the Req in

of the subsequent device in the chain

3. Thus the peripheral nearest to the μC asserts Int.

4. The processor stops executing its program and stores its state. 5. Processor asserts Inta the nearest device.

6. The Inta passes through the chain till it finds a flag which is set by the device which

has generated the interrupt.

7. The interrupting device sends the Interrupt Address Vector to the processor for its interrupt service subroutine.

8. The processor jumps to the address of ISR read from data bus, ISR executes and

returns.

9. The flag is reset. The processor now checks for the next device which has interrupted simultaneously.

In this case The device nearest to the processor has the highest

priority The service to the subsequent stages is interrupted if the chain is broken at one

place.

Handling a number of Interrupts by Intel 8259 Programmable Interrupt Controller

The Programmable Interrupt Controller (PlC) functions as an overall manager in an Interrupt-

Driven system. It accepts requests from the peripheral equipment, determines which of the

incoming requests is of the highest importance (priority), ascertains whether the incoming

request has a higher priority value than the level currently being serviced, and issues an

interrupt to the CPU based on this determination

Each peripheral device or structure usually has a special program or “routine” that is

associated with its specific functional or operational requirements; this is referred to as a

“service routine”. The PlC, after issuing an interrupt to the CPU, must somehow input

information into the CPU that can point (vector) the Program Counter to the service routine

associated with the requesting device. The PIC manages eight levels of requests and has built-in features for expandability to other

PIC (up to 64 levels). It is programmed by system software as an I/O peripheral. The priority

modes can be changed or reconfigured dynamically at any time during main program

operation.

Interrupt Request Register (IRR) and In-Service Register (ISR)

The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt

Request Register (lRR) and the In- Service Register (lSR). The IRR is used to indicate all

the interrupt levels which are requesting service, and the ISR is used to store all the interrupt

levels which are currently being serviced.

Priority Resolver

This logic block determines the priorities of the bits set in the lRR. The highest priority

is selected and strobed into the corresponding bit of the lSR during the INTA sequence.

Interrupt Mask Register (IMR)

The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on

the output of the IRR. Masking of a higher priority input will not affect the interrupt request

lines of lower priority.

Data Bus Buffer

This 3-state, bidirectional 8-bit buffer is used to interface the PIC to the System Data

Bus. Control words and status information are transferred through the Data Bus Buffer.

Read/Write Control Logic

The function of this block is to accept output commands from the CPU. It contains the

Initialization Command Word (lCW) registers and Operation Command Word (OCW)

registers which store the various control formats for device operation. This function block

also allows the status of the PIC to be transferred onto the Data Bus. This function block

stores and compares the IDs of all PICs used in the system. The associated three I/O pins

(CAS0- 2) are outputs when the 8259 is used as a master and are inputs when the 8259 is

used as a slave. As a master, the

8259 sends the ID of the interrupting slave device onto the CAS0 - 2 lines. The slave, thus

selected will send its preprogrammed subroutine address onto the Data Bus during the next

one or two consecutive INTA pulses.

Fig.15.10 shows the daisy chain connection of a number of PICs. The extreme right PIC interrupts the processor. In this figure the processor can entertain up to 24 different interrupt

requests. The SP/EN signal has been connected to Vcc for the master and grounded for

the slaves.

Software Interrupts

These are initiated by the program by specific instructions. On encountering such instructions,

the

CPU executes an Interrupt service subroutine.

Result: Thus study of interrupts was completed.

EX.NO: 18 INTEL 8255: (PROGRAMMABLE PERIPHERAL INTERFACE)

The 8255A is a general purpose programmable I/O device designed for use with Intel

microprocessors. It consists of three 8-bit bidirectional I/O ports (24I/O lines) that can be

configured to meet different system I/O needs. The three ports are PORT A, PORT B & PORT

C. Port A contains one 8-bit output latch/buffer and one 8-bit input buffer. Port B is same as

PORT A or PORT B. However, PORT C can be split into two parts PORT C lower (PC0-PC3)

and PORT C upper (PC7-PC4) by the control word. The three ports are divided in two groups

Group A (PORT A and upper PORT C) Group B (PORT B and lower PORT C). The two

groups can be programmed in three different modes. In the first mode (mode 0), each group

may be programmed in either input mode or output mode (PORT A, PORT B, PORT C lower,

PORT C upper). In mode 1, the second’s mode, each group may be programmed to have 8-

lines of input or output (PORT A or PORT B) of the remaining 4-lines (PORT C lower or

PORT C upper) 3-lines are used for hand shaking and interrupt control signals. The third mode

of operation (mode 2) is a bidirectional bus mode which uses 8-line (PORT A only for a

bidirectional bus and five lines (PORT C upper 4 lines and borrowing one from other group)

for handshaking. The 8255 is contained in a 40-pin package, whose pin out is shown below:

Functional Description:

This support chip is a general purpose I/O component to interface peripheral equipment

to the microcomputer system bus. It is programmed by the system software so that normally

no external logic is necessary to interface peripheral devices or structures.

Data Bus Buffer:

It is a tri-state 8-bit buffer used to interface the chip to the system data bus. Data is

transmitted or received by the buffer upon execution of input or output instructions by the CPU.

Control words and status information are also transferred through the data bus buffer. The data

lines are connected to BDB of µp.

Read/Write and logic control:

The function of this block is to control the internal operation of the device and to control

the transfer of data and control or status words. It accepts inputs from the CPU address and

control buses and in turn issues command to both the control groups.

Chip Select:

A low on this input selects the chip and enables the communication between the 8255

A& the CPU. It is connected to the output of address decode circuitry to select the device when

it (Read). A low on this input enables the 8255 to send the data or status information to the

CPU on the data bus.

(Write): A low on this input pin enables the CPU to write data or control words into the 8255

A.

A1, A0 port select:

These input signals, in conjunction with the and inputs, control the selection of one of

the three ports or the control word registers. They are normally connected to the least significant

bits of the address bus (A0 and A1). Following Table gives the basic operation,

RESET:

A high on this input pin clears the control register and all ports (A, B & C) are initialized

to input mode. This is connected to RESET OUT of 8255. This is done to prevent destruction

of circuitry connected to port lines. If port lines are initialized as output after a power up or

reset, the port might try to output into the output of a device connected to same inputs might

destroy one or both of them.

PORTs A, B and C: The 8255A contains three 8-bit ports (A, B and C). All can be configured

in a variety of functional characteristic by the system software.

PORTA: One 8-bit data output latch/buffer and one 8-bit data input latch.

PORT B: One 8-bit data output latch/buffer and one 8-bit data input buffer.

PORT C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).

This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains

a 4-bit latch and it can be used for the control signal outputs and status signals inputs in

conjunction with ports A and B.

Group A& Group B control: The functional configuration of each port is programmed by the

system software. The control words outputted by the CPU configure the associated ports of the

each of the two groups. Each control block accepts command from Read/Write content logic

receives control words from the internal data bus and issues proper commands to its associated

ports. Control Group A – Port A& Port C upper Control Group B – Port B & Port C lower

The control word register can only be written into No read operation if the control word register

is allowed.

Operation Description:

Mode selection: There are three basic modes of operation that can be selected by the

system software.

Mode 0: Basic Input/output

Mode 1: Strobes Input/output

Mode 2: Bi-direction bus. When the reset input goes HIGH all poets are set to mode’0’ as input

which means all 24 lines are in high impedance state and can be used as normal input. After

the reset is removed the 8255A remains in the input mode with no additional initialization.

During the execution of the program any of the other modes may be selected using a single

output instruction. The modes for PORT A& PORT B can be separately defined, while PORT

C is divided into two portions as required by the PORT A and PORT B definitions. The ports

are thus divided into two groups Group A& Group B. All the output register, including the

status flip-flop will be reset whenever the mode is changed. Modes of the two group may be

combined for any desired I/O operation e.g. Group A in mode ‘1’ and group B in mode ‘0’.

The basic mode definitions with bus interface and the mode definition format are given in fig

(a) & (b),

Result : Thus study of 8255 was completed.

EX.NO: 19 DC MOTOR CONTROL USING ARM PROCESSOR

AIM:

Perform DC motor controller experiment with ARM2148 and evaluate the response of

variations.

THEORY:

The reason to control the speed of the engine is to conquer the issue in the industry like

to maintain a strategic distance from machines harms and to stay away from the

moderate ascent time and high overshoot. This is on account of when the beginning

voltage is high, it isn’t reasonable for a machine as it can make machine harms. In this

way, a controller like PID is created to beat this issue.

Three techniques have been used to control the speed of the DC motor, one involving

a PID controller, other involving PWM hysteresis and hardware implementation using

optocoupler sensor. We are going to discuss the theory related to PID controller, PWM

hysteresis and optocoupler sensor. A proportional integral subsidiary controller (PID

controller) is generally utilized as a part of mechanical control frameworks. It is a bland

control circle criticism instrument and utilized as input controller. PID working

standard is that it figures blunder esteem from the handled estimated esteem and the

coveted reference point. Crafted by the controller is to limit the blunder by changing in

the contributions of the framework. In the event that the framework isn‟t plainly known

at that point applying PID controller give the best comes about in the event that it is

tuned legitimately by keeping parameters of the framework as per the idea of the

framework

PROGRAMMING:

General setup:

1.Install KEIL SETUP Ver 5.18Trial from the CD.(Its used for develop the program)

2.Install the FT232 driver from the CD. (Driver setup)

3.Install the Flash Magic Setup from the CD. (It’s used for Execute the program)

4.For detailed information see KEIL μVision 4 Tool and Flash Magic.

5.Install Terminal setup\ teraterm-4.89, it’s only used for serial communication.

PROCEDURE:

6.Connect the 9V adaptor to the ARM2148 Board.

7.Keep the Switch SW21 in ON position.

8.Connect ARM2148 Board’s Lower USB to PC’s USB by using given USB cable.

9.Open Flash Magic and follow the steps1, 2, 3to choose Respective .hex program and step 4,

5 to start.

10. The bottom of Flash Magic page indicates that completed.

11. Set values are adjusted by the following instruction 1as increment button, 2 as decrement

button, 3 as shift button (from right to left), 4 as enter button.

12. The DB- 9 pin and data configuration is listed below.

13. Vary the set value in the lpc2148 board and observe the actual value in LCD.

MODEL OUTPUT

RESULT: Thus the performance of DC motor controller experiment with ARM2148 was

studied.

EX.NO: 20 STUDY OF 8257/8237 DMA CONTROLLER.

Aim:

To study the DMA controller 8257/8237.

Theory:

Following is the sequence of operations performed by a DMA −

Initially, when any device has to send data between the device and the memory, the

device has to send DMA request (DRQ) to DMA controller.

The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to

assert the HLDA.

Then the microprocessor tri-states all the data bus, address bus, and control bus. The

CPU leaves the control over bus and acknowledges the HOLD request through HLDA

signal.

Now the CPU is in HOLD state and the DMA controller has to manage the operations

over buses between the CPU, memory, and I/O devices.

Features of 8257

Here is a list of some of the prominent features of 8257 −

It has four channels which can be used over four I/O devices.

Each channel has 16-bit address and 14-bit counter.

Each channel can transfer data up to 64kb.

Each channel can be programmed independently.

Each channel can perform read transfer, write transfer and verify transfer operations.

It generates MARK signal to the peripheral device that 128 bytes have been transferred.

It requires a single phase clock.

Its frequency ranges from 250Hz to 3MHz.

It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture

The following image shows the architecture of 8257 −

8257 Pin Description

The following image shows the pin diagram of a 8257 DMA controller −

DRQ0−DRQ3

These are the four individual channel DMA request inputs, which are used by the peripheral

devices for using DMA services. When the fixed priority mode is selected, then DRQ0 has the

highest priority and DRQ3 has the lowest priority among them.

DACKo − DACK3

These are the active-low DMA acknowledge lines, which updates the requesting peripheral

about the status of their request by the CPU. These lines can also act as strobe lines for the

requesting devices.

Do − D7

These are bidirectional, data lines which are used to interface the system bus with the internal

data bus of DMA controller. In the Slave mode, it carries command words to 8257 and status

word from 8257. In the master mode, these lines are used to send higher byte of the generated

address to the latch. This address is further latched using ADSTB signal.

IOR

It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal

registers of 8257 in the Slave mode. In the master mode, it is used to read data from the

peripheral devices during a memory write cycle.

IOW

It is an active low bi-direction tri-state line, which is used to load the contents of the data bus

to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal

count register. In the master mode, it is used to load the data to the peripheral devices during

DMA memory read cycle.

CLK

It is a clock frequency signal which is required for the internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3

These are the four least significant address lines. In the slave mode, they act as an input, which

selects one of the registers to be read or written. In the master mode, they are the four least

significant memory address output lines generated by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables the read/write operations

to/from 8257. In the master mode, it disables the read/write operations to/from 8257.

A4 - A7

These are the higher nibble of the lower byte address generated by DMA in the master mode.

READY

It is an active-high asynchronous input signal, which makes DMA ready by inserting wait

states.

HRQ

This signal is used to receive the hold request signal from the output device. In the slave mode,

it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input

of the CPU.

HLDA

It is the hold acknowledgement signal which indicates the DMA controller that the bus has

been granted to the requesting peripheral by the CPU when it is set to 1.

MEMR

It is the low memory read signal, which is used to read the data from the addressed memory

locations during DMA read cycles.

MEMW

It is the active-low three state signal which is used to write the data to the addressed memory

location during DMA write operation.

ADST

This signal is used to convert the higher byte of the memory address generated by the DMA

controller into the latches.

AEN

This signal is used to disable the address bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present

peripheral devices.

MARK

The mark will be activated after each 128 cycles or integral multiples of it from the beginning.

It indicates the current DMA cycle is the 128th cycle since the previous MARK output to the

selected peripheral device.

Vcc

It is the power signal which is required for the operation of the circuit.

Result:

Thus DMA controller 8257/8237 has been studied.

EX.NO: 20 REALTIME CLOCK

Aim:

To write an assembly language program to interface and program a traffic light controller.

Theory:

Program:

Result:

Thus the real time clock has been implemented and studied.

15EE305J - MICROCONTROLLER LAB REFERENCE MANUAL

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