1.2.1 PowerMOS Introduction - ghioni.faculty.polimi.it · Philips Semiconductors A cross-section...

Introduction Power Semiconductor ApplicationsPhilips Semiconductors

1.2.1 PowerMOS Introduction

Device structure and fabricationThe idea of a vertical channel MOSFET has been knownsince the 1930s but it was not until the mid 1970s that thetechnology of diffusion, ion implantation and materialtreatment had reached the level necessary to produceDMOS on a commercial scale. The vertical diffusiontechnique uses technology more commonly associatedwith the manufacture of large scale integrated circuits thanwith traditional power devices. Figure 1(a) shows thevertical double implanted (DIMOS) channel structure whichis the basis for all Philips power MOSFET devices.

An N-channel PowerMOS transistor is fabricated on anN+substrate with a drain metallization applied to its’underside. Above the N+substrate is an N- epi layer, thethickness and resistivity of which depends on the requireddrain-source breakdown voltage. The channel structure,formed from a double implant in to the surface epi material,is laid down in a cellular pattern such that many thousandsof cells go to make a single transistor. The N+polysilicongate which is embedded in an isolating silicon dioxide layer,is a single structure which runs between the cells acrossthe entire active region of the device. The sourcemetallization also covers the entire structure and thus

parallels all the individual transistor cells on the chip. Thelayout of a typical low voltage chip is shown in Fig.1(b). Thepolysilicon gate is contacted by bonding to the defined padarea while the source wires are bonded directly to thealuminium over the cell array. The back of the chip ismetallized with a triple layer of titanium/nickel/silver and thisenables the drain connection to be formed using a standardalloy bond process.

The active part of the device consists of many cellsconnected in parallel to give a high current handlingcapability where the current flow is vertical through the chip.Cell density is determined by photolithographic tolerancerequirements in defining windows in the polysilicon andgate-source oxide and also by the width of the polysilicontrack between adjacent cells. The optimum value forpolysilicon track width and hence cell density varies as afunction of device drain-source voltage rating, this isexplained in more detail further in the section. Typical celldensitiesare 1.6 million cells per square inch for low voltagetypes and 350,000 cells per square inch for high voltagetypes. The cell array is surrounded by an edge terminationstructure to control the surface electric field distribution inthe device off-state.

Fig.1(a) Power MOSFET cell structure.

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Fig.1(b) Plan view of a low voltage Power MOS chip

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A cross-section through a single cell of the array is shownin Fig.2. The channel length is approximately 1.5 micronsand is defined by the difference in the sideways diffusionof the N+ source and the P-body. Both these diffusions areauto-aligned to the edge of the polysilicon gate during thefabrication process. All diffusions are formed by ionimplantation followed by high temperature anneal/drive-into give good parameter reproducibility. The gate iselectrically isolated from the silicon by an 800 Angstromlayer of gate oxide (for standard types, 500 Angstrom forLogic level and from the overlying aluminium by a thick layerof phosphorus doped oxide. Windows are defined in thelatter oxide layer to enable the aluminium layer to contactthe N+ source and the P+ diffusion in the centre of each cell.The P+ diffusion provides a low resistance connectionbetween the P- body and ground potential, thus inhibitingturn-on of the inherent parasitic NPN bipolar structure.

Fig.2 Cross-section of a single cell.

Device operationCurrent flow in an enhancement mode power MOSFET iscontrolled by the voltage applied between the gate andsource terminals. The P- body isolates the source and drainregions and forms two P-N junctions connectedback-to-back. With both the gate and source at zero voltsthere is no source-drain current flow and the drain sits atthe positive supply voltage. The only current which can flowfrom source to drain is the reverse leakage current.

As the gate voltage is gradually made more positive withrespect to the source, holes are repelled and a depletedregion of silicon is formed in the P- body below thesilicon-gate oxide interface. The silicon is now in a’depleted’ state, but there is still no significant current flowbetween the source and drain.

When the gate voltage is further increased a very thin layerof electrons is formed at the interface between the P- bodyand the gate oxide. This conductive N-type channelenhanced by the positive gate-source voltage, now permitscurrent to flow from drain to source. The silicon in the P-

body is referred to as being in an ’inverted’ state. A slightincrease in gate voltage will result in a very significantincrease in drain current and a corresponding rapiddecrease in drain voltage, assuming a normal resistive loadis present.

Eventually the drain current will be limited by the combinedresistances of the load resistor and the RDS(ON) of theMOSFET. The MOSFET resistance reaches a minimumwhen VGS = +10 volts (assuming a standard type).Subsequently reducing the gate voltage to zero voltsreverses the above sequence of events. There are nostored charge effects since power MOSFETS are majoritycarrier devices.

Power MOSFET parameters

Threshold voltageThe threshold voltage is normally measured by connectingthe gate to the drain and then determining the voltage whichmust be applied across the devices to achieve a draincurrent of 1.0 mA. This method is simple to implement andprovides a ready indication of the point at which channelinversion occurs in the device.

The P- body is formed by the implantation of boron throughthe tapered edge of the polysilicon followed by an annealand drive-in. The main factors controlling threshold voltageare gate oxide thickness and peak surface concentrationin the channel, which is determined by the P-body implantdose. To allow for slight process variation a window isusually defined which is 2.1 to 4.0 volts for standard typesand 1.0 to 2.0 volts for logic level types.

Positive charges in the gate oxide, for example due tosodium, can cause the threshold voltage to drift. Tominimise this effect it is essential that the gate oxide isgrown under ultra clean conditions. In addition thepolysilicon gate and phosphorus doped oxide layer providea good barrier to mobile ions such as sodium and thus helpto ensure good threshold voltage stability.

Drain-source on-state resistanceThe overall drain-source resistance, RDS(ON), of a powerMOSFET is composed of several elements, as shown inFig.3.

The relative contribution from each of the elements varieswith the drain-source voltage rating. For low voltagedevices the channel resistance is very important while for

N- EPI Layer

N+ Substrate

DRAIN

SOURCE

P- P-P+

N+ N+

GATE

20 um

21


Fig.3 Power MOSFET components of RDS(ON).

the high voltage devices the resistivity and thickness of theepitaxial layer dominates. The properties of the variousresistive components will now be discussed:

Channel . The unit channel resistance is determined by thechannel length, gate oxide thickness, carrier mobility,threshold voltage, and the actual gate voltage applied tothe device. The channel resistance for a given gate voltagecan be significantly reduced by lowering the thickness ofthe gate oxide. This approach is used to fabricate the LogicLevel MOSFET transistors and enables a similar valueRDS(ON) to be achieved with only 5 volts applied to the gate.Of course, the gate-source voltage rating must be reducedto allow for the lower dielectric breakdown of the thinneroxide layer.

The overall channel resistance of a device is inverselyproportional to channel width, determined by the totalperiphery of the cell windows. Channel width is over200 cm for a 20 mm2 low voltage chip. The overall channelresistance can be significantly reduced by going to highercell densities, since the cell periphery per unit area isreduced.

Accumulation layer . The silicon interface under the centreof the gate track is ’accumulated’ when the gate is biasedabove the threshold voltage. Thisprovides a low resistancepath for the electrons when they leave the channel, prior toentering the bulk silicon. This effect makes a significantcontribution towards reducing the overall RDS(ON).

Parasitic JFET . After leaving the accumulation layer theelectrons flow vertically down between the cells into thebulk of the silicon. Associated with each P-N junction thereis a depletion region which, in the case of the high voltagedevices,extends severalmicrons into the N epitaxial region,even under zero bias conditions. Consequently the currentpath for the electrons is restricted by this parasitic JFETstructure. The resistance of the JFET structure can bereduced by increasing the polysilicon track width. Howeverthis reduces the cell density. The need for compromise

leads to an optimum value for the polysilicon track width fora given drain-source voltage rating. Since the zero-biasdepletion width is greater for low doped material, then awider polysilicon track width is used for high voltage chipdesigns.

Spreading resistance . As the electrons move further intothe bulk of the silicon they are able to spread sideways andflow under the cells. Eventually paths overlap under thecentre of each cell.

Epitaxial layer . The drain-source voltage ratingrequirements determine the resistivity and thickness of theepitaxial layer. For high voltage devices the resistance ofthe epitaxial layer dominates the overall value of RDS(ON).

Substrate. The resistance of the N+ substrate is onlysignificant in the case of 50 V devices.

Wires and leads . In a completed device the wire and leadresistances contribute a few milli-ohms to the overallresistance.

For all the above components the actual level of resistanceis a function of the mobility of the current carrier. Since themobility of holes is much lower than that of electrons theresistance of P-Channel MOSFETs is significantly higherthan that of N-Channel devices. For this reason P-Channeltypes tend to be unattractive for most applications.

Drain-source breakdown voltage

The voltage blocking junction in the PowerMOS transistoris formed between the P-body diffusion and the N- epi layer.For any P-N junction there exists a maximum theoreticalbreakdown voltage, which is dependent on doping profilesand material thickness. For the case of the N-channelPowerMOS transistor nearly all the blocking voltage issupported by the N- epi layer. The ability of the N- epi layertosupport voltage is a function of its resistivity and thicknesswhere both must increase to accommodate a higherbreakdown voltage. This has obvious consequences interms of drain-source resistance with RDS(ON) beingapproximately proportional to BVDSS

2.5. It is thereforeimportant to design PowerMOS devices such that thebreakdown voltage is as close as possible to the theoreticalmaximum otherwise thicker, higher resistivity material hasto be used. Computer models are used to investigate theinfluence of cell design and layout on breakdown voltage.Since these factors also influence the ’on-state’ andswitching performances a degree of compromise isnecessary.

To achieve a high percentage of the theoretical breakdownmaximum it is necessary to build edge structures aroundthe active area of the device. These are designed to reducethe electric fields which would otherwise be higher in theseregions and cause premature breakdown.

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For low voltage devices this structure consists of a fieldplate design, Fig.4. The plates reduce the electric fieldintensity at the corner of the P+ guard ring which surroundsthe active cell area, and spread the field laterally along thesurface of the device. The polysilicon gate is extended toform the first field plate, whilst the aluminium sourcemetallization forms the second plate. The polysilicontermination plate which is shorted to the drain in the cornersof the chip (not shown on the diagram) operates as achannel stopper. This prevents any accumulation ofpositive charge at the surface of the epi layer and thusimproves stability. Aluminium overlaps the terminationplate and provides a complete electrostatic screen againstany external ionic charges, hence ensuring good stabilityof blocking performance.

Fig.4 Field plate structure for low voltage devices.

For high voltage devices a set of floating P+ rings, see Fig.5,is used to control the electric field distribution around thedevice periphery. The number of rings in the structuredepends on the voltage rating of the device, eight rings areused for a 1000 volt type such as the BUK456-1000A. Athree dimensional computer model enables the optimumringspacing to be determined so that each ring experiencesa similar field intensity as the structure approachesavalanche breakdown. The rings are passivated withpolydox which acts as an electrostatic screen and preventsexternal ionic charges inverting the lightly doped N-

interface to form P- channels between the rings. Thepolydox is coated with layers of silicon nitride andphosphorus doped oxide.

All types have a final passivation layer of plasma nitride,which acts as a further barrier to mobile charge and alsogives anti-scratch protection to the top surface.

Fig.5 Ring structure for high voltage devices.

Electrical characteristics

The DC characteristicIf a dc voltage source is connected across the drain andsource terminals of an N channel enhancement modeMOSFET, with the positive terminal connected to the drain,the following characteristics can be observed. With the gateto source voltage held below the threshold level negligiblecurrent will flow when sweeping the drain source voltagepositive from zero. If the gate to source voltage is takenabove the threshold level, increasing the drain to sourcevoltage will cause current to flow in the drain. This currentwill increase as the drain-source voltage is increased up toa point known as the pinch off voltage. Increasing thedrain-source terminal voltage above this value will notproduce any significant increase in drain current.

The pinch off voltage arises from a rapid increase inresistance which for any particular MOSFET will dependon the combination of gate voltage and drain current. In itssimplest form, pinch off will occur when the ohmic dropacross the channel region directly beneath the gatebecomes comparable to the gate to source voltage. Anyfurther increase in drain current would now reduce the netvoltage across the gate oxide to a level which is no longersufficient to induce a channel. The channel is thus pinchedoff at its edge furthest from the source N+ (see Fig.6).

A typical set of output characteristics is shown in Fig.7. Thetwo regions of operation either side of the pinch off voltagecan be seen clearly. The region at voltages lower than thepinch off value is usually known as the ohmic region.Saturation region is the term used to describe that part ofthe characteristic above the pinch-off voltage. (NB Thisdefinition of saturation is different to that used for bipolardevices.)

N- EPI Layer

P+

N+

P-

LOPOX

LPCVD NITRIDE

POLYDOX

P+P+P+P+

SourceGuardRing

Floating Guard Rings

N- EPI Layer

N+ Substrate

P+

P-

N+

Guard Ring

Polysilicon

SourceMetallization

Gate RingSource RingPolysiliconTerminationPlate

(Source)

23


Fig.6 Pinch off in a Power MOSFET

Fig.7 A typical dc characteristic for an N-channelenhancement mode MOSFET.

The switching characteristics

The switching characteristics of a Power MOSFET aredetermined largely by the various capacitances inherent inits’ structure. These are shown in Fig.8.

To turn the device on and off the capacitances have to becharged and discharged, the rate at which this can beachieved is dependent on the impedance and the currentsinking/sourcing capability of the drive circuit. Since it isonly the majority carriers that are involved in the conductionprocess, MOSFETs do not suffer from the same storagetime problems which limit bipolar devices where minoritycarriers have to be removed during turn-off. For mostapplications therefore the switching times of the Power

Fig.8. The internal capacitances of a Power MOSFET.

MOSFET are limited only by the drive circuit and can bevery fast. Temperature has only a small effect on devicecapacitances therefore switching times are independent oftemperature.

In Fig.9 typical gate-source and drain-source voltages fora MOSFET switching current through a resistive load areshown. The gate source capacitance needs to be chargedup to a threshold voltage of about 3 V before the MOSFETbegins to turn on. The time constant for this is CGS(RDR+RG)and the time taken is called the turn-on delay time (tD(ON)).As VGS starts to exceed the threshold voltage the MOSFETbegins to turn on and VDS begins to fall. CGD now needs tobe discharged as well as CGS being charged so the timeconstant is increased and the gradient of VGS is reduced.As VDS becomes less than VGS the value of CGD increasessharply since it is depletion dependent. A plateau thusoccurs in the VGS characteristic as the drive current goesinto the charging of CGD.

VGS10 V

Ohmic Drop7 V

3 V Net Gate to Channel10 V Gate to Channel

Polysilicon Gate

Gate Oxide

P-Source

ChannelN-

Pinch Off

Id

+

D

S

G

Cgs

Cgd

Cds

0VDS / V

ID / A BUK4y8-800A20

15

10

5

0

4

5

6

4.5

5.5

10

10 20 30

VGS / V =

24


Fig.9. The switching waveforms for a MOSFET.

0 0.2 0.4 0.6 0.8 1 1.2

50

40

30

20

10

0

Time (Microseconds)

Vol

tage

(V

olts

)

Drain-Source Voltage

Gate-Source Voltage

Turn-on Turn-off

When VDS has collapsed VGS continues to rise as overdriveis applied. Gate overdrive is necessary to reduce theon-resistance of the MOSFET and thereby keep power lossto a minimum.

To turn the MOSFET off the overdrive has first to beremoved. The charging path for CGD and CDS now containsthe load resistor (RL) and so the turn-off time will begenerally longer than the turn-on time.

The Safe Operating AreaUnlike bipolar devices Power MOSFETs do not suffer fromsecond breakdown phenomena when operated within theirvoltage rating. Essentially therefore the safe operating areaof a Power MOSFET is determined only by the power

necessary to raise its junction temperature to the ratedmaximum of 150 ˚C or 175 ˚C (which TJMAX depends onpackage and voltage rating). Whether a MOSFET is beingoperated safely with respect to thermal stress can thus bedetermined directly from knowledge of the power functionapplied and the thermal impedance characteristics.

Asafe operating areacalculated assumingamounting basetemperature of 25 ˚C is shown in Fig.10 for a BUK438-800device. This plot shows the constant power curves for avariety of pulse durations ranging from dc to 10 µs. Thesecurves represent the power levels which will raise Tj up tothe maximum rating. Clearly for mounting basetemperatures higher than 25 ˚C the safe operating area issmaller. In addition it is not usually desirable to operate the

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device at its TJMAX rating. These factors can be taken intoaccount quite simply where maximum power capability fora particular application is calculated from:

Tj is the desired operating junction temperature (must beless than Tjmax)Tmb is the mounting base temperatureZth is the thermal impedance taken from the data curves

The safe operating area is bounded by a peak pulse currentlimit and a maximum voltage. The peak pulse current isbased on a current above which internal connections maybe damaged. The maximum voltage is an upper limit abovewhich the device may go into avalanche breakdown.

Fig.10. The Safe Operating Area of the BUK438-800.

In a real application the case temperature will be greaterthan 25 ˚C because of the finite thermal impedance ofpracticalheatsinks. Alsoa junction temperature of between80 ˚C and 125 ˚C would be preferable since this improvesreliability. If a nominal junction temperature of 80 ˚Cinstead of 150 ˚C is used then the ability of the MOSFETto withstand current spikes is improved.

Causes of Power Loss

There are four main causes of power dissipation inMOSFETs.

Conduction losses - The conduction losses (PC) are givenby equation (1).

It is important to note that the on-resistance of the MOSFETwhen it is operated in the Ohmic region is dependent onthe junction temperature. On-resistance roughly doublesbetween 25 ˚C and 150 ˚C, the exact characteristics areshown in the data sheets for each device.

Switching losses - When a MOSFET is turned on or off itcarries a large current and sustains a large voltage at thesame time. There is therefore a large power dissipationduring the switching interval. Switching losses arenegligible at low frequencies but are dominant at highfrequencies. The cross-over frequency depends on thecircuit configuration. For reasons explained in the sectionon switching characteristics, a MOSFET usually turns offmore slowly than it turns on so the losses at turn-off will belarger than at turn-on. Switching losses are very dependenton circuit configuration since the turn-off time is affected bythe load impedance.

Turn-off losses may be reduced by the use of snubbercomponents connected across the MOSFET which limit therate of rise of voltage. Inductors can be connected in serieswith the MOSFET to limit the rate of rise of current at turn-onand reduce turn-on losses. With resonant loads switchingcan take place at zero crossing of voltage or current soswitching losses are very much reduced.

Diode losses - These losses only occur in circuits whichmake use of the antiparallel diode inherent in the MOSFETstructure. A good approximation to the dissipation in thediode is the product of the diode voltage drop which istypically less than 1.5 V and the average current carried bythe diode. Diode conduction can be useful in such circuitsas pulse width modulated circuits used for motor control, insome stepper motor drive circuits and in voltage fed circuitsfeeding a series resonant load.

Gate losses - The losses in the gate are given in equation2whereRG is the internal gate resistance, RDR is the externaldrive resistance, VGSD is the gate drive voltage and CIP isthe capacitance seen at the input to the gate of theMOSFET.

The input capacitance varies greatly with the gate drainvoltage so the expression in equation 3 is more useful.

(3)

Where QG is the peak gate charge.

Parallel OperationIf power requirements exceed those of available devicesthen increased power levels can be achieved by parallellingdevices. Parallelling of devices is made easier using

Pmax =(Tj − Tmb)

Zth

10 1000VDS / V

ID / A100

10

1

0.1

100 us

1 ms

10 ms

RDS(ON) =

VDS/ID

100 ms DC

10 us

tp =

BUK438-800

100

A

B

PG =CIP.VGSD

2 .f .RG

(RG + RDR)(2)

PG =QG.VGSD.f .RG

(RG + RDR)(3)

PC = ID2.RDS(ON) (1)

26


MOSFETs because they have a positive temperaturecoefficient of resistance. If one parallelled MOSFET carriesmore current than the others it becomes hotter. Thiscauses the on-resistance of that particular device tobecome greater than that of the others and so the currentin it reduces. This mechanism opposes thermal runawayin one of the devices. The positive temperature coefficientalso helps to prevent hot spots within the MOSFET itself.

Applications of Power MOSFETsPower MOSFETs are ideally suited for use in manyapplications, some of which are listed below. Furtherinformation on the major applications is presented in

subsequent chapters.

Chapter 2: Switched mode power supplies (SMPS)

Chapter 3: Variable speed motor control.

Chapter 5: Automotive switching applications.

ConclusionsIt can be seen that the operation of the Power MOSFET isrelatively easy to understand. The advantages of fastswitching times, ease of parallelling and low drive powerrequirements make the device attractive for use in manyapplications.

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1.2.2 Understanding Power MOSFET Switching Behaviour

Power MOSFETs are well known for their ease of drive andfast switching behaviour. Being majority carrier devicesmeans they are free of the charge storage effects whichinhibit the switching performance of bipolar products. Howfast a Power MOSFET will switch is determined by thespeed at which its internal capacitances can be chargedand discharged by the drive circuit. MOSFET switchingtimes are often quoted as part of the device data howeveras an indication as to the true switching capability of thedevice, these figures are largely irrelevant. The quotedvalues are only a snapshot showing what will be achievedunder the stated conditions.

This report sets out to explain the switching characteristicsof Power MOSFETs. It will consider the main features ofthe switching cycle distinguishing between what is devicedeterminant and what can be controlled by the drive circuit.The requirements for the drive circuit are discussed in termsof the energy that it must supply as well as the currents itis required to deliver. Finally, how the drive circuitinfluences switching performance, in terms of switchingtimes, dV/dt and dI/dt will be reviewed.

Voltage dependent capacitanceThe switching characteristics of the Power MOSFET aredetermined by its capacitances. These capacitances arenot fixed but are a function of the relative voltages betweeneach of the terminals. To fully appreciate Power MOSFETswitching, it is necessary to understand what gives rise tothis voltage dependency.

Parallel plate capacitance is expressed by the well knownequation

where ’a’ is the area of the plates, d is the separatingdistance and Ε is the permittivity of the insulating materialbetween them. For a parallel plate capacitor, the plates aresurfaces on which charge accumulation / depletion occursin response to a change in the voltage applied across them.In a semiconductor, static charge accumulation / depletioncan occur either across a PN junction or at semiconductorinterfaces either side of a separating oxide layer.

i) P-N junction capacitanceThe voltage supporting capability of most powersemiconductors is provided by a reverse biased P-Njunction. The voltage is supported either side of the junctionby a region of charge which is exposed by the appliedvoltage. (Usually referred to as the depletion regionbecause it is depleted of majority carriers.) Fig.1 showshow the electric field varies across a typical P-N- junction

for a fixed dc voltage. The shaded area beneath the curvemust be equal to the applied voltage. The electric fieldgradient is fixed, independent of the applied voltage,according to the concentration of exposed charge. (This isequal to the background doping concentration used duringdevice manufacture.) A slight increase in voltage abovethis dc level will require an extensionof the depletion region,and hence more charge to be exposed at its edges, this isillustrated in Fig.1. Conversely a slight reduction in voltagewill cause the depletion region to contract with a removalof exposed charge at its edge. Superimposing a small acsignal on the dc voltage thus causes charge to be addedand subtracted at either side of the depletion region of widthd1. The effective capacitance per unit area is

Since the depletion region width is voltage dependent it canbe seen from Fig.1 that if the dc bias is raised to say V2,the junction capacitance becomes

Junction capacitance is thus dependent on applied voltagewith an inverse relationship.

Fig.1 Voltage dependence of a PN junctioncapacitance

ii) Oxide capacitanceFig.2 shows two semiconductor layers separated by aninsulating oxide. In this case the surface layer is polysilicon(representative of the PowerMOS gate structure) and thelower layer is a P-type substrate. Applying a negativevoltage to the upper layer with respect to the lower will causepositive charge accumulation at the surface of the P-doped

C1 =Εd1

2

C2 =Εd2

3

E

xd1d2

V1

V2

N type siliconP type silicon

C = Εad

1

29


material (positively charged holes of the P material areattracted by the negative voltage). Any changes in thisapplied voltage will cause a corresponding change in theaccumulation layer charge. The capacitance per unit areais thus

where t = oxide thickness

Applying a positive voltage to the gate will cause a depletionlayer to form beneath the oxide, (ie the positively chargedholes of the P-material are repelled by the positive voltage).The capacitance will now decrease with increasing positivegate voltage as a result of widening of the depletion layer.Increasing the voltage beyond a certain point results in aprocess known as inversion; electrons pulled into theconduction band by the electric field accumulate at thesurface of the P-type semiconductor. (The voltage at whichthis occurs is the threshold voltage of the power MOSFET.)Once the inversion layer forms, the depletion layer widthwill not increase with additional dc bias and the capacitanceis thus at its minimum value. (NB the electron chargeaccumulation at the inversion layer cannot follow a highfrequency ac signal in the structure of Fig.2, so highfrequency capacitance is still determined by the depletionlayer width.) The solid line of Fig.3 represents thecapacitance-voltage characteristic of an MOS capacitor.

Fig.2 Oxide capacitance

In a power MOSFET the solid line is not actually observed;the formation of the inversion layer in the P-type materialallows electrons to move from the neighbouring N+-source,the inversion layer can therefore respond to a highfrequency gate signal and the capacitance returns to itsmaximum value, dashed line of Fig.3.

Fig.3 C-V plot for MOS capacitance

Power MOSFET capacitances

Fig.4 Parasitic capacitance model

The circuit model of Fig.4 illustrates the parasiticcapacitances of the Power MOSFET. Most PowerMOSdata sheets do not refer to these components but to inputcapacitance Ciss, output capacitance Coss and feedbackcapacitance Crss. The data sheet capacitances relate tothe primary parasitic capacitances of Fig.4 as follows:

Ciss: Parallel combination of Cgs and CgdCoss: Parallel combination of Cds and CgdCrss: Equivalent to Cgd

Fig.5 shows the cross section of a power MOSFET cellindicatingwhere the parasiticcapacitances occur internally.

Cox

C

Bias Voltage

(Polysilicon to P-type silicon)

Cox =Εt

4

Cgd

Cds

Cgs

G

S

D

toxide

P type silicon

Polysilicon

30


Fig.5 Cross section of a single PowerMOS cell showinginternal capacitance

Thecapacitancebetween drain andsource is aP-N junctioncapacitance, varying in accordance with the width of thedepletion layer, which in turn depends on the voltage beingsupported by the device. The gate source capacitanceconsists of the three components, CgsN+, CgsP and CgsM.Of these CgsP is across the oxide which will vary accordingto the applied gate source voltage as described above.

Of particular interest is the feedback capacitance Cgd. Itis this capacitance which plays a dominant role duringswitching and which is also the most voltage dependent.Cgd is essentially two capacitors in series such that

CgsN+

CgsM OxidePolysilicon

N+P-

P

N-

N+

MetalizationSource

Drain

Gate

Cgdbulk

CgdoxCgsP

Cds Depletion Layer

1Cgd

=1

Cgdox+

1Cgdbulk

5

Fig.6 How Cgd is affected by voltage

OxidePolysilicon

N+P-

P

N-

N+

Metalization

Source

Drain

Gate

Depletion Layer Widths

Area of Oxide Capacitance Exposedfor Voltages V1 & V2

For Three Applied Voltages

Width for Cgdbulk

at Voltage V3

V3

V2V1

31


Fig.6 illustrateshow this capacitance is affected by the drainto gate voltage. With a large voltage drain to gate, Cgdbulkis very small due to the wide depletion region and thusmaintains Cgd at a low value. As the voltage is reducedthe depletion region shrinks until eventually the oxidesemiconductor interface is exposed. This occurs as Vdgapproaches 0 V. Cgdox now dominates Cgd. As Vdg isfurther reduced the drain will become negative with respectto the gate (normal on-state condition) an increasing areaof the oxide-semiconductor interface is exposed and anaccumulation layer forms at the semiconductor surface.Thenow large area of exposed oxide results in a large valuefor Cgdox and hence Cgd. Fig.7 shows Cgd plotted as afunction of drain to gate voltage. This illustrates the almoststep increase in capacitance at the point where Vgs = Vgd.

Fig.7 How Cgd varies with drain to gate voltage

Charging cycle - The Gate ChargeOscillogramThe switching cycle of a power MOSFET can be clearlyobserved by applying a constant current to the gate andusing a constant current source as the load, Fig.8. In thiscircuit the MOSFET is turned on by feeding a constantcurrent of 1 mA on to the gate, conversely the device isturned off by extracting a constant current of 1 mA from thegate. The gate and drain voltages with respect to sourcecan be monitored on an oscilloscope as a function of time.Since Q = it, a 1 µsec period equates to 1 nc of chargeapplied to the gate. The gate source voltage can thus beplotted as a function of charge on the gate. Fig.9 showssuch a plot for the turn-on of a BUK555-100A, also shownis the drain to source voltage. This gate voltage plot showsthe characteristic shape which results from charging of thepower MOSFETs input capacitance. This shape arises asfollows: (NB the following analysis uses the two circuitmodels of Fig.10 to represent a MOSFET operating in theactive region (a) and the ohmic region (b). In the active

region the MOSFET is a constant current source where thecurrent is a function of the gate-source voltage. In the ohmicregion the MOSFET is in effect just a resistance.)

Fig.8 Gate charge circuit

At time, t0 (Fig.9), the gate drive is activated. Current flowsinto the gate as indicated in Fig.11(a), charging both Cgsand Cgd. After a short period the threshold voltage isreached and current begins to rise in the MOSFET. Theequivalent circuit is now as shown in Fig.11(b). The drainsource voltage remains at the supply level as long as id < I0and the free wheeling diode D is conducting.

Fig.9 Gate charge plot for a BUK555-100A (Logic LevelFET)

Vdd

Vdg0

Cdg

0 10 20 30 40

26

24

22

20

18

16

14

12

10

8

6

4

2

0

(V)

(us)(1us = 1 nc for Vgs plot)

Vds

Vgs

BUK555-100A(@ Id = 25 A)

t0 t1 t2

32


The current in the MOSFET continues to rise until id = I0,since the device is still in its active region, the gate voltagebecomes clamped at this point, (t1). The entire gate currentnow flows through Cgd causing the drain-source voltage todrop as Cgd is discharged, Fig.11(c). The rate at whichVds falls is given by:

As Vdg approaches zero, Cgd starts to increasedramatically, reaching its maximum as Vdg becomesnegative. dVds/dt is now greatly reduced giving rise to thevoltage tail.

Once the drain-source voltage has completed its drop tothe on-state value of I0.RDS(ON), (point t2), the gate sourcevoltage becomes unclamped and continues to rise,Fig.11(d). (NB dVgs/dQ in regions 1 and 3 indicates the

input capacitance values.)

Fig.10 Equivalent circuits for a Power MOSFET duringswitching

G

D

S

Cgd

Cgs

id = f(Vgs)

G

D

S

Cgd

Cgs

Rds(on)

(a) (b)

dVdsdt

=dVdg

dt=

igCgd

6

Fig.11 Charging the parasitic capacitance during turn-on

Vdd

Cgd

Cgs

Io

(a) Vdd

Cgd

Cgs

id = f(Vgs)

Io

(b)

Vdd

Cgd

Cgs

id = f(Vgs)

Io

(c) Vdd

Cgd

Cgs

Rds(on)

Io

(d)

33


The gate charge oscillogram can be found in the data forall Philips PowerMOS devices. This plot can be used todetermine the required average gate drive current for aparticular switching speed. The speed is set by how fastthe charge is supplied to the MOSFET.

Energy consumed by the switching eventIn the majority of applications the power MOSFET will bedriven not from a constant current source but via a fixed

gate drive impedance from a voltage source. Fig.13 showsthe voltageon avoltage independentcapacitor as a functionof charge. The area beneath the charge vs voltage curveequals the stored energy (E = Q.V/2). The area above thecharge vs voltage curve (bounded by the supply voltage)is the amount of energy dissipated during the charging cyclefrom a fixed voltage source. The total energy delivered bythe supply is therefore Q.V, where 1/2 Q.V is stored on thecapacitor to be dissipated during the discharge phase.

Fig.12 Gate charging cycle

t0 t1 t2 t3 t4 t5 t6

1a 2a 3a

1b 2b3b

4a

4b

Vgg

Vdd

Out

put C

apac

itanc

e

34


Although the voltage vs charge relationship for theMOSFETs gate is not linear, energy loss is easily identified.The following discussion assumes a simple drive circuitconsisting of a voltage source and drive resistance.

From t0 to t1 energy is stored in the gate capacitance whichis equal to the area of region 1a. Since this charge hasfallen through a voltage Vgg - Vgs(t), the area of region 1brepresents the energy dissipated in the drive resistanceduring its delivery. Between t1 and t2 all charge entersCgd, the area of region 2a represents the energy stored inCgd while 2b again corresponds with the energy dissipationin the drive resistor. Finally, between t2 and t3 additionalenergy is stored by the input capacitance equal to the areaof region 3a.

Fig.13 Energy stored on a capacitor

The total energy dissipated in the drive resistance at turn-onis therefore equal to the area 1b + 2b + 3b. Thecorresponding energy stored on the input capacitance is1a + 2a + 3a, this energy will be dissipated in the driveresistance at turn-off. The total energy expended by thegate drive for the switching cycle is Q.Vgg.

As well as energy expended by the drive circuit, a switchingcycle will also require energy to be expended by the draincircuit due to the charging and discharging of Cgd and Cdsbetween the supply rail and VDS(ON). Moving from t5 to t6the drain side of Cgd is charged from Io.RDS(ON) to Vdd. Thedrain circuit must therefore supply sufficient current for thischarging event. The total charge requirement is given bythe plateau region, Q6 - Q5. The area 4a (Fig.12) underthe drain-source voltage curve represents the energystored by the drain circuit on Cgd during turn-on. Region4b represents the corresponding energy delivered to theload during this period. The energy consumed from thedrain supply to charge and discharge Cgd over oneswitching cycle is thus given by:

(The energy stored on Cgd during turn-off is dissipatedinternally in the MOSFET during turn-on.) Additional energyis also stored on Cds during turn-off which again isdissipated in the MOSFET at turn-on.

The energy lost by both the gate and drain supplies in thecharging and discharging of the capacitances is very smallover 1 cycle; Fig.9 indicates 40 nc is required to raise thegate voltage to 10 V, delivered from a 10 V supply thisequates to 400 nJ; to charge Cgd to 80 V from an 80 Vsupply will consume 12 nc x 80 V = 1.4 µJ. Only asswitching frequencies approach 1 MHz will this energy lossstart to become significant. (NB these losses only apply tosquare wave switching, the case for resonant switching issome-what different.)

Switching performance

1) Turn-on

The parameters likely to be of most importance during theturn-on phase are,

turn-on timeturn-on losspeak dV/dtpeak dI/dt.

Turn-on time is simply a matter of how quickly the specifiedcharge can be applied to the gate. The average currentthat must be supplied over the turn-on period is

For repetitive switching the average current requirement ofthe drive is

where f = frequency of the input signal

Turn-on loss occurs during the initial phase when currentflows in the MOSFET while the drain source voltage is stillhigh. To minimise this loss, a necessary requirement ofhigh frequency circuits, requires the turn-on time to be assmall as possible. To achieve fast switching the drive circuitmust be able to supply the initial peak current, given byequation 10.

Voltage

Charge

Stored Energy

Supply Voltage

Ion =Qton

8

I = Q.f 9

WDD = (Q6 − Q5).(VDD − VDS(ON)) 7

35


Fig.14 Bridge Circuit

One of the main problems associated with very fastswitching MOSFETs is the high rates of change in voltageand current. High values of dV/dt can couple throughparasitic capacitances to give unwanted noise on signallines. Similarly a high dI/dt may react with circuit inductanceto give problematic transients and overshoot voltages in thepower circuit. dI/dt is controlled by the time taken to chargethe input capacitance up to the plateau voltage, while dV/dtis governed by the rate at which the plateau region is movedthrough.

Particular care is required regarding dV/dt when switchingin bridge circuits, (Fig.14). The free wheeling diode willhave associated with it a reverse recovery current. Whenthe opposing MOSFET switches on, the drain current risesbeyond the load current value Io to a value Io + Irr.Consequently Vgs increases beyond Vgt(Io) to Vgt(Io + Irr)as shown in Fig.15. Once the diode has recovered thereis a rapid decrease in Vgs to Vgt(Io) and this rapid decreaseprovides additional current to Cgd on top of that beingsupplied by the gate drive. This in turn causes Vdg andVds to decrease very rapidly during this recovery period.

The dV/dt in this period is determined by the recoveryproperties of the diode in relation to the dI/dt imposed uponit by the turn-on of the MOSFET, (reducing dI/dt will reducethis dV/dt, however it is best to use soft recovery diodes).

Fig.15 Gate charging cycle for a bridge circuit

ii) Turn-off

The parameters of most importance during the turn-offphase are,

turn-off timeturn-off losspeak dVds/dtpeak dId/dt.

Turn-off of a power MOSFET is more or less the inverse ofthe turn-on process. The main difference is that thecharging current for Cgd during turn-off must flow throughboth the gate circuit impedance and the load impedance.A high load impedance will thus slow down the turn-offspeed.

The speed at which the plateau region is moved throughdetermines the voltage rise time. In most applications thecharging current for Cgd will be limited by the gate drivecircuitry. The charging current,assuming no negative drive,is simply

and the length of the plateau region will be

T1

T2

D1

D2

Load

Vdd

0

Vdd

0

0

Vgt(Io)Vgt(Io + Irr)Gate Source Voltage

Drain Source Voltage

MOSFET Current

0

IoIo + Irr

Diode Current0

Io

Irr

t

Ipk =VGG

Rg

10

dVdsdt

=ig

Cgd=

VGG − VGT

RG.Cgd11

i =VgtRG

12

tp =Q.RG

Vgt13

36


The implications for low threshold (Logic Level) MOSFETsare clear from the above equations. The lower value of Vgtwill mean a slower turn-off for a given gate impedance whencompared to an equivalent standard threshold device.Equivalent switching therefore requires a lower driveimpedance to be used.

ConclusionsIn theory the speed of a power MOSFET is limited only bythe parasitic inductances of its internal bond wires. The

speed is essentially determined by how fast the internalcapacitances can be charged and discharged by the drivecircuit. Switching speeds quoted in data should be treatedwith caution since they only reflect performance for oneparticular drive condition. The gate charge plot is a moreuseful way of looking at switching capability since itindicates how much charge needs to be supplied by thedrive to turn the device on. How fast that charge should beapplied depends on the application and circuit performancerequirements.

37


1.2.6 Logic Level FETS

Standard Power MOSFETs require a gate-source voltageof 10 V to be fully ON. With Logic Level FETs (L2FETs)however, the same level of conduction is possible with agate-source voltage of only 5 V. They can, therefore, bedriven directly from 5 V TTL/CMOS ICs without the needfor the level shifting stages required for standardMOSFETs, see Fig.1. This makes them ideal for today’ssophisticated electrical systems, where microprocessorsare used to drive switching circuits.

Fig.1 Drive circuit for a standard MOSFET and anL2FET

This characteristic of L2FETs is achieved by reducing thegate oxide thickness from - 800 Angstroms to - 500Angstroms, which reduces the threshold voltage of thedevice from the standard 2.1-4.0 V to 1.0-2.0 V. Howeverthe result is a reduction in gate-source voltage ratings,from ±30 V for a standard MOSFET to ±15 V for the L2FET.The ±15 V rating is an improvement over the ’industrystandard’ of ±10 V, and permits Philips L2FETs to be usedin demanding applications such as automotive.

Although a 5 V gate-drive is ideal for L2FETs, they can beused in circuits with gate-drive voltages of up to 10 V. Using

a 10 V gate-drive results in a reduced RDS(ON) (see Fig.2)but the turn-off delay time is increased. This is due toexcessive charging of the L2FET’s input capacitance.

Fig.2 RDS(ON) as a function of VGS for a standardBUK453-100B MOSFET and a BUK553-100B L2FET. Tj

= 25 ˚C; VGS = 10 V

Capacitances, Transconductance andGate Charge

Figure3 shows the parasitic capacitances areas of a typicalPower MOSFET cell. Both the gate-source capacitanceCgs and the gate-drain capacitance Cgd increase due to thereduction in gate oxide thickness, although the increasein Cgd is only significant at low values of VDS, when thedepletion layer is narrow. Increases of the order of 25% ininput capacitance Ciss, output capacitance Coss and reversetransfer capacitance Crss result for the L2FET, comparedwith a similar standard type, at VDS = 0 V. However at thestandard measurement condition of VDS = 25 V thedifferences are virtually negligible.

Forward transconductance gfs is a function of the oxidethickness so the gfs of an L2FET is typically 40% - 50%higher than a standard MOSFET. This increase in gfs morethan offsets the increase in capacitance of an L2FET, sothe turn on charge requirement of the L2FET is lower thanthe standard type see Fig.4. For example, the standardBUK453-100B MOSFET requires about 17 nC to be fullyswitched on (at a gate voltage of 10 V) while theBUK553-100B L2FET only needs about 12 nC (at a gatesource voltage of 5 V).

input

TTL / CMOS

+10 V

VDD

StandardMOSFET

Standard MOSFET drive

input

TTL / CMOS

VDD

L FET drive2

L FET2

+5 V

57


Fig.3 Parasitic capacitances of a typical PowerMOSFET cell

Fig.4 Turn-on gate charge curves of a standardBUK453-100B and a BUK553-100B L2FET. VDD = 20 V;

ID = 12 A

Switching speed.

Figure5 compares the turn-on performance of the standardBUK453-100B MOSFET and the BUK553-100B L2FET,under identical drive conditions of 5 V from a 50 Ωgenerator using identical loads. Thanks to its lower gatethreshold voltage VGST, the L2FET can be seen to turn onin a much shorter time from the low level drive.

Figure 6 shows the turn-off performance of the standardBUK453-100B MOSFET and the BUK553-100B L2FET,again with the same drive. This time the L2FET is slowerto switch. The turn-off times are determined mainly by thetime required for Cgd to discharge. The Cgd is higher for theL2FET at low VDS, and the lower value of VGST leads to alower discharging current. The net result is an increasein turn off time.

Fig.5 Comparison of (a) gate-source voltage and (b)drain-source voltage waveforms during turn-on of a

standard BUK453-100B MOSFET and a BUK553-100BL2FET. VGS is 5 V, ID is 3 A and VDD is 30 V.

Fast switching in many applications, for exampleautomotive circuits, is not important. In areas where it isimportant however the drive conditions should beexamined. For example, for a given drive power, a 10 Vdrive with a 50 Ω source impedance is equivalent to a 5 Vdrive with a source impedance of only 12 Ω. This results infaster switching for the L2FET compared with standardMOSFETs.

Ruggedness and reliabilityMOSFETs are frequently required to be able to withstandthe energy of an unclamped inductive load turn-off. Sincethis energy is dissipated in the bulk of the silicon, stressis avoided in the gate oxide. This means that theruggedness performance of L2FETs is comparable withthat of standard MOSFETs. The use of thinner gate oxidein no way compromises reliability. Good control of keyprocess parameters such as pinhole density, mobile ioncontent, interface state density ensures good oxide quality.The projected MTBF is 2070 years at 90˚C, at a 60%confidence level.

58


Fig.6 Comparison of (a) gate-source voltage and (b)drain-source voltage waveforms during turn-off of a

standard BUK453-100B MOSFET and a BUK553-100BL2FET. VGS is 5 V, ID is 3 A and VDD is 30 V.

The VGS rating of an L2FET is about half that of a standardMOSFET,but thisdoes not affect the VDS rating. In principle,an L2FET version of any standard MOSFET is feasible.

Temperature stabilityIn general threshold voltage decreases with increasingtemperature. Although the threshold voltage of L2FETs islower than that of standard MOSFETs, so is theirtemperature coefficient of threshold voltage (about half infact), so their temperature stability compares favourablywith standard MOSFETs. Philips low voltage L2FETs(≤200v) in TO220 all feature Tjmax of 175˚C, rather thanthe industry standard of 150˚C.

ApplicationsThe Philips Components range of rugged Logic LevelMOSFETs enable cost effective drive circuit designwithout compromising ruggedness or reliability. Since theyenable power loads to be driven directly from ICs they maybe considered to be the first step towards intelligent powerswitching. Thanks to their good reliability and 175˚C Tjmax

temperature rating, they are displacing mechanical relaysin automotive body electrical functions and are beingdesigned in to such safety critical areas as ABS.

59


1.2.7 Avalanche Ruggedness

Recent advances in power MOS processing technologynow enables power MOS transistors to dissipate energywhile operating in the avalanche mode. This feature resultsin transistors able to survive in-circuit momentaryovervoltage conditions, presenting circuit designers withincreased flexibility when choosing device voltage gradeagainst required safety margins.

This paper considers the avalanche characteristics of’rugged’ power MOSFETs and presents results frominvestigations into the physical constraints which ultimatelylimit avalanche energy dissipation in the VDMOS structure.Results suggest that the maximum sustainable energy is afunction of the applied power density waveform,independent of device voltage grade and chip size.

The ability of a rugged device to operate reliably in a circuitsubject to extreme interference is also demonstrated.

Introduction.Susceptibility to secondary breakdown is a phenomenonwhich limits the power handling capability of a bipolartransistor to below its full potential. For a power MOSFET,power handling capability is a simple function of thermalresistance and operating temperature since the device isnot vulnerable to a second breakdown mechanism. Theprevious statement holds true provided the device isoperated at or below its breakdown voltage rating (BVDSS)and not subject to overvoltage. Should the transistor beforced into avalanche by a voltage surge the structure ofthe device permits possible activation of a parasitic bipolartransistor which may then suffer the consequences ofsecond breakdown. In the past this mechanism was typicalof failure in circuits where the device became exposed toovervoltage. To reduce the risk of device failure duringmomentaryoverloads improvements have been introducedto the Power MOS design which enable it to dissipateenergy while operating in the avalanche condition. The termcommonly used to describe this ability is ’Ruggedness’,however before discussing in further detail the merits of arugged Power MOSFET it is worth considering the failuremechanism of non-rugged devices.

Failure mechanism of a non-rugged PowerMOS.A power MOS transistor is made up of many thousands ofcells, identical in structure. The cross section of a typicalcell is shown in Fig. 1. When in the off-state or operating insaturation, voltage is supported across the p-n junction asshown by the shaded region. If the device is subjected toover-voltage (greater than the avalanche value of the

device), the peak electric field, located at the p-n junction,rises to the critical value (approx. 200 kV / cm ) at whichavalanche multiplication commences.

Computer modelling has shown that the maximum electricfield occurs at the corners of the P diffusions. Theelectron-hole plasma generated by the avalanche processin these regions gives rise to a source of electrons, whichare swept across the drain, and a source of holes, whichflow through the P- and P regions towards the source metalcontact.

Fig. 1 Cross section of a typical Power MOS cell.

Clearly the P- region constitutes a resistance which will giverise to a potential drop beneath the n+. If this resistance istoo large the p-n junction may become forward biased forrelatively low avalanche currents.

Also if the manufacturing process does not yield a uniformcell structure across the device or if defects are present inthe silicon then multiplication may be a local event withinthe crystal. This would give rise to a high avalanche currentdensity flowing beneath the source n+ and cause arelatively large potential drop sufficient to forward bias thep-n junction and hence activate the parasitic npn bipolartransistor inherent in the MOSFET structure. Due to thepositive temperature coefficient associated with a forwardbiased p-n junction, current crowding will rapidly ensue withthe likely result of second breakdown and eventual devicedestruction.

N+ Substrate

N- Layer

P

P-P-

N+ N+

Source Contact Metal

Polysilicon Gate

Drain

SourceParasitic

Bipolar

Transistor

61


In order that a power MOS transistor may survive transitoryexcursions into avalanche it is necessary to manufacture adevice with uniform cell structure, free from defectsthroughout the crystal and that within the cell the resistancebeneath the n+ should be kept to a minimum. In this way aforward biasing potential across the p-n junction is avoided.

Definition of ruggedness.The term ’Ruggedness’ when applied to a power MOStransistor, describes the ability of that device to dissipateenergy while operating in the avalanche condition. To testruggedness of a device it is usual to use the method ofunclamped inductive load turn-off using the circuit drawn inFig. 2.

Fig. 2 Unclamped inductive load test circuit forruggedness evaluation.

Fig. 3 Typical waveforms taken from the unclampedinductive load test circuit.

Circuit operation:-

A pulse is applied to the gate such that the transistor turnson and load current ramps up according to the inductorvalue, L and drain supply voltage, VDD. At the end of thegate pulse, channel current in the power MOS begins to fallwhile voltage on the drain terminal rises rapidly inaccordance with equation 1.

The voltage on the drain terminal is clamped by theavalanche voltage of the Power MOS for a duration equalto that necessary for dissipation of all energy stored in theinductor. Typical waveforms showing drain voltage andsource current for a device undergoing successful test areshown in Fig. 3.

The energy stored in the inductor is given by equation 2where ID is the peak load current at the point of turn-off ofthe transistor.

All this energy is dissipated by the Power MOS while thedevice is in avalanche.

Provided the supply rail is kept below 50 % of the avalanchevoltage, equation 2 approximates closely to the total energydissipation by the device during turn-off. However a moreexact expression which takes account of additional energydelivered from the power supply is given by equation 3.

Clearly the energy dissipated is a function of both theinductor value and the load current ID, the latter being setby the duration of the gate pulse. The 50 Ohm resistorbetween gate and source is necessary to ensure a fastturn-off such that the device is forced into avalanche.

The performance of a non-rugged device in response to theavalanche test is shown in Fig. 4. The drain voltage risesto the avalanche value followed by an immediate collapseto approximately 30 V. This voltage is typical of thesustaining voltage during Second Breakdown of a bipolartransistor, [1]. The subsequent collapse to zero volts after12 µS signifies failure of the device. The transistor shownhere was only able to dissipate a few micro joules at a verylow current if a failure of this type was to be avoided.

dvdt

= Ld2I

dt2(1)

L

T.U.T.

VDD

RGSR 01

VDS

-ID/100

+

-

shunt

VGS

0 WDSS= 0.5LID2 (2)

WDSS=BVDSS

BVDSS− VDD

0.5LID2 (3)

62


Fig. 4 Failure waveforms of a non rugged Power MOStransistor.

Fig. 5 Power and energy waveforms prior to failure for atypical BUK627-500B

Characteristics of a rugged Power MOS.

i) The energy limitation of a rugged deviceThe power waveform for a BUK627-500B (500 V, 0.8 Ohm)tested at a peak current of 15 A is presented in Fig. 5.

The area within the triangle represents the maximumenergy that this particular device type may sustain withoutfailure at the above current. Figure 6 shows the junctiontemperature variation in response to the power pulse,calculated from the convolution integral as shown inequation 4.

where transient thermal impedance.

Fig. 6 Junction temperature during the power pulse forthe avalanche ruggedness test on a Philips

BUK627-500B.

Equation 4 predicts that the junction temperature will passthrough a maximum of 325 ˚C during the test. Thecalculation of Zth(t) assumes that the power dissipation isuniform across the active area of the device. When thedevice operates in the avalanche mode the power will bedissipated more locally in the region of the p-n junctionwhere the multiplication takes place. Consequently a localtemperature above that predicted by equation 4 is likely tobe present within the device.

Work on bipolar transistors [2] has shown that at atemperature of the order of 400 ˚C, the voltage supportingp-n region becomes effectively intrinsic as a result ofthermal multiplication, resulting in a rapid collapse in theterminal voltage. It is probable that a similar mechanism isresponsible for failure of the Power MOS with a localtemperature approaching 400 ˚C resulting in a device shortcircuit. A subsequent rapid rise in internal temperature willresult in eventual device destruction.

Clearly the rise in Tj is a function of the applied powerwaveform which is in turn related to circuit current,avalanche voltage of the device and duration of the energypulse.Thus the energy required to bringabout device failurewill vary as a function of each of these parameters. Theruggedness of Power MOSFETS of varying crystal size andvoltage specification together with dependence on circuitcurrent is considered below.

ii) Sustainable avalanche energy as afunction of current.The typical avalanche energy required to cause devicefailure is plotted as a function of peak current in Fig. 7 fora BUK553-60A (60 V, 0.085 Ohm Logic Level device). Thisresult was obtained through destructive device testingusing the circuit of Fig. 2 and a variety of inductor values.

Tj(t) = ⌠⌡τ = 0

τ = t

P(t − τ)Zth(τ)dτ (4)

Zth(τ) =

63


Fig. 7 Avalanche energy against current for a typicalPhilips BUK553-60A

Fig. 8(a) Temperature during avalanche test for aBUK553-60A; ID = 10 A

Fig. 8(b) Temperature during avalanche test for aBUK553-60A; ID = 22 A

Theplot shows that the effectof reducing current is to permitgreater energy dissipation during avalanche prior to failure.This is an expected result since lower currents result inreduced power dissipation enabling avalanche to besustained over a longer period. Temperature plots (Fig. 8)calculated for the 10 A and 22 A failure points confirm thatthe maximum junction temperature reached in each caseis the same despite the different energy values. (N.B. Thecritical temperature is again underestimated as previouslystated.)

iii) Effect of crystal size.To enable a fair comparison of ruggedness betweendevices of various chip size it is necessary to normalise theresults. Therefore instead of plotting avalanche energyagainst current, avalanche energy density and currentdensitybecome more appropriate axes. Figure 9 shows theavalanche energy density against current density failurelocus for two 100 V Philips Power MOS types which aredifferent only in silicon area. Also shown on this plot aretwo competitor devices of different chip areas (BVDSS = 100V). This result demonstrates two points:a) the rise in Tj to the critical value for failure is dependenton the power density dissipated within the device as afunction of time,b) the sustainable avalanche energy scales proportional tochip size.

KEY: x Philips BUK553-100A (6.25 mm2 chip)+ Philips BUK555-100A (13 mm2 chip)

Competitor Devices (100 V)Fig. 9 Avalanche energy density against current density

iv) Dependence on the drain sourcebreakdown voltage rating.Energy density against current density failure loci areshown for devices of several different breakdown voltagesin Fig. 10.

64


KEY: x Philips BUK553-60A+ Philips BUK555-100A

Philips BUK627-500BFig. 10 Avalanche energy density against current

density

Presented in this form it is difficult to assess the relativeruggedness of each device since the current density isreduced for increasing voltage. If instead of peak currentdensity, peak power density is used for the x-axis thencomparison is made very simple. The data of Fig. 10 hasbeen replotted in Fig. 11 in the above manner. Representedin this fashion the ruggedness of each chip appears verysimilar highlighting that the maximum energy dissipation ofa device while in avalanche is dependent only on the powerdensity function.

KEY: x Philips BUK553-60A+ Philips BUK555-100A

Philips BUK627-500BFig. 11 Avalanche energy density against peak power

density

Ruggedness ratings.

It should be stressed that the avalanche energiespresentedin the previous section result in a rise of the junctiontemperature far in excessof the device rating and in practiceenergies should be kept within the specification.Ruggedness is specified in data for each device in termsof an unclamped inductive load test maximum condition;recommended energy dissipation at a particular current(usually the rated current of the device).

DEVICE RDSON VDS ID WDSS

TYPE (Ω) (V) (A) (mJ)

BUK552-60A 0.15 60 14 30

BUK552-100A 0.28 100 10 30

BUK553-60A 0.085 60 20 45

BUK553-100A 0.18 100 13 70

Table 1 Ruggedness Ratings

The ruggedness rating is chosen to protect against a risein Tj above the maximum rating. Examples of ruggednessratings for asmall selection ofdevices are shown in Table 1.

Fig. 12 Normalised temperature derating curve

This data is applicable for Tj = 25 C. For higher operatingtemperatures the permissible rise in junction temperatureduring the energy test is reduced. Consequentlyruggedness needs to be derated with increasing operatingtemperature. A normalised derating curve for devices withTj max 175 ˚C is presented in Fig. 12.

20 40 60 80 100 120 140 160 180Tmb / C

120

110

100

90

80

70

60

50

40

30

20

10

0

WDSS%

65


Fig. 13(a) Test circuit

Fig. 13(b) Output from transient generator.

Performance of a rugged Power MOSdevice.The ability of a rugged Power MOS transistor to survivemomentary power surges results in excellent devicereliability. The response of a BUK553-60A to interferencespikes while switching a load is presented below. The test

circuit is shown in Fig. 13(a) together with the profile of theinterference spike in Fig. 13(b).

The interference generator produces pulses asynchronousto the switching frequency of the Power MOS. Figure 14shows the drain voltage and load current response at fourinstances in the switching cycle. Devices were subjectedto 5000 interference spikes at a frequency of 5 Hz. Nodegradation in device performance was recorded.

Conclusions.The ability of power MOS devices to dissipate energy in theavalanche mode has been made possible by processoptimisation to remove the possibility of turn-on of theparasitic bipolar structure. The failure mechanism of arugged device is one of excessive junction temperatureinitiating a collapse in the terminal voltage as the junctionarea becomes intrinsic. The rise in junction temperature isdictated by the power density dissipation which is a functionof crystal size, breakdown voltage and circuit current.

Ruggedness ratings for Philips PowerMOS are chosen toensure that the specified maximum junction temperature ofthe device is not exceeded.

References.1. DUNN and NUTTALL, An investigation of the voltage

sustained by epitaxial bipolar transistors in currentmode second breakdown. Int.J.Electronics, 1978,vol.45, no.4, 353-372

2. DOW and NUTTALL, A study of the current distributionestablished in npn epitaxial transistors during currentmode second breakdown. Int.J.Electronics, 1981,vol.50, no.2, 93-108

T.U.T.

50 R

VDS

7.5 V

014 V DC

SOURCE

TRANSIENT

GENERATOR

14 V38 WLAMP

20 R

100 Hz - 1 kHz

50 % DUTY CYCLE

SQUARE WAVE

t1 = point of turn-on of PowerMOSt2 = point of turn-off of PowerMOS

Fig. 14 VDS and ID waveforms for the circuit in Fig. 13(a)

66


1.2.9 Understanding the Data Sheet: PowerMOS

All manufacturers of power MOSFETs provide a data sheetfor every type produced. The purpose of the data sheet isprimarily to give an indication as to the capabilities of aparticular product. It is also useful for the purpose ofselecting device equivalents between differentmanufacturers. In some cases however data on a numberof parameters may be quoted under subtly differentconditions by different manufacturers, particularly onsecond order parameters such as switching times. Inaddition the information contained within the data sheetdoes not always appear relevant for the application. Usingdata sheets and selecting device equivalents thereforerequires caution and an understanding of exactly what thedata means and how it can be interpreted. Throughout thischapter the BUK553-100A is used as an example, thisdevice is a 100 V logic level MOSFET.

Information contained in the Philips datasheet

The data sheet is divided into 8 sections as follows:

* Quick reference data

* Limiting values

* Thermal resistances

* Static characteristics

* Dynamic characteristics

* Reverse diode limiting values and characteristics

* Avalanche limiting value

* Graphical data

The information contained within each of these sections isnow described.

Quick reference data

This data is presented for the purpose of quick selection. Itlists what is considered to be the key parameters of thedevice such that a designer can decide at a glance whetherthe device is likely to be the correct one for the applicationor not. Five parameters are listed, the two most importantare the drain-source voltage VDS and drain-source on-stateresistance, RDS(ON). VDS is the maximum voltage the devicewill support between drain and source terminals in theoff-state. RDS(ON) is the maximum on-state resistance at thequoted gate voltage, VGS, and a junction temperature of25 ˚C. (NB RDS(ON) is temperature dependent, see staticcharacteristics). It is these two parameters which providea first order indication of the devices capability.

A drain current value (ID) and a figure for total powerdissipation are also given in this section. These figuresshould be treated with caution since they are quoted forconditions that are rarely attainable in real applications.(See limiting values.) For most applications the usable dccurrent will be less than the quoted figure in the quickreference data. Typical power dissipations that can betolerated by the majority of designers are less than 20 W(for discrete devices), depending on the heatsinkingarrangement used. The junction temperature (TJ) is usuallygiven as either 150 ˚C or 175 ˚C. It is not recommendedthat the internal device temperature be allowed to exceedthis figure.

Limiting valuesThis table lists the absolute maximum values of sixparameters. The device may be operated right up to thesemaximum levels however they must not be exceeded, todo so may incur damage to the device.

Drain-source voltageand drain-gate voltage have the samevalue. The figure given is the maximum voltage that maybe applied between the respective terminals. Gate-sourcevoltage, ±VGS, gives the maximum value that may beallowed between the gate and source terminals. To exceedthis voltage, even for the shortest period can causepermanent damage to the gate oxide. Two values for thedc drain current, ID, are quoted, one at a mounting basetemperature of 25 ˚C and one at a mounting basetemperature of 100 ˚C. Again these currents do notrepresent attainable operating levels. These currents arethe values that will cause the junction temperature to reachits maximum value when the mounting base is held at thequoted value. The maximum current rating is therefore afunction of the mounting base temperature and the quotedfigures are just two points on the derating curve ,see Fig.1.

The third current level quoted is the pulse peak value, IDM.PowerMOS devices generally speaking have a very highpeak current handling capability. It is the internal bond wireswhich connect to the chip that provide the final limitation.The pulse width for which IDM can be applied depends uponthe thermal considerations (see section on calculatingcurrents.) The total power dissipation, Ptot, and maximumjunction temperature are also stated as for the quickreference data. The Ptot figure is calculated from the simplequotient given in equation 1 (see section on safe operatingarea). It is quoted for the conditionwhere the mounting basetemperature is maintained at 25 ˚C. As an example, for theBUK553-100A the Ptot figure is 75 W, dissipating thisamount of power while maintaining the mounting base at25 ˚C would be a challenge! For higher mounting basetemperatures the total power that can be dissipated is less.

69


Fig.1 Normalised continuous drain current.ID% = 100 . ID/ID25 ˚C = f(Tmb); conditions: VGS ≥ 5 V

Obviously if the mounting base temperature was madeequal to the max permitted junction temperature, then nopower could be dissipated internally. A derating curve isgiven as part of the graphical data, an example is shown inFig.2 for a device with a limiting Tj of 175 ˚C.

Fig.2 Normalised power dissipation.PD% = 100 PD/PD 25 ˚C = f(Tmb)

Storage temperature limits are also quoted, usuallybetween -40 /-55 ˚C and +150 /+175 ˚C. Both the storagetemperature limits and the junction temperature limit arefigures at which extensive reliability work is performed byour Quality department. To exceed these figures will causea reduction in long-term reliability.

Thermal resistance.For non-isolated packages two thermal resistance valuesare given. The value from junction to mounting base (Rthj-mb)indicates how much the junction temperature will be raisedabove the temperature of the mounting base whendissipating a given power. Eg a BUK553-100A has a Rthj-mb

of 2 K/W, dissipating 10 W, the junction temperature will be20 ˚C above the temperature of its mounting base. Theother figure quoted is from junction to ambient. This is amuch larger figure and indicates how the junctiontemperature will rise if the device is NOT mounted on aheatsink but operated in free air. Eg for a BUK553-100A,Rthj-a = 60 K/W, dissipating 1 W while mounted in free airwill produce a junction temperature 60 ˚C above theambient air temperature.

For isolated packages, (F-packs) the mounting base (themetal plate upon which the silicon chip is mounted) is fullyencapsulated in plastic. Therefore it is not possible to givea thermal resistance figure junction to mounting base.Instead a figure is quoted from junction to heatsink, Rthj-hs,which assumes the use of heatsink compound. Care shouldbe taken when comparing thermal resistances of isolatedand non-isolated types. Consider the following example:

The non-isolated BUK553-100A has a Rthj-mb of 2 K/W. Theisolated BUK543-100A has a Rthj-hs of 5 K/W. These deviceshave identical crystals but mounted in different packages.At first glance the non-isolated type might be expected tooffer much higher power (and hence current) handlingcapability. However for the BUK553-100A the thermalresistance junction to heatsink has to be calculated, thisinvolves adding the extra thermal resistance betweenmounting base and heatsink. For most applications someisolation is used, such as a mica washer. The thermalresistance mounting base to heatsink is then of the order2 K/W. The total thermal resistance junction to heatsink istherefore

Rthj-hs (non isolated type) = Rthj-mb + Rthmb-hs = 4 K/W

It can be seen that the real performance difference betweenthe isolated and non isolated types will not be significant.

Static CharacteristicsThe parameters in this section characterise breakdownvoltage, threshold voltage, leakage currents andon-resistance.

A drain-source breakdown voltage is specified as greaterthan the limiting value of drain-source voltage. It can bemeasured on a curve tracer, with gate terminal shorted tothe source terminal, it is the voltage at which a drain currentof 250 µA is observed. Gate threshold voltage, VGS(TO),indicates the voltage required on the gate (with respect tothe source) to bring the device into its conducting state. Forlogic level devices this is usually between 1.0 and 2.0 Vand for standard devices between 2.1 and 4 V.

0 20 40 60 80 100 120 140 160 180Tmb / C

ID% Normalised Current Derating120

110

100

90

80

70

60

50

40

30

20

10

0

0 20 40 60 80 100 120 140 160 180Tmb / C

PD% Normalised Power Derating120

110

100

90

80

70

60

50

40

30

20

10

0

70


Fig.3 Typical transfer characteristics.ID = f(VGS); conditions: VDS = 25 V; parameter Tj

Useful plots in the graphical data are the typical transfercharacteristics (Fig.3) showing drain current as a functionof VGS and the gate threshold voltage variation with junctiontemperature (Fig.4). An additional plot also provided is thesub-threshold conduction, showing how the drain currentvaries with gate-source voltage below the threshold level(Fig.5).

Off-state leakage currents are specified for both thedrain-source and gate-source under their respectivemaximum voltage conditions. Note, although gate-sourceleakage current is specified in nano-amps, values aretypically of the order of a few pico-amps.

Fig.4 Gate threshold voltage.VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS

Fig.5 Sub-threshold drain current.ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS

Fig.6 Typical output characteristics, Tj = 25 ˚C.ID = f(VDS); parameter VGS

The drain-source on-resistance is very important. It isspecifiedat a gate-source voltage of 5 V for logic level FETsand 10 V for a standard device. The on-resistance for astandard MOSFET cannot be reduced significantly byincreasing the gate source voltage above 10 V. Reducingthe gate voltage will however increase the on-resistance.For the logic level FET, the on-resistance is given for a gatevoltage of 5 V, a further reduction is possible however atgate voltages up to 10 V, this is demonstrated by the outputcharacteristics, Fig.6 and on-resistance characteristics,Fig.7 for a BUK553-100A. .

0 2 4 6 8

BUK543-100A

VGS / V

15

10

5

0

ID / A

Tj / C = 25 150

0 0.4 0.8 1.2 1.6 2 2.4VGS / V

ID / A1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

SUB-THRESHOLD CONDUCTION

2 % typ 98 %

0 2 4 6 8 10

BUK553-100A

VDS / V

24

20

16

12

8

4

0 2

3

4

57

10ID / A

VGS / V =

-60 -20 20 60 100 140 180Tj / C

VGS(TO) / V

2

1

0

max.

typ.

min.

71


The on-resistance is a temperature sensitive parameter,between 25 ˚C and 150 ˚C it approximately doubles invalue. A plot of normalised RDS(ON) versus temperature(Fig.8) is included in each data sheet. Since the MOSFETwill normally operate at a Tj higher than 25 ˚C, when makingestimates of power dissipation in the MOSFET, it isimportant to take into account the higher RDS(ON).

Fig.7 Typical on-state resistance, Tj = 25 ˚C.RDS(ON) = f(ID); parameter VGS

Fig.8 Normalised drain-source on-state resistance.a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 6.5 A; VGS = 5 V

Dynamic Characteristics

These include transconductance, capacitance andswitching times. Forward transconductance, gfs, isessentially the gain parameter which indicates the changein drain current that will result from a fluctuation in gatevoltage when the device is saturated. (NB saturation of a

MOSFET refers to the flat portion of the outputcharacteristics.) Fig.9 shows how gfs varies as a function ofthe drain current for a BUK553-100A.

Fig.9 Typical transconductance, Tj = 25 ˚C.gfs = f(ID); conditions: VDS = 25 V

Fig.10 Typical capacitances, Ciss, Coss, Crss.C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Capacitances are specified by most manufacturers, usuallyin terms of input, output and feedback capacitance. Thevalues quoted are for a drain-source voltage of 25 V.However this is only part of the story as the MOSFETcapacitances are strongly voltage dependent, increasingasdrain-source voltage is reduced. Fig.10showshow thesecapacitances vary with voltage. The usefulness of thecapacitance figures is limited. The input capacitance valuegives only a rough indication of the charging required bythe drive circuit. Perhaps more useful is the gate chargeinformation an example of which is shown in Fig.11. Thisplot shows how much charge has to be input to the gate to

0 2 4 6 8 10 12 14 16 18 20

BUK543-100A

ID / A

gfs / S10

9

8

7

6

5

4

3

2

1

0

0 4 8 12 16 20 24 28

BUK553-100A

ID / A

0.5

0.4

0.3

0.2

0.1

0

2.5 3 3.5 44.5

5

10

RDS(ON) / Ohm

VGS / V =

0 20 40VDS / V

C / pF

Ciss

Coss

Crss

10

100

1000

10000BUK5y3-100

-60 -20 20 60 100 140 180Tj / C

Normalised RDS(ON) = f(Tj)2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

a

72


reach a particular gate-source voltage. Eg. to charge aBUK553-100A to VGS = 5 V, starting from a drain-sourcevoltage of 80 V, requires 12.4 nc. The speed at which thischarge is to be applied will give the gate circuit currentrequirements. More information on MOSFET capacitanceis given in chapter 1.2.2.

Resistive load switching times are also quoted by mostmanufacturers, however extreme care should be takenwhen making comparisons between differentmanufacturers data. The speed at which a power MOSFETcan be switched is essentially limited only by circuit andpackage inductances. The actual speed in a circuit isdetermined by how fast the internal capacitances of theMOSFET are charged and discharged by the drive circuit.The switching times are therefore extremely dependent onthe circuit conditions employed; a low gate drive resistancewill provide for faster switching and vice-versa. The Philipsdata sheet presents the switching times for all PowerMOSwith a resistor between gate and source of 50 Ω. The deviceis switched from apulse generator with a source impedancealso of 50 Ω. The overall impedance of the gate drive circuitis therefore 25 Ω.

Fig.11 Typical turn-on gate-charge characteristics.VGS = f(QG); conditions: ID = 13 A; parameter VDS

Also presented under dynamic characteristics are thetypical inductances of the package. These inductancesbecome important when very high switching speeds areemployed such that large dI/dt values exist in the circuit.Eg. turning-on 30 A within 60 ns gives a dI/dt of 0.5 A/ns.The typical inductance of the source lead is 7.5 nH, fromV = -L*dI/dt the potential drop from the source bond pad(point where the source bond wire connects to the chipinternally) to the bottom of the source lead would be 3.75 V.Normallya standarddevice will be driven with agate-sourcevoltage of 10 V applied across the gate and sourceterminals, the actual voltage gate to source on the

semiconductor however would only be 6.25 V during theturn-on period! The switching speed is therefore ultimatelylimited by package inductance.

Reverse diode limiting values andcharacteristicsThe reverse diode is inherent in the vertical structure of thepower MOSFET. In some circuits this diode is required toperformauseful function. For this reasonthe characteristicsof the diode are specified. The forward currents permissiblein the diode are specified as ’continuous reverse draincurrent’ and ’pulsed reverse drain current’. The forwardvoltage drop of the diode is also provided together with aplot of the diode characteristic, Fig.12. The switchingcapability of the diode is given in terms of the reverserecovery parameters, trr and Qrr.

Fig.12 Typical reverse diode current.IF = f(VSDS); conditions: VGS = ) V; parameter Tj

Because the diode operates as a bipolar device it is subjectto charge storage effects. This charge must be removed forthe diode to turn-off. The amount of charge stored is givenby Qrr, the reverse recovery charge, the time taken to extractthe charge is given by trr, the reverse recovery time. NB. trrdepends very much on the -dIf/dt in the circuit, trr is specifiedin data at 100 A/µs.

Avalanche limiting valueThis parameter is an indication as to the ruggedness of theproduct in terms of its ability to handle a transientovervoltage, ie the voltage exceeds the drain-sourcevoltage limiting value and causes the device to operate inan avalanche condition. The ruggedness is specified interms of a drain-source non-repetitive unclamped inductiveturn-off energy at a mounting base temperature of 25 ˚C.This energy level must be derated at higher mounting basetemperatures as shown in Fig.13. NB. this rating is

0 1 2

BUK553-100A

VSDS / V

30

20

10

0

IF / A

Tj / C = 150 25

0 2 4 6 8 10 12 14 16 18 20QG / nC

VGS / V12

10

8

6

4

2

0

VDS / V =20

80

BUK553-100

73


non-repetitive which means the circuit should not bedesigned to force the PowerMOS repeatedly intoavalanche. This rating is only to permit the device to surviveif exceptional circuit conditions arise such that a transientovervoltage occurs.

The new generation of Philips Medium Voltage MOSFETsalso feature a repetitive ruggedness rating. This rating isspecified in terms of a drain-source repetitive unclampedinductive turn-off energy at a mounting base temperatureof25 ˚C, and indicates that the devices are able to withstandrepeated momentary excursions into avalanchebreakdown provided the maximum junction temperature isnot exceeded. (A more detailed explanation of Ruggednessis given in chapter 1.2.7.)

Fig.13. Normalised avalanche energy rating.WDSS% = f(Tmb); conditions: ID = 13 A

Safe Operating AreaA plot of the safe operating area is presented for everyPowerMOS type. Unlike bipolar transistors a PowerMOSexhibits no second breakdown mechanism. The safeoperating area is therefore simply defined from the powerdissipation that will cause the junction temperature to reachthe maximum permitted value.

Fig.14 shows the SOA for a BUK553-100. The area isbounded by the limiting drain source voltage, limitingcurrent values and a set of constant power curves forvarious pulse durations. The plots in data are all for amounting base temperature of 25 ˚C. The constant powercurves therefore represent the power that raises thejunction temperature by an amount Tjmax - Tmb, ie. 150 ˚Cfor a device with a limiting Tj of 175 ˚C and 125 ˚C for adevice with a limiting Tj of 150 ˚C. . Clearly in mostapplications the mounting base temperature will be higherthan 25 ˚C, the SOA would therefore need to be reduced.The maximum power curves are calculated very simply.

Fig.14 Safe operating area. Tmb = 25 ˚CID & IDM = f(VDS); IDM single pulse; parameter tp

The dc curve is based upon the thermal resistance junctiontomounting base (junction to heatsink in the caseof isolatedpackages), which is substituted into equation 1. The curvesforpulsed operation assumea single shot pulseand insteadof thermal resistance, a value for transient thermalimpedance is used. Transient thermal impedance issupplied as graphical data for each type, an example isshown in Fig.15. For calculation of the single shot powerdissipation capability, a value at the required pulse width isread from the D = 0 curve and substituted in to equation 2.(A more detailed explanation of transient thermalimpedance and how to use the curves can be found inchapter 7.)

Examples of how to calculate the maximum powerdissipation for a 1 ms pulse are shown below. Example 1calculates the maximum power assuming a Tj of 175 ˚C andTmb of 25 ˚C. This power equates to the 1 ms curve on theSOA plot of Fig.14. Example 2 illustrates how the powercapability is reduced if Tmb is greater than 25 ˚C.

Example 1: 1 ms pulse at 25 ˚C for a BUK553-100A

Zth = 0.32 K/W, Tjmax = 175 ˚C, Tmb = 25 ˚C

1 100VDS / V

ID / A100

10

1

0.1

10 us

100 us

1 ms

10 ms

RDS(ON) =

VDS/ID

100 ms DC

tp =

BUK553-100

10

B

A

20 40 60 80 100 120 140 160 180Tmb / C

120

110

100

90

80

70

60

50

40

30

20

10

0

WDSS%

Ptot (dc) =Tjmax − Tmb

Rthj − mb

1

Ptot (pulse) =Tjmax − Tmb

Zthj − mb

2

74


Fig.15 Transient thermal impedance.Zthj-mb = f(t); parameter D = tp/T

The 469 W line is observed on Fig.13, (4.69 A @ 100 V and15.6 A @ 30 V etc)

Example 2: 1 ms pulse at 75 ˚C for a BUK553-100A

Zth = 0.32 K/W, Tjmax = 175 ˚C, Tmb = 75 ˚C

Therefore with a mounting base temperature of 75 ˚C themaximum permissible power dissipation is reduced by onethird compared with the 25 ˚C value on the SOA plot.

Calculating CurrentsThe current ratings quoted in the data sheet are deriveddirectly from the maximum power dissipation.

substituting for Ptot from equation 1

To calculate a more realistic current it is necessary toreplace Tjmax in equation 4 with the desired operatingjunction temperature and Tmb with a realistic working value.It is generally recommended that devices are not operatedcontinuously at Tjmax. For reasons of long term reliability,125 ˚C is a more suitable junction operating temperature.A value of Tmb between 75 ˚C and 110 ˚C is also a moretypical figure.

As an example a BUK553-100A is quoted as having a dccurrent rating of 13 A. Assuming a Tmb of 100 ˚C andoperating Tj of 125 ˚C the device current is calculated asfollows:

From Fig.8

Rthj-mb = 2 K/W, using equation 4

The device could therefore conduct 6.3 A under theseconditions which equates to a 12.5 W power dissipation.

Conclusions

The most important information presented in the data sheetis the on-resistance and the maximum voltagedrain-source. Current values and maximum powerdissipation values should be viewed carefully since theyare only achievable if the mounting base temperature isheld to 25 ˚C. Switching times are applicable only for thespecific conditions described in the data sheet, whenmaking comparisons between devices from differentmanufacturers, particular attention should be paid to theseconditions.

ID(@Tmb) =

Tjmax − Tmb

Rthj − mb ⋅ RDS(ON)(@Tjmax)

1

2

4

1E-07 1E-05 1E-03 1E-01 1E+01t / s

Zth j-mb / (K/W)1E+01

1E+00

1E-01

1E-02

1E-03

0

0.5

0.20.1

0.05

0.02

BUKx53-lv

D = tp tp

T

TP

t

D

D =

RDS(ON)(@125oC) = 1.75⋅ RDS(ON)(@25oC) = 1.75⋅ 0.18= 0.315ΩPmax(1ms pulse) =

175− 250.32

= 469W

ID =

252 ⋅ 0.315

1

2

= 6.3A

Pmax(1ms pulse) =175− 75

0.32= 312W

ID(@Tmb)2 ⋅ RDS(ON)(@Tjmax) = Ptot 3

75

1.2.1 PowerMOS Introduction - ghioni.faculty.polimi.it · Philips Semiconductors A cross-section...

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