(108632885) Can Bus vs i2c vs Serial vs Parallel - Copy

8/13/2019 (108632885) Can Bus vs i2c vs Serial vs Parallel - Copy

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REPORT 1

I-SERIAL AND PARALLEL PORTS COMPARISON:

Serial port has all the advantages of serial data transmission:

1. The serial port cable can be longer than a parralel port cable, as serial port

transmits '1' as voltage from -5 to -12V and '0' as voltage from 5 to 12 V,

!hile parralel port transmits '1' as voltage of 5 volts and '0' as voltage of 0

volts. "t the same time the receiver of the serial port receives '1' as voltage

from -# to -25 V and '0' as voltage from # to 25 V. Th$s serial port can have

ma%imal s!ing $p to 50 volts, !hile parralel port has ma%imal s!ing of 5

volts. Th$s the losses in the cable !hen transmitting data $sing serial port are

less s$bstantial then losses !hen transmitting data $sing parralel port.

2. The n$mber of !ires needed !hen transmitting data seriall& is less than !hen

the transmission is parallel. s the e%ternal device has to be installed at a greatdistance from the comp$ter, the cable !ith three !ires is m$ch cheaper than

the cable !ith 1( or 25 !ires if the transmission is parallel. Still one sho$ld

remember that there are interface creation e%pences for ever&

receiver)transmitter.

#. *$rther development of serial port is $sage of infrared devices !hich

immediatel& proved pop$lar. +an& electronic diaries and palmtop comp$ters

have inb$ilt infrared devices for connection !ith e%ternal devices.

. "nother proof of serial port $niversalit& is microcontrollers. +an& of them

have inb$ilt S Serial omm$nications nterfaces/, $sed for comm$nication

!ith other devices. n this case serial interface red$ces the n$mber of o$tp$ts

on the chip. s$all& onl& 2 o$tp$ts are $sed: Transmit ata T/ and3eceive ata 3/. 4$st compare that to minim$m of o$tp$ts !hen $sing

-bit parralel connection.

S$rel& eno$gh serial port has its dra!bac6s. The main one is that !hen organi7ing

serial connection it is al!a&s necessar& to convert the data into serial code and vice

versa.

Note : I2C and CAN are serial communication rotocols !so t"e# $ill %e

comared to eac" ot"ers &


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II-'o$ CAN()S *OR+S

The "8 is a 9broadcast9 t&pe of b$s. That means there is no e%plicit address in the

messages. "ll the nodes in the net!or6 are able to pic6-$p or receive all

transmissions. There is no !a& to send a message to $st a specific node. To be more

specific, the messages transmitted from an& node on a "8 b$s does not containaddresses of either the transmitting node, or of an& intended receiving node. nstead,

an identifier that is $ni;$e thro$gho$t the net!or6 is $sed to label the content of the

message. $t !hat !ill happen in sit$ations!here t!o or more nodes attempt to transmit message to the "8 b$s/ at the same

time. The identifier field, !hich is $ni;$e thro$gho$t the net!or6 helps to determine

the priorit& of the message. " 9non-destr$ctive arbitration techni;$e9 is $sed to

accomplish this, to ens$re that the messages are sent in order of priorit& and that no

messages are lost. The lo!er the n$merical val$e of the identifier, the higher the

priorit&. That means the message !ith identifier having more dominant bits i.e. bit 0/

!ill over!rite other nodes' less dominant identifier so that event$all& after the

arbitration on the / onl& the dominant message remains and is received b& all

nodes.

"s stated earlier, "8 do not $se address-based format for comm$nication, instead

$ses a message-based data format. ?ere the information is transferred from one

location to another b& sending a gro$p of b&tes at one time depending on the order of

priorit&/. This ma6es "8 ideall& s$ited in applications re;$iring a large n$mber of

short messages e.g.: transmission of temperat$re and rpm information/. b& more than

one location and s&stem-!ide data consistenc& is mandator&. The traditional

net!or6s s$ch as S> or


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cases, the net!or6 need not have a controller node= each node can easil& be connected

to the main b$s directl&./

The "8 ontroller stores received bits one b& one/ from the b$s $ntil an entire

message bloc6 is available, that can then be fetched b& the host processor $s$all&

after the "8 ontroller has triggered an interr$pt/. The an transciever adapts

signal levels from the b$s, to levels that the "8 ontroller e%pects and also providesa protective circ$itr& for the "8 ontroller. The host-processor decides !hat the

received messages mean, and !hich messages it !ants to transmit itself.

*ig 1-a

t is li6el& that the more rapidl& changing parameters need to be transmitted more

fre;$entl& and, therefore, m$st be given a higher priorit&. ?o! this high-priorit& is

achievedA "s !e 6no!, the priorit& of a "8 message is determined b& the

n$merical val$e of its identifier. The n$merical val$e of each message identifier andth$s the priorit& of the message/ is assigned d$ring the initial phase of s&stem design.

To determine the priorit& of messages !hile comm$nication/, "8 $ses the

established method 6no!n as S+") !ith the enhanced capabilit& of non-

destr$ctive bit-!ise arbitration to provide collision resol$tion and to e%ploit the

ma%im$m available capacit& of the b$s. 9arrier Sense9 describes the fact that a

transmitter listens for a carrier !ave before tr&ing to send. That is, it tries to detect the

presence of an encoded signal from another station before attempting to transmit. f a

carrier is sensed, the node !aits for the transmission in progress to finish before

initiating its o!n transmission. 9+$ltiple "ccess9 describes the fact that m$ltiple

nodes send and receive on the same medi$m. "ll other nodes $sing the medi$m

generall& receive transmissions b& one node. 9ollision etection9 / means that

collisions are resolved thro$gh a bit-!ise arbitration, based on a preprogrammed

priorit& of each message in the identifier field of a message.


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*ig 1-b

T?< term 9priorit&9 becomes more important in the net!or6.


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d/ "nother $sef$l feat$re b$ilt into the "8 protocol is the abilit& of a node to

re;$est information from other nodes. This is called a remote transmit re;$est, or

3T3.

e/ The $se of 83E encoding ens$res compact messages !ith a minim$m n$mber of

transitions and high resilience to e%ternal dist$rbance.

f/ "8 protocol can lin6 $p to 20#2 devices ass$ming one node !ith one identifier/on a single net!or6. >$t acco$nting to the practical limitations of the hard!are

transceivers/, it ma& onl& lin6 $p to 110 nodes on a single net!or6.

g/ ?as an e%tensive and $ni;$e error chec6ing mechanisms.

h/ ?as ?igh imm$nit& to ase frame format

b/


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*rame and a re;$est for data from a remote node.

c/ " ontrol *ield containing si% bits in !hich t!o reserved bits r0 and r1/ and a fo$r

bit ata @ength ode @/. The @ indicates the n$mber of b&tes in the ata

*ield that follo!s.

d/ " ata *ield, containing from 7ero to eight b&tes.

e/ The 3 field, containing a fifteen-bit c&clic red$ndanc& chec6-code and arecessive delimiter bit.

f/ The "c6no!ledge field, consisting of t!o bits. The first one is a Slot bit !hich is

transmitted as recessive, b$t is s$bse;$entl& over !ritten b& dominant bits transmitted

from an& node that s$ccessf$ll& receives the transmitted message. The second bit is a

recessive delimiter bit.

g/ The it +onitoring.

2. >it St$ffing.#. *rame hec6.


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. "c6no!ledgement hec6.

5. &clic 3ed$ndanc& hec6

1.


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enter the >$s Bff state, !hich means that the node doesn't participate in the b$s traffic

at all. >$t the comm$nications bet!een the other nodes can contin$e $nhindered.

To be more specific, an 9$s Bff, the other nodes !ill have a co$nt in their 3eceive


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the local oscillator, m$ltiplied b& the val$e in the >a$d 3ate Fre-scaler >3F/ register

in the "8 controller.

#. " bit edge is e%pected to ta6e place d$ring this s&nchroni7ation segment !hen the

data changes on the b$s.

. Fropagation segment is $sed to compensate for ph&sical dela& times !ithin the

net!or6 b$s lines. "nd is programmable from one to eight time ;$anta long.5. Fhase-segment1 is a b$ffer segment that can be lengthened d$ring

res&nchroni7ation to compensate for oscillator drift and positive phase differences

bet!een the oscillators of the transmitting and receiving nodes. "nd is also

programmable from one to eight time ;$anta long.

I. Fhase-segment2 can be shortened d$ring res&nchroni7ation to compensate for

negative phase errors and oscillator drift. "nd is the ma%im$m of Fhase-segment1

combined !ith the nformation Frocessing Time.

H. The Sample point !ill al!a&s be at the end of Fhase-seg1. t is the time at !hich

the b$s level is read and interpreted as the val$e of the c$rrent bit.

. The nformation Frocessing Time is less than or e;$al to 2 time ;$anta.

This bit time is programmable at each node on a "8 >$s. >$t be a!are that all

nodes on a single "8 b$s m$st have the same bit time regardless of transmitting or

receiving. The bit time is a f$nction of the period of the oscillator local to each node,

the val$e that is $ser-programmed into >3F register in the controller at each node,

and the programmed n$mber of time ;$anta per bit.

?o! do the& s&nchroni7e:

S$ppose a node receives a data frame. Then it is necessar& for the receiver to

s&nchroni7e !ith the transmitter to have proper comm$nication. >$t !e don't have

an& e%plicit cloc6 signal that a "8 s&stem can $se as a timing reference. nstead, !e

$se t!o mechanisms to maintain s&nchroni7ation, !hich is e%plained belo!.

?ard s&nchroni7ation:

t occ$rs at the Start-of-*rame or at the transition of the start bit. The bit time is

restarted from that edge.

3es&nchroni7ation:

To compensate for oscillator drift, and phase differences bet!een transmitter and

receiver oscillators, additional s&nchroni7ation is needed. The res&nchroni7ation for

the s$bse;$ent bits in an& received frame occ$rs !hen a bit edge doesn't occ$r !ithin

the S&nchroni7ation Segment in a message. The res&nchroni7ation is a$tomaticall&

invo6ed and one of the Fhase Segments are shortened or lengthened !ith an amo$nt

that depends on the phase error in the signal. The ma%im$m amo$nt that can be $sed

is determined b& a $ser-programmable n$mber of time ;$anta 6no!n as the

S&nchroni7ation 4$mp Cidth parameter S4C/.

?igher @a&er Frotocols:

?igher la&er protocol ?@F/ is re;$ired to manage the comm$nication !ithin a

s&stem. The term ?@F is derived from the BS model and its seven la&ers. >$t the"8 protocol $st specifies ho! small pac6ets of data ma& be transported from one


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point to another safel& $sing a shared comm$nications medi$m. t does not contain

an&thing on the topics s$ch as flo! control, transportation of data larger than "8 fit

in an -b&te message, node addresses, establishment of comm$nication, etc. The ?@F

gives sol$tion for these topics.

?igher la&er protocols are $sed in order to

1. Standardi7e start$p proced$res incl$ding bit rate setting2. istrib$te addresses among participating nodes or 6inds of messages

#. etermine the la&o$t of the messages

. Frovide ro$tines for error handling on s&stem level

ifferent ?igher @a&er Frotocols

There are man& higher la&er protocols for the "8 b$s. Some of the most commonl&

$sed ones are given belo!.

1. an Gingdom

2. "8 open

#. F)F

. evice 8et

5. 41(#(I. BS


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III- ISC 'O* IT *OR+S,

J is a m$lti-master, lo!-band!idth, short distance, serial comm$nication b$s

protocol. 8o!ada&s it is not onl& $sed on single boards, b$t also to attach lo!-speed

peripheral devices and components to a motherboard, embedded s&stem, or cell-

phone, as the ne! versions provide lot of advanced feat$res and m$ch higher speed.The feat$res li6e simplicit& D fle%ibilit& ma6e this b$s attractive for cons$mer and

a$tomotive electronics.

Details:

The basic design of J has a H-bit address space !ith 1I reserved addresses, !hich

ma6es the ma%im$m n$mber of nodes that can comm$nicate on the same b$s as 112.

That means each J device is recogni7ed b& a $ni;$e H-bit address. t is important to

note that the ma%im$m n$mber of nodes is obvio$sl& limited b& the address space,

and also b& the total b$s capacitance of 00 pf.

The t!o bi-directional lines, !hich carr& information bet!een the devices connected

to the b$s, are 6no!n as Serial ata line S"/ and Serial loc6 line S@/. "s the

name indicates the S" line contains the data and the S@ !ith the cloc6 signal for

s&nchroni7ation. The t&pical voltages $sed are 5 V or #.#V.

@i6e the "8 D @8 protocols, the J also follo!s the master-slave comm$nication

protocol. >$t the J b$s is a m$lti-master b$s, !hich means more than one )device

capable of initiating a data transfer can be connected to it. The device that initiates the

comm$nication is called +"ST


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T"e real communication:

"s !e sa! alread&, the active lines $sed for comm$nication in J protocol are bi-

directional. oth the master and slave can receive or transmit data

depending on !hether the comm$nication is a read or !rite. The transmitter sends

-bits of data to the receiver, !hich replies !ith a 1-bit ac6no!ledgement. "nd the

action of data transfer contin$es.

. Chen the comm$nication is complete, the master iss$es a stop condition indicating

that ever&thing is done. This action free $ps the b$s. The stop signal is $st one bit

of information transferred b& a special '!iggling' of the S")S@ !ires of the b$s.


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8otes:

1. evices !ith +aster capabilit& can identif& themselves to other specific +aster

devices and advise their o!n specific address and f$nctionalit&.

2. Bnl& t!o devices e%change data d$ring one 'conversation'

The tric6 of open-drain lines D p$ll-$p resistors:

The b$s interface in J is b$ilt aro$nd an inp$t b$ffer and an open drain transistor.

Chen the b$s is in 9idle9 state, the b$s lines are 6ept in the logic 9high9 state. The

e%ternal p$ll-$p resistors are $sed for this condition to achieve. This p$ll-$p resistor

as seen in the fig-1 is act$all& a small c$rrent so$rce. f the device !ants to p$t a

signal on the b$s, the chip drives its o$tp$t transistor, th$s p$lling the b$s to 9lo!9

level. S$ppose the b$s is alread& occ$pied b& another chip b& sending a 9lo!9 state to

the b$s. Then all other chips lose their right to access the b$s. The chip does this !ith

a b$ilt-in b$s mastering techni;$e.

>oth the b$s lines S" and S@ are initiall& bi-directional. This means that in a

partic$lar device, these lines can be driven b& the itself or from an e%ternal device.

n order to achieve this f$nctionalit&, these signals $se open collector or open drain

o$tp$ts.

The !ea6 point of open-collector techni;$e is, in a length& b$s the speed of

transmission comes do!n drasticall& d$e to the presence of capacitive load. The

shapes of the signals alter in proportion to 3 time constant. ?igher the 3 constant,

the slo!er !ill be the transmission. "t some point, the s !ill not be able to sense

logic 1 and 0.


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"nd also it can ca$se reflections at high speed, !hich creates 9ghost signals9 and

corr$pt the data, !hich is being transmitted.

This problem can be overcome b& $sing an active J terminator. This device consists

of a t!in charge p$mp, !hich can be considered as a d&namic resistor instead of the

passive p$ll-$p resistors $sed/. The moment the state changes, it provides a largec$rrent lo! d&namic resistance/ to the b$s. This action !ill charge the parasitic

capacitor ver& ;$ic6l&. Bnce the voltage has risen above a certain level, the high

c$rrent mode c$ts o$t and the o$tp$t c$rrent drops sharpl&.

ifferent states, conditions D events on the b$s:

Ce sa! several $ni;$e states and conditions on the b$s in o$r e%planation: ST"3T,

"3it 0 of this b&te

determines the slave access mode '1' K read ) '0' K !rite/. 3emember, b&tes are

al!a&s transmitted +S> first. The 3)C bit '0' indicates the master is !illing to send

data to the slaves. Then the intended slave !ill respond bac6 !ith "G signal,

indicating that its read& to receive. "nd the comm$nication contin$es.

n the same !a&, a b&te can be received from the slave if the 3)C bit in the address

!as set to '1', i.e. 'read'. >$t no! the master is not allo!ed to to$ch the S" line.

+aster sends the cloc6 p$lses needed to cloc6 in a b&te on the S@ line, and

releases the S" line. nstead, the slave !ill no! ta6e control of this S" line for

data transfer. "ll the master has to do no! is generate a rising edge on the S@ line,read the level on S" and generate a falling edge on the S@ line. The slave !ill not

change the data d$ring the time that S@ is high. This se;$ence has to be performed

times to complete the data b&te.

Some of the addresses are reserved for 9e%tended addressing mode9, !hich $se 10-bit

addressing. f a standard slave node, !hich is not able to resolve this e%tended

addressing receives this address, it !on't do an&thing.

AC+:

"s !e 6no! the "G signal is send bac6 to the master !henever the address or datab&te has been transmitted onto the b$s and received b& the intended slave node.


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The slave after sending "G signal !ill drive the S" line to lo! stat$s immediatel&

after receiving the th data bit transmitted b& the master or after eval$ating received

address b&te. So to signal the completion of transmission, S@ p$lled to lo! b&

master, !hereas S" is p$lled to lo! b& slave.

To repeat the transmission, master drops a cloc6 p$lse on the S@ line and slave !illrelease the S" line after receiving the cloc6. Cith this, b$s is no! read& again for

master to send data or to initiate a stop condition.

n the same !a&, the master m$st ac6no!ledge the slave device $pon s$ccessf$l

reception of a b&te from a slave.

S" and the S@ line are in f$ll control of the master. The slave !ill release the S"

line after sending last bit to the master and ma6e the S" line high. The +aster !ill

no! bring the S" line lo! state and p$t a cloc6 p$lse on the S@ line. "fter

completion of this cloc6 p$lse, the master !ill again release the S" line to allo! the

slave to regain control of the S" line.

The master can stop receiving data from the slave at an& time, $st b& sending a stop

condition.

NAC+:

8"G means 98ot "c6no!ledge9. onf$sedA on't conf$se it !ith 98o

"c6no!ledge9. >eca$se, 98ot "c6no!ledge9 occ$rs onl& after a master has read a

b&te from a slave. "nd 98o "c6no!ledge9 occ$rs after a master has !ritten a b&te to

a slave. "gain conf$sedA @ets anal&7e this in detail.

This happens !hen the slave regains control of the S" line after the "G c&cle

iss$ed b& the master.

@et's ass$me the ne%t bit read& to be sent to the master is a 0. The slave !o$ld p$ll the

S" line lo! immediatel& after the master ta6es the S@ line lo!. The master no!

attempts to generate a Stop condition on the b$s. t releases the S@ line first and then

tries to release the S" line, !hich is held lo! b& the slave. So in short, 8o Stop

condition has been generated on the b$s. This condition is called a 8"G.

No AC+:

f, after transmission of the th bit from the master to the slave the slave does not p$ll

the S" line lo!, then this is considered a 8o "G condition.

This condition ma& be created d$e to the follo!ing reasons:

1. The slave is not there in case of an address/

2. The slave missed a p$lse and got o$t of s&nc !ith the S@ line of the master.

#. The b$s is 9st$c69. Bne of the lines co$ld be held lo! permanentl&.

n an& case the master sho$ld abort b& attempting to send a stop condition on the b$s.


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STOP:

The stop state is sent to the b$s onl& after the message transfer has been completed.

The master-+ first releases the S@ and then the S" line. This condition is atr$e indication to all the chips and devices on the b$s that the b$s is idle or the b$s is

free and available again for another comm$nication.

" Stop condition denotes the


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T"e ris o0 data corrution:

The operation of the b$s !ith one master node seems to be ver& eas&. >$t !hat

happens if there are t!o masters connected to the b$s and if both of them start

comm$nicating at the same time. @et $s tr& to anal&7e this sit$ation in detail.

Chen the first + iss$es a start condition and sends an address, all slaves !ill listenincl$ding the second + !hich at that time is considered a slave as !ell/. f the

address does not match the address of the second +, it !ill hold bac6 an& activit&

$ntil the b$s becomes idle again after a stop condition.

"s long as the t!o +'s monitor !hat is going on, on the b$s start and stop/ and as

long as the& are a!are that a transaction is going on beca$se the last iss$ed command

!as not a STBF, there is no problem.

>$t, !hat !ill happen if one of the +'s missed the ST"3T condition and still

thin6s the b$s is idle, or it $st came o$t of reset and !ants to comm$nicate.

The ph&sical b$s set$p of the J helps to solve this problem. Since the b$s str$ct$re

is a !ired "8 if one device p$lls a line lo! it sta&s lo!/, its possible to find!hether the b$s is idle or occ$pied.

(ene0its and Dra$%acs:

Since onl& t!o !ires are re;$ired, 2 is !ell s$ited for boards !ith man& devices

connected on the b$s. This helps red$ce the cost and comple%it& of the circ$it as

additional devices are added to the s&stem.

$e to the presence of onl& t!o !ires, there is additional comple%it& in handling the

overhead of addressing and ac6no!ledgments. This can be inefficient in simple

config$rations and a direct-lin6 interface s$ch as SF might be preferred.

IIII-I2C AND CAN COMPARISON :

- "8 is differential, and is more imm$ne to noise

- 2 does s$pport arbitration and m$ltiple masters!hile can has onl& onemaster s$pport

- i2c !as reall& designed for tal6ing bet!een chips on the same board !hile can

is $sed to connect m$ltiple boards

- "8 onl& allo!s b&tes to be sent at a time, i2c is essentiall&

$nlimited

- Mo$ can broadcast !ith i2c, altho$gh i2c $ses node addresses for mostmessages.

- 2 t&picall& re;$ires more + overhead than "8, beca$se most of the

"8 controllers implement all of the lo! level ms in ?C.

- 2 slave devices can stretch the cloc6 to adpat the speed do!n. This is not

good if the cloc6 gets stretched indefinitel&.


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(108632885) Can Bus vs i2c vs Serial vs Parallel - Copy

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