10-09-2004

Wilco Vink 1

Outline

• Optical station• Vertex processor board• Output board• Latency

10-09-2004

Wilco Vink 2

VETO Dataflow

VETO, station B

VETO, station A

L0 decision unitTELL1

Balco

ny

Optical stationVETO front end data mixer8 mixer /optical transmitter cards1 control card (ttc SPECS)

60m 8 opt. ribbons(96 fibers @ 1.6 Gb/s)

Pile-Up VETO (trigger)Vertex finder

1024 lvds @ 80 Mb/s15m (256 cat5 cables)

Second vertex position

L0 BufferReadout

Vertex ProcBoard (2/4)

L0 Decision Unit

First vertex position

Front end crate

VETO crateVertex Proc.Board (3/4)

Shielding wall

Vertex Proc.Board (4/4)

Optical patch panel

Vertex Proc.Board (1/4)

Opticallinks

Rocket I/O

Output board

VELO vertex detector

Barra

ck

Vertex Tank

Opticallinks

10-09-2004

Wilco Vink 3

VETO Optical Station

• Single 9U crate (with 3u power backplane)

• 8 Optical transmitter boards

• cat5 cables fed in from rear via transition boards(32 RJ45 inputs each)

• 1 control unit tbd (ttc)– Possibly replaced by VELO ECS

10-09-2004

Wilco Vink 4

Veto optical transmitter Board

• Inputs: 128 lvds pairs @80Mb/s

• Synchronize inputs (de-skew/ differences in cable length)

• Data demultiplexing• Queuing event fragments • 12 GOL serializers• Output: 1 optical ribbon

Actel 54sx32PBGA329

DS90lv048alvds receivers32 x 4 lvds pairs

Actel 54sx32PBGA329

Qpll

GOL

GOL

GOL

GOL

GOL

GOL

GOL

GOL

GOL

GOL

GOL

Agilent txHFBR772b

Actel 54sx32PBGA329

Actel 54sx32PBGA329

GOL

9U optical transmitter board Power connectorto power backplane

128 LVDS pairsfrom transitionboard

3 Actel FPGA’s:-Re-timing-multiplexing

Qpll and bcid decoding FPGA

Optical transmitter12 channel VCSEL

10-09-2004

Wilco Vink 5

Synchronize differences in cable length

• Input data @80Mb/s from beetle chips

• Synchronization clock, selectable via i2c

• Maximum allowed channel to channel skew: 1 period(12.5 ns)

CLKsel2

CLK ff2

synceddata out

CLK ff3

CLK ff1

CLKA

data in

CLKB

CLKsel3

CLKsel4

CLKsel1

10-09-2004

Wilco Vink 6

Status Optical Transmitter Board

• Completed:– Functional design FPGA’s– Full timing simulation

• In progress:– Schematic entry

• To be done:– Layout (dec. 2004)

10-09-2004

Wilco Vink 7

VETO Dataflow

VETO, station B

VETO, station A

L0 decision unitTELL1

Balco

ny

Optical stationVETO front end data mixer8 mixer /optical transmitter cards1 control card (ttc SPECS)

60m 8 opt. ribbons(96 fibers @ 1.6 Gb/s)

Pile-Up VETO (trigger)Vertex finder

1024 lvds @ 80 Mb/s15m (256 cat5 cables)

Second vertex position

L0 BufferReadout

Vertex ProcBoard (2/4)

L0 Decision Unit

First vertex position

Front end crate

VETO crateVertex Proc.Board (3/4)

Shielding wall

Vertex Proc.Board (4/4)

Optical patch panel

Vertex Proc.Board (1/4)

Opticallinks

Rocket I/O

Output board

VELO vertex detector

Barra

ck

Vertex Tank

Opticallinks

10-09-2004

Wilco Vink 8

Veto vertex Processor Board

• Vertex finder in Xilinx Virtex2Pro– type XC2VP100ff1704-5

• 2 O-rx Optical input Cards

• Credit Card PC and Glue Card

• TTCrq Mezzanine Card

• Trigger decision on 1 copper serial link to output board

• 2 optical outputs to L1 buffer/DAQ (TELL1)

10-09-2004

Wilco Vink 9

Functional diagram

Trigger

Right detectormatrix

2nd peak

24, 16 bit inputsfrom O-rx cards@80Mb/s

To output board

B

Dem

ux to 40 Mhz

A

BA

PipelineBuffer

Xilinx Virtex 2Pro: XC2VP100ff1704-5

Histogram2nd peak

Coincidencematrix

Left detectormatrix

BA

BA

Right detectormatrixB

AHistogram1st peak

128

Left detectormatrix

BA

1st peak

Sync input links

1st peak2nd peakhistogram sumtrigger desc.

1st peak

Rocket I/O

Mask 1st peak

Coincidencematrix

10-09-2004

Wilco Vink 10

VEPROB (Vertex PROcessor Board)

Done:

-VHDL programming algorithm

-simulation VHDL

-schematic entry

Ongoing:

-Layout

10-09-2004

Wilco Vink 11

Output board

• 4 serial inputs from vertex processor boards

• Sole functionality: multiplex trigger data towards L0DU

• Xilinx FPGA with Rocket I/O

• 2 fibers optical output

• CCPC to configure, debug, monitor

• TTCrq

10-09-2004

Wilco Vink 12

VETO Latency      LHC Clocks

Hybrid   50ns 2

Cabling to optical station 6ns/m 108 ns

5

VETO Optical Station Synchronisation and demultiplexing   4

  GOL 64 ns max 3

Optical Ribbon 60m (4.5ns/m) 270 ns 11

Vertex processor board

Orx-card(tlk2501) 

4

  channel sync and vertex finder algoritm(xilinx FPGA) 1050ns

42

  MGT Rocket i/o transmitter + cable   4

Output board MGT Rocket i/o receiver   4

  Mux   1

  MGT Rocket i/o transmitter   3

Cable to L0DU 90ns 4

Total:     87