1 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer...

Fouts MAPLD 2005/C1171 of 23

Synthesis of False Target Radar ImagesUsing a Reconfigurable Computer

Dr. Douglas J. Fouts

LT Kendrick R. Macklin

Daniel P. Zulaica

Department of Electrical

and Computer Engineering

U.S. Naval Postgraduate School

Monterey, California

http://www.nps.navy.mil/NPS/LogoMeaning.htm


Outline

1. High resolution imaging inverse synthetic aperture radar (ISAR).

2. Digital synthesis of realistic false target images.

3. The SRC-6E reconfigurable computer.

4. Synthesis of false target images on the SRC-6E.

5. Testing results.

6. Conclusions

Synthesis of False Target Radar Images Using a Reconfigurable Computer



The USS Crockett, a typical target for a potential adversary.




Target appearance on the screen of atypical surface search and navigation radar.




Appearance of USS Crockett on U.S. Navy AN/APS-137

imaging Inverse Synthetic Aperture Radar (ISAR).





Block diagram of electronic warfare systemwith false target image synthesis capability.

Digital ImageSynthesisHardware



U.S. Navy Ship

Range Bins

Interrogating Radar Signal

Reflected Radar Signal


Dividing a target into range bins.



Block diagram of digital image synthesis hardware.





To synthesize a false target image, the math must be done very fast.



RTL diagram ofRange Bin Processor




The SRC-6E Reconfigurable Computer

• LINUX cluster of two PCs• Each PC has

– Two 1000 MHz Intel XEON® processors– Common memory– Snap port to Multi Adaptive Processor (MAP)

• Each MAP has– Two user-programmable Xilinx Virtex-II FPGAs (6 M gates each)– One Xilinx Virtex-II Control FPGA (not user programmable)– On-board memory– Snap port to PC– Two 96-bit wide chain ports to other MAP

• Programs written in C or Fortran.– User identifies which part(s) of program are converted to FPGA circuitry for

(hopefully) increased execution speed– FPGA code can also be written in VHDL OR Verilog– FPGA can also be programmed schematically or with IP cores




SRC-6E Architecture (half)

Intel® μP

L2

MIOC

PCI Common

Memory

SNAP

Controller

On-Board Memory (24 MB)

FPGA

Intel® μP

L2

μP Board

FPGA

6x 800 MB/s

6x 800 MB/s

MAP315/195

MB/s (peak)

Chain Port To/From

Other MAP

800 MB/s

Chain Port To/From

Other MAP

800 MB/s




MAP Software Development

• Code for FPGAs is isolated in external function• SRC compiler translates C source code into FPGA programming file.• MAP can also be programmed with Verilog, VHDL, IP cores, or schematically• FPGA circuitry deeply pipelined with 100 MHz clock (10 ns period)• Large pipeline fill time (large latency)• Calls are inserted in the main program to

– Initialize the MAP– Transfer input data from common memory to on-board memory– Call the external function– Transfer output data from on-board memory to common memory– Release the MAP (optional)




Programming Steps Used in This Research

• Describe range bin processor using VHDL in the Aldec Active-HDL 5.2 environment

– Code the individual logic blocks– Combine to build a single range bin processor– Instance the range bin processor the required number of times– Test code using Aldec Active-HDL simulator

• Create support and interface files for SRC-6E• Create “main” part of program in C for execution on PCs in SRC-6E• Compile and link




Benchmarks

1. VHDL macro on the SRC-6E MAP

2. C program on the SRC-6E– 1 GHz Xeon P3– 1.5 Gigabytes of RAM– Linux OS

3. C program on Pentium 4 system– 3 GHz P4– 2 Gigabytes of RAM– Windows XP Professional OS




FPGA Usage

y = 4.693e0.2978x

y = 1.9449x2 - 10.003x + 19.02

0.00

10.00

20.00

30.00

40.00

50.0060.00

70.00

80.00

90.00

100.00

1 2 4 8 16 32 64 128 256 512

Number of Bins

Us

ag

e (

%)

Usage Expon. (Usage) Poly. (Usage)




Average Total Time (4 Bins)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Number of Samples

Tim

e (

Se

co

nd

s)

SRC Macro MAP Call SRC Macro Total

Windows XP C Program SRC C Program





0123456789

10

Number of Samples

Tim

e (

Se

co

nd

s)







0

2

4

6

8

10

12

14

16

18

Number of Samples

Tim

e (

Se

co

nd

s)






SRC M AP Call Average Time

0.09

0.1

0.11

0.12

0.13

0.14

0.15

Number of Samples

Tim

e (

Se

co

nd

s)

Old 4 Bins 4 Bins 8 Bins 16 Bins 64 Bins 128 Bins




Average Percentage of Total Time (4 Bins)

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Number of Samples

Pe

rce

nta

ge

I/O Overhead MAP Overhead MAP Call




I/O Overhead Percentage of Total Time (Semi-Log)

0.01%

0.10%

1.00%

10.00%

100.00%

Number of Samples

Pe

rce

nta

ge

(L

og

)

4 Bins 8 Bins 16 Bins 64 Bins 128 Bins




Conclusions

1. The SRC-6E compiler allows C programmers to utilize the MAP without having to become circuit designers.

2. Porting code to the MAP requires basic knowledge of the hardware.3. Programming an SRC-6E requires less time and effort than developing

FPGA designs using COTS FPGA development systems.4. Overall performance of SRC-6E can be limited by transfer time

between common memory and on-board memory. 5. Use of large data sets amortizes MAP overhead and pipeline latency

across many calculations.6. Applications performing a large number of calculations on each data

set derive the largest performance boost from using the MAP.



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