ReSpace / MAPLD 2011 - Using FPGAs and a LEON3FT Processor ... - Habinc.pdf · ReSpace / MAPLD 2011...
Transcript of ReSpace / MAPLD 2011 - Using FPGAs and a LEON3FT Processor ... - Habinc.pdf · ReSpace / MAPLD 2011...
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G OUsing FPGAs and a LEON3FT Processor to Build a "Flying Laptop"
Sandi Habinc (1), Barry Cook (2), Paul Walker (2), Jens Eickhoff (3) Rouven Witt (4), Hans-Peter Röser (4)
(1) Aeroflex Gaisler, Kungsgatan 12, 411 19 Göteborg, [email protected]
(2) 4-Links Ltd. Suite EU2, Bletchley Park, Milton Keynes, MK3 6EB, [email protected], [email protected]
(3) Astrium GmbH - Satellites, 88039 Friedrichshafen, Germanyeickhoff@irs uni-stuttgart [email protected]
(4) Institute of Space Systems, Universität Stuttgart, Pfaffenwaldring 31, 70569 Stuttgart, Germany
[email protected], [email protected]
RESPACE/MAPLD 2011
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The Flying-Laptop (FLP) Satellite
Activity lead by Institute of Space Systems, University of Stuttgart (D)y , y g ( )3-axis stabilized LEO satelliteBox size of 60cm x 70cm x 80cmDeployable solar panelsMass of 120kgMass of 120kgAOCS including star trackers, wheels, GPSLaunch envisaged 2013 on ISRO PSLV launcherLaunch envisaged 2013 on ISRO PSLV launcherPayloads:− Panoramic camera− Panoramic camera,− Multispectral camera,− Laser link terminal
®4LinksUniversitätStuttgart
®4LinksUniversitätStuttgart
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The Flying-Laptop (FLP) Satellite
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®4LinksUniversitätStuttgart
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FLP Spacecraft Electrical Block Diagram
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®4LinksUniversitätStuttgart
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Flying-Laptop Onboard Computer
CCSDS Processor Boards Power Supply BoardsCCSDS Processor Boards Power Supply Boards
I/O Boards
On-Board Computer Boards
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®4LinksUniversitätStuttgart
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Onboard Computer Board
Eurocard size single board computer based on UT699 LEON3FT device, operating at 33 MHz, p g4 MB NV RAM, 8 MB SRAM4 SpaceWire interfaces (2x CCSDS board, 2x I/O Board)p ( , )1x UART (OBSW Service I/F)1x 44 Pin mixed connector with JTAG, Power Supply, etc., pp y,
Clearance for publication byClearance for publication byAeroflex Corp., Colorado Springs, USA
Information from DASIA 2011 presentation by Astrium®4LinksUniversit
ätStuttgart
®4LinksUniversitätStuttgart
Information from DASIA 2011 presentation by Astrium
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I/O Board
I/O boards form the bridge btw OBC and S/CI/O-boards mimic the digital interface function of a RIUI/O-boards mimic the digital interface function of a RIUThe I/O boards are connected to the OBC boards via a SpaceWire connection running the RMAP protocolSpaceWire connection running the RMAP protocol The I/O board are developed by 4Links Ltd., UK.Th I/O b d S Wi f ti lit d d t tiThe I/O boards SpaceWire functionality and data routing between SpW and the low level I/O and bus interfaces is implemented in a ProAsic3 FPGAimplemented in a ProAsic3 FPGA I/O board incorporates MRAM for S/C HK TM storage and for S/C state vector storage for reconfigurationsfor S/C state vector storage for reconfigurationsGeneric board design with I/Fs and SpW and central ProAsic3 FPGA and also used for CCSDS processor
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®4LinksUniversitätStuttgart
ProAsic3 FPGA and also used for CCSDS processor
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I/O Board block diagram
FPGA – Actel ProASIC 3eA3PE3000 (Industrial temperature version)
SpaceWireCODECs
Remote Memory Access Protocol (RMAP) TargetLVDS
UARTs Digital I/O Memory I/F
CODECs TargetLVDS Buffers
I2CIBIS
MRAM
/
RS422/485 Buffers
Digital line Buffers
O/C Buffers
RS422/485 Buffers
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®4LinksUniversitätStuttgart
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I/O Board PCB layout (Draft)
Information from DASIA 2011 presentation by Astrium®4LinksUniversit
ätStuttgart
®4LinksUniversitätStuttgart
Information from DASIA 2011 presentation by Astrium
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CCSDS Processor Board
FLP applies CCSDS/PUS standards for S/C command and controlTo implement this, the FLP is equipped with a CCSDS processor built on the same basic PCB design and ProAsic3 FPGA as the I/O BoardCCSDS board manufactured by 4Links Ltd.CCSDS IP cores designed by Aeroflex GaislerCCSDS IP cores designed by Aeroflex GaislerCCSDS processor breadboard from AeroflexGaislerGaisler
®4LinksUniversitätStuttgart
®4LinksUniversitätStuttgart
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CCSDS SpacePackets over SpaceWireAeroflex Gaisler has developed a method to transfer CCSDS Space Packets over SpaceWire links based on Remote Memory Access Protocol (RMAP).The Space Packet is transferred as part of the data field of the RMAP write command. The write access is done to memory areas in the target that are dedicated to different Packet Telemetry Virtual Channels Thedifferent Packet Telemetry Virtual Channels. The success of the transfer is acknowledged by an optional RMAP reply.RMAP reply.The Space Packet is protected by means of the RMAP data field CRC. Additionally, the RMAP command y,header (containing the addressing information, e.g. for Virtual Channel routing) is protected by means of CRC.
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®4LinksUniversitätStuttgart
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GRLIB IP core library
GRLIB is a complete design environment:– Processors– PeripheralsPeripherals– Serial interfaces– Parallel interfaces– Memory controllers– Memory controllers– AMBA on-chip bus with
Plug & Play supportFault tolerant & standard version– Fault tolerant & standard version
Support for tools & prototyping boardsPortability between technologies:Portability between technologies:
Actel, Aeroflex, Altera, Artisan, Atmel, DARE, eASIC/Nextreme, Eclipse Lattice Synopsys DesignWareEclipse, Lattice, Synopsys DesignWareRamon Chips / RadSafe, TSMC, UMC, Virage, Xilinx, etc.
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®4LinksUniversitätStuttgart
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GRTM Encoder & GRTC Decoder IP cores
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®4LinksUniversitätStuttgart
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CCSDS TC Decoder / TM Encoder FPGA
TelecommandCLTU
tseq
uenc
e se
arch
DMA
Data Link Protocol Sub-Layer
NR
Z-L
BCH
Dec
oder
Coding Sub-Layer
FIFOAMBAAHB
Master
udo
-Der
ando
miz
er
Physical Layer
AMBA
Sta
r t
AMBAAHBSlave
B
Pse
u
Rec
ept.
uxuxtion
Configuration
very
actio
n
actio
nData Link Protocol Sub-Layer
A
All
Fram
es R
MC
Dem
u
VC
Dem
u
VC
Rec
ept
HardwareCommands
TC UARTTelecommand Decoder
Descriptor AMBA
8k MemoryAHBSlave
Path
Rec
ov
Pack
et E
xtra
VC P
kt E
xtra
CLCWCross-coupling
DMA 2k FIFOAMBAAHB
MasterTelemetry Encoder
pMemoryAHBSlave
16k BufferMemoryAHBSlave
Configuration
AMBAAPBSlave
16k BufferCoding Sub-Layer
SpaceWire
AHBSlave
Ree
d-So
lom
onVCGenerate
Pseu
do R
ando
miz
er
Con
volu
tiona
l
Sync
Mar
ker
ual C
hann
el M
ultip
lexe
r
ter C
hann
el G
ener
atio
n
NR
Z-L
TelemetryCADU
Virtual Channel Frame Service
GRSPWRMAPAHB
M t
Fram
es G
ener
atio
nPhysical Layer
VC0
VC1AHBSlave
VCGenerate
AMBAAHB
Master
AMBAAHB
M t
16k BufferMemoryAHBSlave
P
Virtu
Mas
tMaster
All
VC2
VC3
Slave Generate
AHBSlave
VCGenerate
AHBSlave
VCGenerate
Master
AMBAAHB
Master
AMBAAHB
Master
SpaceWire GRSPWRMAPAHB
Master
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®4LinksUniversitätStuttgart
IdleFrame
VC7
TMTC FPGA
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CCSDS TM/TC breadboard
GR-MCC-C + GR-TMTC-ADAPTER + GR-CPCI-RS422
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®4LinksUniversitätStuttgart
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Conclusions
• The re-programmable ProASIC3 FPGA technology fits well in applications with low radiation requirements.
• The in-situ programmability enables the development of highly miniaturized systems which can be adapted to customers needs late in the development cycle.
• Porting a combined SpaceWire and CCSDS system to Flash-based FPGA technology went smoothly, with much of the IP core library work already donewith much of the IP core library work already done.
• Main processing power located in UT699 device, with peripheral functions such as I/O and CCSDSperipheral functions such as I/O and CCSDS processing implemented in custom designed FPGAs.
®4LinksUniversitätStuttgart
®4LinksUniversitätStuttgart
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Contact information
• Processor and IP core information:http://www.Aeroflex.com/Gaisler
• Board and component information:http://www 4Links comhttp://www.4Links.com
• Flying Laptop information:y g p phttp://www.kleinsatelliten.de/index.php/en/flying-laptop.html
®4LinksUniversitätStuttgart
®4LinksUniversitätStuttgart