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NTSC to VGA Converter

Marco Moreno

Adrian De La Rosa

EE382M-4 Adv Emb Arch

Project Goal

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TLL5000Spartan3 FPGA

RCA Video Cable

NTSC VideoSource

15-pin VGACable

Project Challenges

• YUV -> RGB color space conversion

• Input to display sync timing

• Interlaced video to progressive scan

Project Hardware

• TLL5000 – base development module– Analog Devices: ADV7180 - NTSC decoder– Analog Devices: ADV7125 - VGA DAC– Xilinx: Spartan III - FPGA

• TLL6219 – MX21 daughter board

• Digital camera NTSC source + A/V cable

• LCD monitor + 15-pin VGA cable

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ADV7180 NTSC Decoder

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• Analog Input– Composite– Component– Svideo

• Digital Outputs– LLC 27MHz clock– HS, VS/Field– 8-bit Output Port P

ADV7180 Block Diagram

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ADV7125 Video DAC

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Converts 8-bit values on RGBports to analog levels for display

Color-Space Conversion

• YUV Data Format

• RGB Data Format

• Color-space conversion

• Conversion quality / speed

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YUV Data Format

• Compatible with black & white TV infrastructure

• U & V color difference signals.• Single Image format

• Video format

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YUV Analyzer

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Sunray Image – YUV Tools http://www.sunrayimage.com/

Analysis data used for conversion quality reference

RGB Data Format

• Additive color model• R, G and B are color contributions rather than

color differences• Single Image Format

• Video Format– Three channels for color, 8-bit values– VGA connector – separate lines for vertical and horizontal

synchronization signals.

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Color-space conversion

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• Multiple sources for information

• Multiple recommendations for values used in calculation

• Ultimately chose a mix to give values closed to reference YUV tool analyzerR = 1.164*((int)Y - 16) + 1.596*((int)V - 128);

G = 1.164*((int)Y - 16) - 0.714*((int)V - 128) - 0.344*((int)U-128);B = 1.164*((int)Y - 16) + 2.018*((int)U - 128);

Conversion C++ code

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//memory allocationint *yuv = (volatile unsigned int *)malloc(YUVBLOCK);

//Open the file for reading in binary formatint fd = open("flower_droplet.uyvy", O_RDWR);

//write file to yuv memory blockread(fd, yuv, YUVBLOCK);close(fd);

//open file for writingfd = open ("converted.bmp", O_CREAT|O_RDWR);printf("fd %d\n", fd);

// write headerwrite(fd,&header[0],4);...write(fd,&header[13],2);

//Calculate values and store to arrayR = 1.164*((int)Y - 16) + 1.596*((int)V - 128);G = 1.164*((int)Y - 16) - 0.714*((int)V - 128) - 0.344*((int)U-128);B = 1.164*((int)Y - 16) + 2.018*((int)U - 128);

//Write entire array to memory at oncewrite(fd,&BLOCK[0],YUVBLOCK);printf("\n\n");close(fd);

• Allocate memory• Open file and write to mem• Create new file• Write header for new file• Calculate all pixel RGB

data• Write out to new file• Rev 1.0 :~4hr• Rev 2.0 : ~4sec

Conversion Verilog code• Implemented with shifts and adds only• Asynchronous logic block• Bitwise operations

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// CALCULATE Y COMPONENT OF R, G AND Bassign ycomp = ((y & 8'hf0) == 8'h00) ? (8'h00 - y_16 - {3'b0, y_16[7:3]}) : ((y_16) + {3'b0, y_16[7:3]} + {5'b0, y_16[7:5]} + {7'b0, y_16[7]});// CALCULATE V COMPONENT OF Rassign r_vcomp = ((v & 8'h80) == 8'h00) ? (9'd0 - v_128 - {3'b0, v_128[7:3]} - {4'b0, v_128[7:4]}) : (v_128 + {3'b0, v_128[7:3]} + {4'b0, v_128[7:4]});// CALCULATE V COMPONENT OF Gassign g_vcomp = ((v & 8'h80) == 8'h00) ? (9'b0 - {1'b0, v_128[7:1]} - {3'b0, v_128[7:3]} - {4'b0, v_128[7:4]} - {5'b0, v_128[7:5]}) : ({1'b0, v_128[7:1]} + {3'b0, v_128[7:3]} + {4'b0, v_128[7:4]} + {5'b0, v_128[7:5]});// CALCULATE U COMPONENT OF Gassign g_ucomp = ((u & 8'h80) == 8'h00) ? (9'b0 - {2'b0, u_128[7:2]} - {4'b0, u_128[7:4]} - {5'b0, u_128[7:5]} - {6'b0, u_128[7:6]}) : ({2'b0, u_128[7:2]} + {4'b0, u_128[7:4]} + {5'b0, u_128[7:5]} + {6'b0, u_128[7:6]});// CALCULATE U COMPONENT OF Bassign b_ucomp = ((u & 8'h80) == 8'h00) ? (9'b0 - {u_128, 1'b0} - {6'b0, u_128[7:6]}) : ({u_128, 1'b0} + {6'b0, u_128[7:6]});

// ADD COMPONENTS TO CALCULATE R, G AND Bassign r_wire = ycomp + r_vcomp;assign g_wire = ycomp - g_vcomp - g_ucomp;assign b_wire = ycomp + b_ucomp;

// CHECK FOR R, G OR B LESS THAN ZEROassign r_zero = (r_wire[8] && 1) ? (9'h00) : (r_wire);assign g_zero = (g_wire[8] && 1) ? (9'h00) : (g_wire);assign b_zero = (b_wire[8] && 1) ? (9'h00) : (b_wire);

// CHECK FOR R, G, OR B GREATER THAN 255 AND SET FINAL VALUEassign r = (r_zero[8:7] > 255) ? (8'hff) : (r_zero[7:0]);assign g = (g_zero[8:7] > 255) ? (8'hff) : (g_zero[7:0]);assign b = (b_zero[8:7] > 255) ? (8'hff) : (b_zero[7:0]);

Y-component = (y - 16) * 1.0010101;Y-component = (y - 16) + (Y - 16 ) >> 3 + (y - 16) >> 5 + (Y - 16) >> 7;

V-component of R = (V - 128) * 1.0011;V-component of R = (V - 128) + (V - 128) >> 3 + (V - 128) >> 4;

V-component of G = (V - 128) * .10111V-component of G = (V - 128) * (V - 128) >> 1 + (V - 128) >> 3 + (V - 128) >> 4 + (V - 128) >> 5;

U-component of G = (U - 128) * .010111;U-component of G = (U - 128) >> 2 + (U - 128) >> 4 + (U - 128) >> 5 + (U - 128) >> 6;

U-component of B = (U - 128) * 10.000001;U-component of B = (U - 128) << 1 + (U - 128) >> 6;

Conversion quality / speed

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Pixels Y V Y U  0x4b 0x7c 0x4b 0x67  75 124 75 103           R G B  Ref. 62 82 18  C++ 62 80 18  Verilog 63 76 17  

Unoptimized C++ codeRev 1.0 : ~ 4hrRev 2.0 : ~4sec

FPGA operating @ ~27Mhz pixel clockFrame rate 60 HzOne frame - ~16 msec

Video Synchronization

• NTSC to VGA timing generation

• Interlaced video to progressive scan

• Solution architecture

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VGA Sync Signals

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VGA Sync Timing (Typical)

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VGA modeResolution (HxV)

Pixel clock(Mhz)

VGA(60Hz) 640x480 25 (640/c)

VGA(85Hz) 640x480 36 (640/c)

SVGA(60Hz) 800x600 40 (800/c)

SVGA(75Hz) 800x600 49 (800/c)

SVGA(85Hz) 800x600 56 (800/c)

XGA(60Hz) 1024x768 65 (1024/c)

XGA(70Hz) 1024x768 75 (1024/c)

XGA(85Hz) 1024x768 95 (1024/c)

1280x1024(60Hz) 1280x1024 108 (1280/c)

a(lines) b(lines) c(lines) d(lines)

2 33 480 10

3 25 480 1

4 23 600 1

3 21 600 1

3 27 600 1

6 29 768 3

6 29 768 3

3 36 768 1

3 38 1024 1

a(ms) b(us) c(us) d(us)

3.8 1.9 25.4 0.6

1.6 2.2 17.8 1.6

3.2 2.2 20 1

1.6 3.2 16.2 0.3

1.1 2.7 14.2 0.6

2.1 2.5 15.8 0.4

1.8 1.9 13.7 0.3

1.0 2.2 10.8 0.5

1.0 2.3 11.9 0.4

Horizontal Regions Vertical Regions

VGA Progressive Video

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Line 1

Line 2Line 3

Line 4

…

Line 522

Line 523Line 524

Line 525

NTSC Interlaced Video

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Field 1 / Field 2 scanning

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Field 1 start(even lines)

Field 2 start(odd lines)

HS (

from

NTSC

deco

der)

Genera

ted V

GA

HS

YN

C

VS/F

ield

(fr

om

NTS

C d

eco

der)

Genera

ted V

GA

VS

YN

C

De-Interlacing

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Video Stream Architecture

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ADV7180NTSC Decoder

RCA InputVGA VSYNCGenerator

LLC - 27MHz pixel clock

VGA HSYNC

VGA VSYNC

De-Interlace /Pixel Reformat

ADV7125Video DAC

Color SpaceConverter

VGA Analog Color Channels

4:2:2

4:4:4

De-Interlace Line Buffers

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WE

ADDR[9:0]

DIN[15:0]

WR_BUF_SEL

DOUT[15:0]

WE

ADDR[9:0]

DIN[15:0]

WR_BUF_SEL

DOUT[15:0]

YUV 4:2:28-bits per clk

RD_BUF_SEL

YUV 4:4:416-bits per clk

WR_BUF_SEL ? WR_PTR : RD_PTR

RD_BUF_SEL ? WR_PTR : RD_PTR

0

1

2 x RAMB16_S18

ADV7180 I2C Interface

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FPGA I2C Controller

ADV7180NTSC Decoder

Registers

-Input Select-H/V SYNC shape-Video Format-Interrupt Control

iMX.210xCC000000-0xCC000100

SCLK

SDA

Registers

– Serial protocol for interconnecting IC’s– I2C block registers memory mapped to CPU– Linux mmap application command line interface– Controls various timing and format options

Wishbone

Lessons Learned

• Keep Verilog code simple

• Edge triggers are extremely useful

• Tie one-off possibilities to switches

• Not all TLL5000 boards have same clocks

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Potential future work

• Complete optimization of C++ code• Implement video stream with ARM

controller rather than full-fpga implementation

• FPGA vs. ARM performance analysis• FPGA vs. ARM power analysis• Fix horizontal positioning error• Smooth de-interlace w/ interpolation• DMA image data to iMX.21 SDRAM

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Backup

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Hsync generation

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Vsync generation

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Field 1 / 2 & data transmission

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Direct Y-data NTSC to VGA

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RGB channel separation

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Buffered, CSC, Partially Aligned

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