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MOS Field-EffectTransistors (MOSFETs)

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Microelectronic Circuits - Fifth Edition Sedra/Smith 2Copyright 2004 by Oxford University Press, Inc.

Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.


Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.


Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity).


Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.


Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.


Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.


Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape.


Figure 4.8 Derivation of the iD–vDS characteristic of the NMOS transistor.


Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.


Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant.


Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.


iD-vDS Characteristics (nMOS enhancement)

2

2

1)( DSDStGSoxnD vvVv

L

WCi

Triode region: vDS vGS-Vt

Saturation region: vDS >vGS-Vt

2)(2

1tGSoxnD Vv

L

WCi

K´n=nCox is the process transconductance parameter


Figure 4.12 The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, k’n W/L = 1.0 mA/V2).


Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.


Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in the saturation region.


Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL).


Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.


iD-vDS Characteristics (nMOS enhancement) with output resistance ro

Saturation region: vDS >vGS-Vt

)1()(2

1 2´DStGSnD vVv

L

Wki

Having = ´/L=1/VA as a process technology parameter (Early voltage)

ro= VA/ID (output resistance)


Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22).


Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal.


Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region and in the saturation region.


Figure E4.8


Table 4.1


Figure 4.20 Circuit for Example 4.2.

Projecte o circuito da figura para que otransistor funcione com ID=0,4mA e VD=0,5V. O NMOS apresenta Vt=0,7V, nCox=100A/V2, L=1 m e W=32 m. Despreze o efeito de modulação da largura de canal.

Resposta: RS=3,25 k e RD=5 k



Projecte o circuito da figura para que o transistor funcione com ID=80A. Qual o valor de R e de VD? O NMOS apresenta Vt=0,6V, nCox=200A/V2, L=0,8 m e W=4 m. Despreze o efeito de modulação da largura de canal.

Resposta: R=25 k e VD=1V


Figure E4.12



Resposta: rDS=253 e RD=12,4 k

Projecte o circuito da figura de modo a obter-se uma tensão de dreno VD =0,1V. Qual a resistência efectiva entre o dreno e a source do transistor para este PFR? O transistor NMOS apresenta os seguintes parâmetros: Vt=1V, k´n(W/L)=1mA/V2. Despreze o efeito de modulação da largura de canal.


Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.

Analise o circuito da figura e determine as tensões em todos os nós do circuito. Faça Vt=1V, k´n(W/L)=1mA/V2 e despreze o efeito de modulação da largura de canal (0).

ID=0,5 mA ; VG=5V ; VS=3V ; VD=7 V



Projecte o circuito de modo ao transistor estar saturado com ID=0,5 mA e VD=3 V. Considere os seguintes parâmetros para o PMOS: Vt=-1V, k´p(W/L)=1mA/V2 e =0.

Qual o maior valor para RD que ainda mantém o transistor saturado?

RD=6k e RD<8k


Figure 4.25 Circuits for Example 4.7.


Figure E4.16


Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of the amplifier in (a).


Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.

vI= VIQ+vi

vO= VOQ+vo


Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the triode region and might not allow for sufficient negative signal swing.


Figure 4.28 Example 4.8.


Figure 4.28 (Continued)


Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2 represent extremes among units of the same type.


Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical implementation using two supplies.


Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.


Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I using a current mirror.


Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.


Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

2)(2

1tGSoxnD Vv

L

WCi

GSGS VvGS

Dm v

ig

)(´ tGSnm VV

L

Wkg

D

Ao I

Vr


Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.


Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34.


Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (the channel-length modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID.


Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.


Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can be added between D and S in the T model of (d).


Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative representation of the T model.


Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body.


Table 4.2


Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations.


Figure E4.30


Table 4.3


Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model implicitly utilized.


Figure 4.44 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equivalent circuit with ro neglected.


Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the amplifier in (a). (c) The common-gate amplifier fed with a current-signal input.


Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. (c) Small-signal analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of the source follower.


Problema de 13-4-2005Relativamente aos quatro circuitos apresentados na tabela 4.4, determine os seguintes parâmetros: Rin, Rout, Av, Gv e GI.

Admita que para o PFR do transistor, este apresenta os seguintes parâmetros: gm=1mA/V e ro=150k.


Table 4.4


Table 4.4 (Continued)


Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in which the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with Cdb neglected (to simplify analysis).


Figure 4.48 Determining the short-circuit current gain Io /Ii.


Figure 4.48 Determining the short-circuit current gain Io /Ii.

gsgdgsmo VsCVgI ..

gsgdgs

i VCCs

I )(

1.

)( gsgd

m

i

o

CCs

g

I

I

gsgd

mTT CC

gf

2

Frequência de ganho unitário


Table 4.5


Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier in (a) delineating the three frequency bands of interest.


Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at the input and the output;

gsLmo VRgV ..


Figure 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq; (d) the frequency response plot, which is that of a low-pass single-time-constant circuit.

0

1

1)(

s

VRR

R

V

Vsig

sigG

G

sig

o


Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected.


Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected.

))()(()()(321 PPP

LGmsigG

G

i

o

s

s

s

s

s

sRRg

RR

R

V

V

)(

1

23

LDCP RRC

)(

1

11

sigGCP RRC

12

C

mP C

g


Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are sufficiently separated for their effects to appear distinct.


Figure 4.53 The CMOS inverter.


Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; (c) equivalent circuit.


Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit.


Figure 4.56 The voltage transfer characteristic of the CMOS inverter.


Triode region: vo vI-Vtn

2

2

1)( ootnI

nnDN vvVv

L

Wki

2)(2

1tnI

nnDN Vv

L

Wki

Saturation region: vo >vI-Vtn

2)(

2

1))(( oDDoDDtpIDD

ppDP vVvVVvV

L

Wki

Triode region: vI+|Vtp | vo

Saturation region: vo <vI+|Vtp |2)(

2

1tpIDD

ppDP VvV

L

Wki


Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the capacitor discharge.


Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter (cont.)

dt

dvCi C

FMpHLFEpHLpHL ttt )()(


Figure 4.58 The current in the CMOS inverter versus the input voltage.

2.. DDD VCfP

PD tPPD ..


Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the case the substrate (B) is connected to the source (S).


Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = –4 V and kn(W/L)

= 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iD–vDS characteristics; (c) the iD–vGS characteristic in saturation.


Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the saturation regions. The case shown is for operation in the enhancement mode (vGS is positive).


Figure 4.62 Sketches of the iD–vGS characteristics for MOSFETs of enhancement and depletion types, of both polarities (operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also note that for generality somewhat different values of |Vt| are shown for n-channel and p-channel devices.


Figure E4.51


Figure E4.52


Figure 4.63 Capture schematic of the CS amplifier in Example 4.14.


Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with CS = 10 F and CS = 0 (i.e., CS removed).


Figure P4.18


Figure P4.33


Figure P4.36


Figure P4.37


Figure P4.38


Figure P4.41


Figure P4.42


Figure P4.43


Figure P4.44


Figure P4.45


Figure P4.46


Figure P4.47


Figure P4.48


Figure P4.54


Figure P4.61


Figure P4.66


Figure P4.74


Figure P4.75


Figure P4.77


Figure P4.86


Figure P4.87


Figure P4.88


Figure P4.97


Figure P4.99


Figure P4.101


Figure P4.104


Figure P4.117


Figure P4.120


Figure P4.121


Figure P4.123

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