1 Interconnection Networks and Scalable Crossbars Prof. U. Brüning Computer Architecture Group...
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Transcript of 1 Interconnection Networks and Scalable Crossbars Prof. U. Brüning Computer Architecture Group...
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Interconnection NetworksInterconnection Networksandand
Scalable Crossbars Scalable Crossbars
Prof. U. BrüningComputer Architecture Group
Institute of Computer EngineeringUniversity of Mannheim
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OverviewOverview
• Future_DAQ workpackages– Embedded optical transceiver cell
– Cascadable 32x32 crossbar switch
• Interconnection Networks• First Results
– OASE
– SWORDFISH
– Scalable Crossbar
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ATOLL Chip:ATOLL Chip:
„Network on a Chip“die size 5.7 x 5.7 mm
4.5 Mio. TransistorsUMC 0.18µm CMOS
6 clock domains 250MHz main areas133MHz PCI-X
64bit architecture
ATOLL
ATOmic Low Latency
R
ATOLLATOLL
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OASEOASEOASER
Optical Advanced SErializer
OASE Chip:OASE Chip:SERDES and Optical Transceiver on a Chip
die size 2.4 x 5.0 mm
UMC 0.18µm CMOS
2,5GHz bidirectional data rate
125MHz parallel interface with DDR LVDS
VCSEL with direct flip chip mounting
8B/10B Encoder
OASE
to VCSELserializer
deserializerclock & datarecovery
laserdriver
transimped. amplifier
limitingamplifier
CMLinput
interfaceparallel
equalization
to optical Transceiver
from PIN Diode
from optical Transceiver
CMLoutput
fromPIN Diode withTransimp. Amp.
8B/10B Decoderinterface
parallel
input
output
pre-
control &debuginterface
control &
registersstatus transmitter
receiver
control
onchip
with PhDet
laserdriver
to VCSELoff chip
PhDet input
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OASEOASEOASER
Optical Advanced SErializer
OASE Optical Attachment:OASE Optical Attachment:
VCSEL with direct flip chip mounting
Bottom emitter VCSEL Fiber mounting with self-alignment structure
SU-8 on glass
Alignment of GaAs wafer to glass substrate at wafer level
Very low cost
VCSEL
45o cuboid bracket
f iber
GaAs
Au mirror
opt ics
bumpsbottom emi tter
glass substrate
posit ioning in X dimension
positioning in
SiliconSubstrate OASE chip
Z dimension
contact pads
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SWORDFISHSWORDFISH
IN Simulator:IN Simulator:
Very flexible
parametrizableWormhole and packet routingTopology generatorMPI like traffic pattern generationPlug ins for routing, arbitrationExecution driven simulation for large INs
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Scalable CrossbarScalable Crossbar
Parameter:Parameter:
Number of Ports
Data width
debug port
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Scalable CrossbarScalable Crossbar
Functional ViewFunctional View
Structured in: Inport
Outport
debug port
interconnect matrix
FIFOs for
reverse flow control
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Scalable CrossbarScalable Crossbar
InPortInPort
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Scalable CrossbarScalable Crossbar
OutPortOutPort
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Scalable CrossbarScalable Crossbar
Crossbar GenerationCrossbar Generation
PERL script
Generates the RTL description of a NxN Crossbar Number of Ports, word width, FIFO depth, cycle time, …
Verilog source code
constraint file
synthesis control file
reports
test bench generation with assertions
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Scalable CrossbarScalable Crossbar
Timing ResultsTiming Results
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Scalable CrossbarScalable Crossbar
Area for Standard CellsArea for Standard Cells
• 32 x 32 Crossbar feasible but with cycle time below 200MHz
• Take care of pin limitation
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ResultsResults
• OASE• TX tested and only one small modification in the high speed analog
part required
• Input Jitter of 100ps at LVDS clock can be accepted due to PLL filtering
• RX could not be tested completely due to analog simulation fault (VCO in CDR to slow)
• Network Simulator • fully functional
• Swordfish: C++ modular simulator with plug ins
• Scalable Crossbar • Automatic generation of parametrized Crossbar• Verified by simulation (hardware structure from ATOLL)
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Thank you for your kind attention!Thank you for your kind attention!
Questions?Questions?
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Present WorkPresent Work
• Prototype Testbed– Based on Virtex4 V60
– Test of MGTs and OASE
– Jitter measurements
– Nearest neighbor interconnect test
– Test of fast host interfaces (HTX)