1 ECE 2372 Modern Digital System Design Section 7.1 Introduction to Hardware Descriptive Language.

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ECE 2372Modern Digital System Design

Section 7.1

Introduction to

Hardware Descriptive Language

Introduction to HDL

• A Hardware Descriptive Language (HDL) allows the digital designer to describe the behavior of a circuit using a high-level computer language.

• The description may take the form of an algorithm, logic equations or truth table.

• This high-level description of the digital system may be compiled into a file that is used to program a Programmable Logic Device, or may be processed by a Silicon Compiler to produce the masks used to create integrated circuits.

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Introduction to HDL

• One HDL is Verilog.• Xilinx features a Verilog editor, synthesizer

and simulator.

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HDL Design Process

Compile

Test and Simulation

PLD Program

Programmable Logic Device

HDL Description

Silicon Synthesizer

Integrated Circuit Masks

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Verilog File Structure

• The basic unit of Verilog Code is called a Module.• A Verilog module has the following format.

module modulename(port list); parameters port declarations wire declarations reg declarations submodule instantiations ..text body.. endmodule 5


• The keywords are module and endmodule.• The modulename identifies the module and may

include any letters, numbers the $ sign and the _ underscore.

• Verilog identifiers are case sensitive..• The modulename is followed by a list of input and

output ports.

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• Parameters are used to define numerical constants.

• These constants are often used to make designs more general and flexible.

• The numerical constants may be decimal, hexadecimal, octal or binary. Numbers are 32 bit unless otherwise specified.

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• Some valid numerical constants are:

parameter n = 391 //32 bit decimal number.

parameter a = 32’h4FF3_2CDA //32 bit hexadecimal number. //The underscore does not //modify the value of the //number and is included to //improve readability.

parameter c = 2’b01 //2 bit binary number.

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• The port declarations are used to describe the input and output ports.

• The input ports are declared with the keywords:

input A; //Single bit input port input [3:0] B; //4-bit input bus

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• Bits are individually referenced by B[3], B[2], B[1] and B[0].

• The most significant bit is listed first.

MyModule A

B[0]

B[1]

B[2]

B[3]

MyModule A

B[3:0]

or

4

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• The port declarations are used to describe the input and output ports.

• The output ports are declared with the keywords:

output C; //Single bit output port bus output [7:0] D; //8-bit output bus inout DATA_IN_OUT; //Single-bit input/output port

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MyModule C

D[0]

D[1]

D[2]

D[3]

MyModule C

D[7:0]

or

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D[4]

D[5]

D[6]

D[7]

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Verilog File Structure • The wire declarations define the connections

between logic gates and sub-modules within a module.

• These correspond to physical conductors in a logic circuit.

• A wire variable type has no memory and cannot be used to store a value.

• A wire must be connected to the output of a gate or must be assigned a value.

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Verilog File Structure A

P1

P2 = 0

B

C

wire P1; //Single wire connection wire P2; //Single wire connection assign P2 = 0;

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Data_Bus[7:0]

8

8

8

A[7:0] B[7:0] S0

S1

wire [7:0] Data_Bus; //8-bit data bus connection

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• The reg declarations are used to define registers.

• These are variables that have memory and may be used to store a value.

• These are in effect variables that retain logical values during a Verilog process.

• A register may also be assigned to output ports.

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reg Q1; //Single-bit register. reg [3:0] Q; //4-bit register

A

Q[0]

Process

Register

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B Q[3:0]

Q[1]

Q[2]

Q[3]

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• The submodule instantiations are where logic gates and other Verilog modules may be incorporated into a module.

Sub_Module_A[1]

My_Module

Sub_Module_A [2]

Sub_Module_A [3]

Sub_Module_B

Inputs Outputs

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• The description of the Verilog module follows.• A Module may be defined with Structural

Descriptions or Behavioral Descriptions. • The module is closed with the endmodule

keyword. • The structure of a Verilog file is demonstrated in

the following example of a full adder.• The purpose of each line keyword and operator is

explained in the comments.

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Verilog File Structure a

b sum c_in

c_out

sum = a b c_in c_out = ab + a c_in + b c_in

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Verilog File Structure module FullAdder(a, b, c_in, sum, c_out); input a; input b; input c_in; output sum; output c_out; assign sum = a ^ b ^ c_in; assign c_out = a & b | a & c_in | b & c_in; endmodule

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• This is a Data Flow Description of a full adder that uses the assign keyword to make a continuous assignment to the output ports.

• These assignments may use the logical operators.• Operators (in order of precedence)

~ NOT

& AND

| OR

^ XOR

^~ XNOR

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p = a b sum = p c_in g = ab p_c = p c_in c_out = p_c + g

a b

sum c_in

c_out

p g

p_c

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module FullAdder(a, b, c_in, sum, c_out); input a, b, c_in; output sum, c_out; wire p, g, p_c; xor Gxor1(p, a, b), Gxor2(sum, p, c_in); and Gand1(g, a, b), Gand2(p_c, p, c_in); or Gor1(c_out, g, p_c); endmodule

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• The wire keyword is used to define three intermediate terms used in the module.

• Each of the gates is defined individually.• The gate definitions are of the form

gate_type gate_name1(output, inputs), gate_name2(output,

inputs);

• The Gate Type may be any of the standard logic gates.

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• Gate Definitions:

and gate_name(output, inputs)

nand gate_name(output, inputs)

or gate_name(output, inputs)

nor gate_name(output, inputs)

xor gate_name(output, inputs)

xnor gate_name(output, inputs)

not gate_name(output, input)

buf gate_name(output, input)

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• This for is a Verilog Structural Description.• The gate_name may be any valid Verilog name.• Gate names should be chosen to be descriptive and

to distinguish the gates.• The gates are assumed to be single output, with

any integer number of inputs greater than one. • The same full adder may be described with a

Functional Description that implements the mathematical operation as follows.

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Verilog File Structure module FullAdder(a, b, c_in, sum, c_out); input a; input b; input c_in; output sum; output c_out; assign {c_out, sum} = a + b + c_in; endmodule

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• The brackets {} indicate a concatenation of the two single bit variables.

• The expression uses the Binary Arithmetic Addition operator, not the Boolean Or operator. .

• A module may be called from within a module.• Consider the 4-bit ripple adder made up of 4 full

adders as follows:

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• The full adder can be designed once, and then called (as if it were a sub-routine) 4 times in creating a 4-bit adder.

FA FA FA FA

A[3] A[2] A[1] A[0]

B[3] B[2] B[1] B[0]

S[3] S[2] S[1] S[0]

C0

C4 C[3] C[2] C[1]

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Verilog File Structure module FullAdder(a, b, c_in, sum, c_out); input a; input b; input c_in; output sum; output c_out; assign sum = a ^ b ^ c_in; assign c_out = a & b | a & c_in | b & c_in; endmodule

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Verilog File Structure module 4_Bit_Adder (A, B, C0, S, C4); input [3:0] A; input [3:0] B; input C0; output [3:0] S; output C4; wire [3:1] C; FullAdder Bit0(A[0], B[0], C0, S[0], C[1]), Bit1(A[1], B[1], C[1], S[1], C[2]), Bit2(A[2], B[2], C[2], S[2], C[3]), Bit3(A[3], B[3], C[3], S[3], C4); endmodule

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module TwoBitAdder(a1,a0,b1,b0,c0,s1,s0,c2); input a0,a1,b0,b1,c0; output s0,s1,c2; wire c1; FullAdder Bit1(a0,b0,c0,s0,c1); FullAdder Bit2(a1,b1,c1,s1,c2); endmodule module FullAdder(a,b,c_in,s,c_out); input a,b,c_in; output s,c_out; assign s = a ^ b ^ c_in; assign c_out = a & b | a & c_in | b & c_in; endmodule


• The sub-module FullAdder is invoked in 4 instantiations.

• A unique name is given to each of the instantiations.

• The same 4-bit adder may be described using the functional description:

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Verilog File Structure module 4_Bit_Adder(A, B, C0, S, C4); input [3:0] A; input [3:0] B; input C0; output [3:0] S; output C4; assign {C4, S} = A + B + C0; endmodule

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Conditional Operator • The conditional operator ( ? : ) evaluates an

expression and returns a value if the expression is true.

• The conditional operator is used in assign statements as follows:

assign Var_1 = (Condition) ? Value :Continue;

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Conditional Operator • The conditional operator is demonstrated in the

following example (x assigns an “unknown”):

module Multiplexer_4_to_1(S, D, Y); input [1:0] S; input [3,0] D; output Y; assign Y = (S == 0) ? D[0] : (S == 1) ? D[1] : (S == 2) ? D[2] : (S == 3) ? D[3] : 0; endmodule

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Conditional Operator • Conditional operations may be nested as

demonstrated in the following example:

module Multiplexer_4_to_1(S, D, Y); input [1:0] S; input [3,0] D; output Y; assign Y = S[1] ? (S[0] ? D[3] : D[2]) :

(S[0] ? D[1] : D[0]); endmodule

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Sequential Logic Circuits • Sequential logical circuits are described using

Procedural Descriptions. • The two types of processes are initial and always.• The initial process is executed once when the

module is executed.• The always process is executed continuously

when the module executed.• The process defined by the statements between the

begin and end keywords.

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Sequential Logic Circuits • An initial process is illustrated by the following

code fragment.

initial begin process statements; end

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Sequential Logic Circuits • An always process is illustrated by the following

code fragment.

always @ (event-expression1 or event-expression2) begin process statements; end

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Sequential Logic Circuits • The always procedure must be triggered by an

event.• This event may be a change in the value of a

variable as illustrated in the code fragment below.

always @ (a or b or c ) begin f = a & b & c; end

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Sequential Logic Circuits • This type of event-expression is typically used to

synthesize asynchronous sequential circuits.

always @ (a or b or c ) begin f = a & b & c; end

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Sequential Logic Circuits • Synchronous sequential circuits are typically

triggered by the rising or falling edges of signals.• This is illustrated in the code fragment below.

always @ (posedge CLK or posedge RESET) begin process statements; end

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Conditional Statements • A conditional procedure may be written using if-

else statements as follows

if (condition) ... statements_1...; else ... statements_2...;

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Conditional Statements • Multiple conditions may be included with the

form:

if (condition_1) ... statements_1...; else if (condition_2) ... statements_2...; else ... statements_3...;

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Conditional Statements • An alternative conditional process may be written

using case statements.

case (variable_name) case_item1 : ...statements_1...; case_item2 : ...statements_2...; : ...defalt_statements...; endcase

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Conditional Statements • Case statements may be combined with if-else

statements:

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case expression case_item1 : if (condition) ... statements_1...; else ... statements_2...; case_item2 : if (condition) ... statements_3...; else ... statements_4...; : if (condition) ... statements_5...; else ... statements_6...; endcase 49

Conditional Statements • A procedure may be initiated by a clock or an

asynchronous preload condition. always @ ( posedge CLOCK or negedge reset ) begin if !reset begin ... statements ... end else begin ... statements ... end end

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Blocking Assignments • Consider the fragment of Verilog code listed

below. Assuming that the variables A, B and C have some initial value.

reg A, B, C; begin B = A; C = B; end

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Blocking Assignments • A the end of the end of the process, both B and C

have the value originally assigned to A.• The assignments have been made sequentially.

reg A, B, C; begin B = A; C = B; end

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Non-blocking Assignments • Consider the fragment of Verilog code listed

below. Assuming that the variables A, B and C have some initial value.

reg A, B, C; begin B <= A; C <= B; end

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Non-blocking Assignments • At the end of the end of the process, B has the

value originally assigned to A. The variable C has the value originally assigned to B.

• The assignments have been made concurrently. reg A, B, C; begin B <= A; C <= B; end 54

JK Flip Flop • Additional keywords and operators are

demonstrated in the following Verilog file. This module implements a JK Flip Flop.

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module JKFlipFlop(J, K, CLK, Q, QNOT); input J, K, CLK; output Q, QNOT; reg Q_reg; assign Q = Q_reg; assign QNOT = !Q_reg; always @(negedge CLK) begin if (!J & !K) Q_reg <= Q_reg; if ( J & !K) Q_reg <= 1; if (!J & K) Q_reg <= 0; if ( J & K) Q_reg <= !Q_reg; end endmodule

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Operators • In order of precedence:

! NOT & AND | OR, ^ EXCLUSIVE OR

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Sequence Recognizer for 1101 • State Transition Table:

Input x Present State 0 1

00 00/0 01/0 01 00/0 10/0 10 11/0 10/0 11 00/0 10/1

Next State/Output

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module Seq_Rec(CLK, RESET, X, Y1, Y0, Z); input CLK, RESET, X; output Y1, Y0, Z; reg [1:0] state, next_state; parameter A = 0; parameter B = 1; parameter C = 2; parameter D = 3; reg Z_reg;

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assign Z = Z_reg; assign Y1 = state[1]; assign Y0 = state[0]; always @(posedge CLK or posedge RESET) begin if (RESET == 1) state <= A; else state <= next_state; end

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always @(X or state) begin case (state) A: if (X) next_state <= B; else next_state <= A; B: if (X) next_state <= C; else next_state <= A; C: if (X) next_state <= C; else next_state <= D; D: if (X) next_state <= B; else next_state <= A; endcase end

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always @(X or state) begin case (state) A: Z_reg <= 0; B: Z_reg <= 0; C: Z_reg <= 0; D: Z_reg <= X ? 1: 0; endcase end endmodule

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module StateMachine( input clk, input a, output z, output y1, output y0, output clk_out ); reg [23:0] slowclk; reg [1:0] state, next_state; assign clk_out = slowclk[23]; parameter A = 0; parameter B = 1; parameter C = 2; parameter D = 3; reg z1; assign z = z1; assign y1 = state[1]; assign y0 = state[0]; always @ (posedge clk) begin slowclk <= slowclk + 1; end always @(posedge slowclk[23]) begin state <= next_state; end

always @(a or state) begin case (state) A: if (a) next_state <= B; else next_state <= A; B: if (a) next_state <= C; else next_state <= A; C: if (a) next_state <= B; else next_state <= D; D: if (a) next_state <= C; else next_state <= D; endcase end always @(a or state) begin case (state) A: z1 <= a ? 0: 1; B: z1 <= 0; C: z1 <= 0; D: z1 <= a ? 0: 1; endcase end endmodule

4-bit Storage Register

A B C

QA QB QC QD C

RESET LOAD CLK

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module Reg_4_Bit(CLK, LOAD, RESET, A, Q); input CLK, RESET, LOAD; input [3:0] A; output [3:0] Q; reg [3:0] Q_reg; assign Q <= Q_reg; always @(posedge CLK) begin if (!RESET) Q_reg <= 0; else if (LOAD) Q_reg <= A; end endmodule

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4-bit Shift Register with Asynchronous Clear

SI Q0

Q1 Q2 Q3

RESET

CLK

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module ShiftReg_4_Bit(CLK, RESET, SI, Q); input CLK, RESET, SI; output [3:0] Q; reg [3:0] Q_reg; assign Q <= Q_reg; initial begin Q_reg <= 4’b0000; end always @(posedge CLK or posedge RESET) begin if (!RESET) Q_reg <= 4’b0000; else Q_reg <= {Q[2:0], SI}; end endmodule 68

4-bit Binary Counter with Synchronous Clear

EN Q0

Q1 Q2 Q3

RESET

CLK

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module Count_4_Bit(CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] Q_reg; assign CO = (Q_reg == 15 && EN == 1) ? 1: 0; assign Q <= Q_reg; always @(posedge CLK) begin if (!RESET) Q_reg <= 0; else if (EN) Q_reg <= Q_reg + 1; end endmodule

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16 x 8-bit synchronous RAM

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RamData15RamData14

RamData0

Dout

Dout7Dout6Dout5Dout4Dout3Dout2Dout1Dout0

ADDR3ADDR2ADDR1ADDR0

Din7Din6Din5Din4Din3Din2Din1Din0

CLCCSWE

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module RAM_16x8(ADDR, CLK, CS, WE, Din, Dout); input CLK, CS, WE; input [3:0] ADDR; input [7:0] Din; output [7:0] Dout; reg [7:0] Dout_Reg; reg [7:0] RamData[15:0]; assign Dout <= Dout_Reg; always @(posedge CLK) begin if (CS) if (WE) Ram_Data[ADDR] <= Din; else Dout_Reg <= Ram_Data[ADDR]; end endmodule

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1 ECE 2372 Modern Digital System Design Section 7.1 Introduction to Hardware Descriptive Language.

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Transcript of 1 ECE 2372 Modern Digital System Design Section 7.1 Introduction to Hardware Descriptive Language.