1 CPC2-CPR2 Assemblies Testing Status Tim Woolliscroft.
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1 CPC2-CPR2 Assemblies Testing Status Tim Woolliscroft
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Transcript of 1 CPC2-CPR2 Assemblies Testing Status Tim Woolliscroft.
1
CPC2-CPR2 Assemblies Testing Status
Tim Woolliscroft
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Brief history• First signals with assemblies on MB4.2
– Initial test were promising– Failed after one day, unknown cause– All subsequent assemblies in MB4.2 also failed
• One chip mounted in MB4.4 (from GelPack1) was assumed to be dead
• GelPack2 inspected– Corrosion found– 4 Chips thought to still bondable and good
• 11/05/07, two more chips mounted onto MB4.4 (#1 & #2)• 17/05/07, fault found with MB4.4 (VDC to CPR1 and CPR2 swapped)
– First assembly in MB4.4 may have been destroyed unnecessarily
• 17/05/07, MB4.4 #2 was cooled and Fe55 signals seen• Has worked every day this week with overnight shutdown
100k
1
10
100
1k
10k
ADC code310 2 4 6 8 10 12 14 16 18 20 22 24 26 28
Code densityADC code density
3
Testing procedure
Similar to before except with extreme paranoia1. Sequencer & CPR Control running 2. Power up the MB ( +/-12V, +/-5V)3. Power up 3.3V on MB4. Exercise the opto-couplers on MB (can be ambiguous on
power up)5. Set correct power up mode for CPR6. Load the DACs on MB -> power CPR with 2.5V 7. Set direct ADC output mode, check for ADC noise8. Cool9. Raise the bias of CPR ground and CPC outputs in 2V
steps Reverse applies for shutdown, without the warming up bit
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How it works
CPR2 ADCs constantly clocked, output is latched and saved during the CPC clocking.
Sequence repeated at 500ms (Fe55 integration time)
CPC voltage channels reset after clocking, before upsets the baseline of the CPR ADCs (why?)
Time
CCD Clock
NC
NC
MB amplifiers active
Reset voltage pulse
NC
NC
Phase correction for CPR clocks
CPR2 ADC digital output is stored to memory
CPR2 Voltage amplifier output
CPC output
Hits ☺
1MHz CPC clocking
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How it works
CPR2 ADCs constantly clocked, output is latched and saved during the CPC clocking.
Sequence repeated at 500ms (Fe55 integration time)
CPC voltage channels are reset after clocking, if done before upsets the baseline of the CPR ADCs (why?)
Time
CCD Clock
NC
NC
MB amplifiers active
Reset voltage pulse
NC
NC
Phase correction for CPR clocks
CPR2 ADC digital output is stored to memory
Hit ☺
CPR2 Voltage amplifier output
CPC output
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How it looks• Capture Data soon as CPC clock
starts, causing a little disruption• 300mV ADC Range• Baseline is quite flat• Hits are clearly visible• Disruption at end
• Select window, linear fit, restore baseline to ADU 32
• Noise is around 60 to 100 e-– Need to improve fitting
• DNL is OK– Few missing codes – But only 1MHz clock and large
range
1E+6
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
Relative ADC500 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
Histogram
Noise Fit
Fe55 Fit
7
Optimisation
• 3 Timing parameters– CLK1 & 2 duty cycle– CPC–CPR CLK Phase
• Seems to like Clocks as shown
• Short CLK2 decreases gain (why?)
• CPC–CPR CLK Phase not very critical
CLK1CLK2
VOUT2
8
Optimisation
• 3 Timing parameters– CLK1 & 2 duty cycle– CPC–CPR CLK Phase
• CPR Biasing
ADC range
Voltage amp biasing
Charge amp biasing
Voltage and charge amp offsets
9
1E+6
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
Relative ADC500 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
Histogram
Noise Fit
Fe55 Fit
Optimisation
• Variations in clocking and biasing lead to...
Amplifier oscillation, Amplifier restoration, overshoot & undershoot
31
0
5
10
15
20
25
Time450400 410 420 430 440
FitRaw Data
1E+6
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
Relative ADC500 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
Histogram
Noise Fit
Fe55 Fit
31
0
5
10
15
20
25
Time380360 365 370 375
FitRaw Data
10
Channel Gain Matching
Scan all voltage channels, using the same settings.
Using 300mV ADC range
Plot as signal as 1D histogram
Compare edge channel
With middle channel
Significant drop in gain towards middle of the chip
100k
1
10
100
1k
10k
ADC code310 2 4 6 8 10 12 14 16 18 20 22 24 26 28
Code densityADC 142
100k
1
10
100
1k
10k
ADC code310 2 4 6 8 10 12 14 16 18 20 22 24 26 28
Code densityADC 242
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Channel Gain Matching
Fe55 Peak
Noise Peak
Sofa Plot
(Gets uncomfortable here)
Scan all voltage channels, using the same settings.
Using 300mV ADC range
Plot as signal as 2D histogram
Or as 3D plot
Significant drop in gain towards middle of the chip
Middle of chip
Edge of chip
12
Channel Gain Matching
Scan all voltage channels, using the same settings.
Using 300mV ADC range
Probably not ADC’s, VDC test shows no gain loss
ADC 140
ADC 240
13
2MHz
• Using 200mV ADC Range– Lost a bit in gain– Needs more work to improve gain
ADC # 190
85e- noise
1E+6
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
Relative ADC500 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
Histogram
Noise Fit
Fe55 Fit
ADC # 210
65e- noise
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Conclusions
• Testing is in the early stages– Voltage channels are working
• Good noise performance up to 2MHz
• Still need a little optimisation, difficult to do systematically
• Gain across the chip is uneven
– Nothing but noise from charge channels• Seem to be affected by digital signals
• Possible to get cluster finder working?– Turn of charge channels– Lower hit densities
• Want to go faster– MB5.0?
