1 CAPS Compilers Activities IRISA Campus Universitaire de Beaulieu 35042 Rennes.
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Transcript of 1 CAPS Compilers Activities IRISA Campus Universitaire de Beaulieu 35042 Rennes.
1
CAPSCompilers Activities
IRISA
Campus Universitaire de Beaulieu
35042 Rennes
2
CA
PS
TE
AM
• Architecture– André Seznec (Director of Research, CAPS group leader)– Pierre Michaud (Researcher)– Jacques Lenfant (Professor)– Thierry Lafage (PhD)– Jonathan Perret (PhD)– Romain Dolbeau (PhD)
• Compiler– F. Bodin (Professor)– Antoine Monsifrot (PhD)– Ronan Amicel (PhD)– Gilles Pokam (PhD)– Laurent Bertaux (PhD)– Laurent Morin (PhD)– Karine Heydemann (PhD)
3
Bac
kgro
un
d• Architecture
– high performance (co-)processors– superscalar microprocessors– memory hierarchy– branch prediction mechanism, ...
• Compiler– high performance computing– parallel computing– optimizations for VLIW– preprocessor infrastructures– code transformations
4
Co
mp
iler
Act
ivit
ies
• Code optimizations for embedded applications– infrastructures– optimizing compiler strategies
• Global constraints– code sizes– low power (starting)
• Interactive tools– code tuning– case based reasoning– assembly code optimizations
5
Ove
r vie
w
InterfaceFront-end
TargetDescription(s)
CodeGeneration
Back-endOptimizer
Instruction setSimulator
tool 2
tool 1
tool 3
tool 4
feedback
6
Fo
rtra
n C
od
e O
pti
miz
atio
n• Provides tools for code tuning
– user oriented
– case based reasoning
– static code analysis and pattern matching
– profiling
• Infrastructure used
– Foresys: Fortran interactive front-end (from Simulog)
– TSF: Scripting language for program transformation (developed by CAPS)
• Bibliography:
symboltable
executablestatement
variabledeclaration
program text
program unit
TSF scriptsscript local variable stack
script global variables
scripts instructions
var1var2var3...
Foresysdisplay
scriptsapply
context variables
“FITS - A Light-Weight Integrated
Programming Environment”, B.
Chapman, F. Bodin, L. Hill, J.
Merlin, G. Viland, F. Wollenweber,
Euro-Par'99
7
Ass
emb
ly C
od
e O
pti
miz
atio
n• Provide methods and tools for analyzing code quality and for fine grain
tuning– VLIW architectures– navigation in the assembly code– access to profiling and compiler data– link with the source code
• Infrastructure used
– Salto
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Hig
h P
erfo
rman
ce In
stru
ctio
n S
et
Sim
ula
tio
n• Provide new generation techniques for instruction set simulation
– high performance, simulation of large code, debugging– flexible– retargetable, experiment new instruction sets
• Infrastructure– Salto
C Source TriMedia Assembly code tmcc
TriMedia Binary
generator
tmsim
tmas
gcc/ld
C++ Source
compile simulation
Architecture
description
9
Sch
edu
ling
Infr
astr
uct
ure • SALTO2
– provide new infrastructure better suited for code optimization
– more abstract interface
– more integration with code generation
ArchitectureDescription
D ® M Architecture Model
Intermediate representation
Opt 1 Opt 2 Opt n
P ® RITextInput
D ® Ass(Emit)
OptimizedProgram
interface to IR
InterfacesExternal
Infrastructure
User interfaceG.U.I.
IntermediateCode
10
Pr e
pro
cess
or
Mu
ltim
edia
In
stru
ctio
n• Provide tools to help rewriting code source for exploiting multimedia
instructions
A S TCCMIR
SWARgen
Unparser
IR Graphrewriting
SWARcc
Patternmatching
COSY
Rules
C Code
Declaration
The SWAR SYSTEM
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Iter
ativ
e C
om
pila
tio
n• Dealing with global constraints
• Better control of tradeoffs
• Bibliography:
2.45E+08
2.50E+08
2.55E+08
2.60E+08
2.65E+08
2.70E+08
2.75E+08
2.80E+08
2.85E+08
120 170 220 270 320 370 420
code size (instructions)
nu
mb
er o
f cy
cles
(S0,S0,S0,S0,S0)
(I,I,U8,U8,S0)
(S0,S0,U2,S0,S0)
(I,S0,S0,S0,S0)
(I,S0,U2,S0,S0)
1
2
MPEG-2
1.00E+08
1.10E+08
1.20E+08
1.30E+08
1.40E+08
1.50E+08
1.60E+08
1.70E+08
1.80E+08
1.90E+08
70 90 110 130 150 170 190 210
code size (instructions)
nu
mb
er o
f cy
cles
1
2
H-263
“Handling Global Constraints in Compiler Strategy”, Erven Rohou, François Bodin, Christine Eisenbeis and André Seznec, to appear in International Journal of Parallel Programming