1 1998 Morgan Kaufmann Publishers & Ing-Jer Huang Chapter Five last upate: 6/24/2015.

11998 Morgan Kaufmann Publishers & Ing-Jer Huang

Chapter Five

last upate: 04/18/23


• We're ready to look at an implementation of the MIPS

• Simplified to contain only:

– memory-reference instructions: lw, sw – arithmetic-logical instructions: add, sub, and, or, slt– control flow instructions: beq, j

• Generic Implementation:

– use the program counter (PC) to supply instruction address

– get the instruction from memory

– read registers

– use the instruction to decide exactly what to do

• All instructions use the ALU after reading the registers

Why? memory-reference? arithmetic? control flow?

The Processor: Datapath & Control


• Abstract / Simplified View:

Two types of functional units:– elements that operate on data values (combinational)– elements that contain state (sequential)

More Implementation Details

Registers

Register #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALU

Instructionmemory

Address


• Unclocked vs. Clocked

• Clocks used in synchronous logic

– when should an element that contains state be updated?

cycle time

rising edge

falling edge

State Elements


• The set-reset latch

– output depends on present inputs and also on past inputs

An unclocked state element


• Output is equal to the stored value inside the element(don't need to ask for permission to look at the value)

• Change of state (value) is based on the clock

• Latches: whenever the inputs change, and the clock is asserted

(level-triggered methodology)

• Flip-flop: state changes only on a clock edge(edge-triggered methodology)

"logically true", ?could mean electrically low

A clocking methodology defines when signals can be read and writtenYou wouldn't want to read a signal at the same time it was being written

Latches and Flip-flops


D-latch

• Two inputs:– the data value to be stored

(D)– the clock signal (C) indicating

when to read & store D• Two outputs:

– the value of the internal state (Q) and it's complement

Q

C

D

_Q


D flip-flop

• Output changes only on the clock edge

• Negative (falling) edge in this example

QQ

_Q

Q

_Q

Dlatch

D

C

Dlatch

DD

C

C


Our Implementation

• An edge triggered methodology

• Typical execution:

– read contents of some state elements,

– send values through some combinational logic

– write results to one or more state elements

Clock cycle

Stateelement

1Combinational logic

Stateelement

2


• Built using D flip-flops

Register File

Mux

Register 0

Register 1

Register n – 1

Register n

Mux

Read data 1

Read data 2

Read registernumber 1


Read registernumber 1 Read

data 1

Readdata 2


Register fileWriteregister

Writedata Write


Register File

• Note: we still use the real clock to determine when to write

n-to-1decoder

Register 0

Register 1

Register n – 1C

C

D

DRegister n

C

C

D

D

Register number

Write

Register data

0

1

n – 1

n


Simple Implementation

• Include the functional units we need for each instruction

Why do we need this stuff?

PC

Instructionmemory

Instructionaddress

Instruction

a. Instruction memory b. Program counter

Add Sum

c. Adder

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

16 32Sign

extend

b. Sign-extension unit

MemRead

MemWrite

Datamemory

Writedata

Readdata

a. Data memory unit

Address


Arithmetic operations

Register access

Figure5.7 Data path for the R-type instructions

Load path

Store

Store path

Figure5.9 Data path for load/store

M[R1+Immed]<-R2

R2<-M[R1+Immed]


Building the Datapath

• Use multiplexors to stitch them together

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add


branch

PC increment

Branch Target Address

mux : multiple sources

Fan out : multiple destinations

Parallelism : speculative executionRegister reads

PC values

Data Path forload / store

ALU

branch

instructions

……single cycle implementationPC++

Figure5.14

Major system state


Instruction fetch Branch

Memory + R-type

I-type

R-type

The Data path with multiplexors and control signals

mux : multiple sources

fan out : multiple destinations

Figure5.17


Control

• Selecting the operations to perform (ALU, read/write, etc.)

• Controlling the flow of data (multiplexor inputs)

• Information comes from the 32 bits of the instruction

• Example:

add $8, $17, $18 Instruction Format:

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

• ALU's operation based on instruction type and function code


• e.g., what should the ALU do with this instruction• Example: lw $1, 100($2)

35 2 1 100

op rs rt 16 bit offset

• ALU control input

000 AND001 OR010 add110 subtract111 set-on-less-than

• Why is the code for subtract 110 and not 011?

Control

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

a.


• Must describe hardware to compute 3-bit ALU conrol input

– given instruction type (classify the ALU operations according to op code)

00 = lw, sw (+)01 = beq, (-)10 = arithmetic

– function code for arithmetic

• Describe it using a truth table (can turn into gates):

ALUOp computed from instruction type

ALU Control

ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X 010X(0) 1 X X X X X X 110

1 X(0) X X 0 0 0 0 0101 X(0) X X 0 0 1 0 1101 X(0) X X 0 1 0 0 0001 X(0) X X 0 1 0 1 0011 X(0) X X 1 0 1 0 111


Control

Instruction RegDst ALUSrcMemto-

RegReg

WriteMem Read

Mem Write Branch ALUOp1 ALUp0

R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20– 16]


Add


MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc


4

16 32Instruction [15– 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1


ALUcontrol

ALUAddress


Control

• Simple combinational logic (truth tables)

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5– 0)

ALUOp0

ALUOp

ALU control block

R-format Iw sw beq

Op0

Op1

Op2

Op3

Op4

Op5

Inputs

Outputs

RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOpO


• All of the logic is combinational

• We wait for everything to settle down, and the right thing to be done

– ALU might not produce the right answer right away

– we use write signals along with clock to determine when to write

• Cycle time determined by length of the longest path

Our Simple Control Structure

We are ignoring some details like setup and hold times

Clock cycle

Stateelement

1Combinational logic

Stateelement

2


Single Cycle Implementation

• Calculate cycle time assuming negligible delays except:– memory (2ns), ALU and adders (2ns), register file access (1ns)

– Find the critical path…R-type: 5ns; LW: 7ns; SW:5ns; BEQ: 5ns,…

MemtoReg

MemRead

MemWrite

ALUOp

ALUSrc

RegDst

PC

Instructionmemory

Readaddress




Add


RegWrite

4

16 32Instruction [15– 0]

0Registers

WriteregisterWritedata

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address Readdata M

ux

1

0

Mux

1

0

Mux

1

0

Mux

1


ALUcontrol

Shiftleft 2

PCSrc

ALU

Add ALUresult


The single cycle datapath of an add instruction

100 add rd, rs, rt 0 rs rt rd 0

rs

rt

0X20

rd


The single cycle datapath of load instruction

104 lw $rt, $rs, offset 0x23 rs rt Offset

rs

rt

Offset


Where we are headed

• Single Cycle Problems:

– what if we had a more complicated instruction like floating point?

– wasteful of area

• One Solution:

– use a smaller cycle time

– have different instructions take different numbers of cycles

– a multicycle datapath: sharing, extra internal registers

PC

Memory

Address

Instructionor data

Data

Instructionregister

Registers

Register #

Data

Register #

Register #

ALU

Memorydata

register

A

B

ALUOut


• We will be reusing functional units

– ALU used to compute address and to increment PC

– Memory used for instruction and data

• Our control signals will not be determined solely by instruction

– e.g., what should the ALU do for a subtract instruction?

• We will use a finite state machine for control

Multicycle Approach


• Finite state machines:– a set of states and – next state function (determined by current state and the input)– output function (determined by current state and possibly input)

– We will use a Moore machine (output based only on current state)– Cf. Mealy machine (output based on BOTH the current state and input)

Review: finite state machines

Next-statefunction

Current state

Clock

Outputfunction

Nextstate

Outputs

Inputs


Review: finite state machines

• Example:

B. 21 A friend would like you to build an electronic eye for use as a fake security device. The device consists of three lights lined up in a row, controlled by the outputs Left, Middle, and Right, which, if asserted, indicate that a light should be on. Only one light is on at a time, and the light moves from left to right and then from right to left, thus scaring away thieves who believe that the device is monitoring their activity. Draw the graphical representation for the finite state machine used to specify the electronic eye. Note that the rate of the eye’s movement will be controlled by the clock speed (which should not be too great) and that there are essentially no inputs.


FSM

Next Value 4

Current Value 3

clk

rst

register

FSM description in Verilog (Hardware Description Language)

always@(posedge clk or posedge rst)begin: proc_fsm_trans if(rst) current_value <= `initial_value; else current_value <= next_value;end // proc_fsm_trans

always@(current_value) next_value = current_value+1’b1;

FSM description in Verilog (Hardware Description Language)

always@(posedge clk or posedge rst)begin: proc_fsm_trans if(rst) current_value <= `initial_value; else current_value <= next_value;end // proc_fsm_trans

always@(current_value) next_value = current_value+1’b1;


FSM

register {s1,s0}

{s1’,s0’}

Combinational Logic (drive output)

Combinational Logic (drive next state)

register


• Break up the instructions into steps, each step takes a cycle

– balance the amount of work to be done

– restrict each cycle to use only one major functional unit

• At the end of a cycle

– store values for use in later cycles (easiest thing to do)

– introduce additional internal registers

Multicycle Approach

Shiftleft 2

PC

Memory

MemData

Writedata

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Mux

0

1

Mux

0

1

4


Signextend

3216




Instructionregister

1 Mux

0

3

2

Mux

ALUresult

ALUZero

Memorydata

register


A

B

ALUOut

0

1

Address


The multi cycle datapath


• Instruction Fetch

• Instruction Decode and Register Fetch

• Execution, Memory Address Computation, or Branch Completion

• Memory Access or R-type instruction completion

• Write-back step

INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

Five Execution Steps


• Use PC to get instruction and put it in the Instruction Register.

• Increment the PC by 4 and put the result back in the PC.

• Can be described succinctly using RTL “Register-Transfer Language”

IR = Memory[PC];PC = PC + 4; (speculative computing)

•Can we figure out the values of the control signals?

What is the advantage of updating the PC now?

Step 1: Instruction Fetch


• Generate the control signals based on the value in the instruction register.

• Read registers rs and rt in case we need them• Compute the branch address in case the instruction is a branch• RTL:

A = Reg[IR[25-21]]; (speculative computing)• B = Reg[IR[20-16]];

ALUOut = PC + (sign-extend(IR[15-0]) << 2);

• We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)

Step 2: Instruction Decode and Register Fetch


• ALU is performing one of three functions, based on instruction type

• Memory Reference:

ALUOut = A + sign-extend(IR[15-0]);

• R-type:

ALUOut = A op B;

• Branch: (complete in this step)

if (A==B) PC = ALUOut;

Step 3 (instruction dependent)


• Loads and stores access memory

MDR = Memory[ALUOut]; (load)

orMemory[ALUOut] = B; (store is completed)

• R-type instructions finish

Reg[IR[15-11]] = ALUOut;

The write actually takes place at the end of the cycle on the edge

Step 4 (R-type or memory-access)


• Reg[IR[20-16]]= MDR;

What about all the other instructions?

Write-back step


Summary:

Step nameAction for R-type

instructionsAction for memory-reference

instructionsAction forbranches

Action forjumps

Instruction fetch IR = Memory[PC]PC = PC + 4

Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0]) << 2)

Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion

Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or

Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR


What if there is no speculation?




Action forjumps



Execution, address ALUOut = A op B ALUOut = A + sign-extend ALUOut = PC + PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) (sign-extend (IR[15-0]) << 2)(IR[25-0]<<2)jump completion

Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut] if (A ==B) thencompletion ALUOut or PC = ALUOut




What if there is no speculation? (some improvement)




Action forjumps



Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = PC + (IR[25-0]<<2)

jump completion(sign-extend

(IR[15-0]) << 2)

Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or



One ALU, one adder

One ALU, one adder


• How many cycles will it take to execute this code?

lw $t2, 0($t3)lw $t3, 4($t3)beq $t2, $t3, Label #assume notadd $t5, $t2, $t3sw $t5, 8($t3)

Label: ...

• What is going on during the 8th cycle of execution?• In what cycle does the actual addition of $t2 and $t3 takes place?

Simple Questions


Comparing Single-cycle and Multi-cycle impmentations

• Single Cycle– Cycle time: 7 ns– CPI: 1 for all instructions

• Multi Cycle– Cycle time: 2 ns– CPI

• R-type: 4

• Memory (load): 5

• Memory (store): 4

• Branch/Jump: 3


• Value of control signals is dependent upon:– what instruction is being executed– which step is being performed

• Use the information we have accumulated to specify a finite state machine– specify the finite state machine graphically, or– use microprogramming

• Implementation can be derived from specification• Register update:

– By the clock signal alone• For data with life span of one clock cycle (A, B, ALUout, EPC, Cause)• simpler, no control signal, useless updates

– By both the clock signal and explicit enable signals…need explicit control signals

• For data with life span of more than one clock cycles (IR, PC, MDR)• Need explicit control logics and signal pins; no useless update

Implementing the Control

• How many state bits will we need?

Graphical Specification of FSM

PCWritePCSource = 10

ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCond

PCSource = 01

ALUSrcA =1ALUSrcB = 00ALUOp= 10

RegDst = 1RegWrite

MemtoReg = 0

MemWriteIorD = 1

MemReadIorD = 1

ALUSrcA = 1ALUSrcB = 10ALUOp = 00

RegDst = 0RegWrite

MemtoReg =1

ALUSrcA = 0ALUSrcB = 11ALUOp = 00

MemReadALUSrcA = 0

IorD = 0IRWrite

ALUSrcB = 01ALUOp = 00

PCWritePCSource = 00

Instruction fetchInstruction decode/

register fetch

Jumpcompletion

BranchcompletionExecution

Memory addresscomputation

Memoryaccess

Memoryaccess R-type completion

Write-back step

(Op = 'LW') or (Op = 'SW') (Op = R-type)

(Op

= 'B

EQ')

(Op

= 'J

')

(Op = 'SW

')

(Op

= 'L

W')

4

01

9862

753

Start


Final data path and control path: multi-cycle w/ exception handling

No enable signals for MDR, A, B, ALUout

Enable signals for PC, IR, EPC, Cause (due to lifespan > 1 cycle)


Step 1 taken to execute add instruction


instructionsAction for memory-

reference instructionsAction for branches

Action for jumps

Instruction fetchIR = Memory[PC]

PC = PC + 4

Instruction decode/register

fetch

A = Reg [IR[25-21]]B = Reg [IR[20-16]]ALUOut = PC + (sign-extend(IR[15-0])<<2)

Execution, address

computation, branch/jump computation

ALUOut = A op BALUOut= A + sign-extend

(IR[15-0])If(A==B) then PC = ALUOut

PC=PC[31-28] || (IR[25-0]<<2)

Memory access or R-type

completion

Reg[IR[15-11]] = ALUout

Load : MDR = Memory[ALUout]or

Store : Memory[ALUout] = B

Memory read completion

Load : Reg [IR[20-16]] = MDR


The multi cycle datapath of add instruction (cycle 1)

add rd, rs, rt 0 rs rt rd 0 0X20



Ing-Jer Huang

After





Action for jumps


PC = PC + 4


fetch

A = Reg [IR[25-21]]B = Reg [IR[20-16]]ALUOut = PC + (sign-extend(IR[15-0]<<2)) % Speculative Computing

Execution, address




PC=PC[31-28] || (IR[25-0]<<2)


completion










rsrt

ALUOut = PC + (sign-extend(IR[15-0]<<2)) (Speculative Computing)




Ing-Jer Huang

After





Action for jumps


PC = PC + 4


fetch

A = Reg [IR[25-21]]B = Reg [IR[20-16]]ALUOut = PC + (sign-extend(IR[15-0]<<2))

Execution, address




PC=PC[31-28] || (IR[25-0]<<2)


completion










ALUOut = A op B



Ing-Jer Huang

After





Action for jumps


PC = PC + 4


fetch


Execution, address




PC=PC[31-28] || (IR[25-0]<<2)


completion








The multi cycle datapath of lw instruction

0x23 rs rt Offset lw rt, offset(rs)


Step 1 taken to execute lw instruction




Action for jumps


PC = PC + 4


fetch


Execution, address




PC=PC[31-28] || (IR[25-0]<<2)


completion







lw rt, offset(rs) 0x23 rs rt Offset

The multi cycle datapath of lw instruction (cycle 1)





Action for jumps


PC = PC + 4


fetch


Execution, address




PC=PC[31-28] || (IR[25-0]<<2)


completion









rsrt







Action for jumps


PC = PC + 4


fetch


Execution, address




PC=PC[31-28] || (IR[25-0]<<2)


completion










ALUOut = A + sign-extend (IR[15-0])





Action for jumps


PC = PC + 4


fetch


Execution, address




PC=PC[31-28] || (IR[25-0]<<2)


completion








Exception

• Exception• Events other than branches or jumps that change the normal flow of instruction exec

ution• Three types of exception

– Internal events: unexpected events from within the processor• Examples: arithmetic overflow; undefined instructions

– External events: unexpected events from outside of the processor• I/O events

– Program controlled events: events generated by software• System call (software interrupt), ex,, printf

• Different interpretations– MIPS: exception for both internal and external events– INTEL 80x86: interrupt for both internal and external events– PowerPC: exception for event occurring and interrupt for the change in control fl

ow


Exception handling

• Save the address of the offending instruction in the exception program counter (EPC).

• Record the reason for the exception:

– Status register (Cause register): MIPS approach; or

– Vectored interrupt: Intel 80x86 approach

• Set the new value of PC to the address of the exception service routine.

– Same address for all kinds of exception (MIPS approach)

– Distinct address for each kind of exception (Intel 80x86 approach)


Modifying the FSM for exception handling


Exceptions (overflow)


The multi cycle datapath of add instruction with overflow (cycle 5, state 11)


pcsource = 11

Record cause: Cause = 1Save EPC: EPC = PC (=PCold+4) – 4

Set new PC: PC = C0000…



PCold+4

Ing-Jer Huang

Also show the setting of EPC and Cause


Exceptions (undefined instruction)


The multi cycle datapath of undefined instruction (cycle 3, state 10)

undef rd, rs, rt 0x16 rs rt rd 0 0x10

pcsource = 11

?



PCold+4


• Implementation:

Finite State Machine for Control

PCWrite

PCWriteCond

IorD

MemtoReg

PCSource

ALUOp

ALUSrcB

ALUSrcA

RegWrite

RegDst

NS3NS2NS1NS0

Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

State register

IRWrite

MemRead

MemWrite

Instruction registeropcode field

Outputs

Control logic

Inputs


PLA Implementation

• If I picked a horizontal or vertical line could you explain it?Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

IorD

IRWrite

MemReadMemWrite

PCWritePCWriteCond

MemtoRegPCSource1

ALUOp1

ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1NS0

ALUSrcB1ALUOp0

PCSource0


• ROM = "Read Only Memory"– values of memory locations are fixed ahead of time

• A ROM can be used to implement a truth table– if the address is m-bits, we can address 2m entries in the ROM.– our outputs are the bits of data that the address points to.

m is the height", and n is the "width"

ROM Implementation

m n

0 0 0 0 0 1 10 0 1 1 1 0 00 1 0 1 1 0 00 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 11 1 0 0 1 1 01 1 1 0 1 1 1


• How many inputs are there?6 bits for opcode, 4 bits for state = 10 address lines(i.e., 210 = 1024 different addresses)

• How many outputs are there?16 datapath-control outputs, 4 state bits = 20 outputs

• ROM is 210 x 20 = 20K bits (and a rather unusual size)

• Rather wasteful, since for lots of the entries, the outputs are the same

i.e., opcode is often ignored

ROM Implementation


• Break up the table into two parts

– 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM

– 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM

– Total: 4.3K bits of ROM

• PLA is much smaller

– can share product terms

– only need entries that produce an active output

– can take into account don't cares

• Size is (#inputs #product-terms) + (#outputs #product-terms)

For this example = (10x17)+(20x17) = 460 PLA cells

• PLA cells usually about the size of a ROM cell (slightly bigger)

ROM vs PLA


• Complex instructions: the "next state" is often current state + 1

Another Implementation Style

AddrCtl

Outputs

PLA or ROM

State

Address select logic

Op

[5–

0]

Adder


1

Control unit

Input

PCWritePCWriteCondIorD

MemtoRegPCSourceALUOpALUSrcBALUSrcARegWriteRegDst

IRWrite

MemReadMemWrite

BWrite


DetailsDispatch ROM 1 Dispatch ROM 2

Op Opcode name Value Op Opcode name Value000000 R-format 0110 100011 lw 0011000010 jmp 1001 101011 sw 0101000100 beq 1000100011 lw 0010101011 sw 0010

State number Address-control action Value of AddrCtl

0 Use incremented state 31 Use dispatch ROM 1 12 Use dispatch ROM 2 23 Use incremented state 34 Replace state number by 0 05 Replace state number by 0 06 Use incremented state 37 Replace state number by 0 08 Replace state number by 0 09 Replace state number by 0 0

State

Op

Adder

1

PLA or ROM

Mux3 2 1 0

Dispatch ROM 1Dispatch ROM 2

0

AddrCtl




Microprogramming

• What are the icroinstructions??

PCWritePCWriteCondIorD

MemtoRegPCSourceALUOpALUSrcBALUSrcARegWrite

AddrCtl

Outputs

Microcode memory

IRWrite

MemReadMemWrite

RegDst

Control unit

Input

Microprogram counter


Op[

5–

0]

Adder

1

Datapath


BWrite


• A specification methodology– appropriate if hundreds of opcodes, modes, cycles, etc.– signals specified symbolically using microinstructions

–

–

• Will two implementations of the same architecture have the same microcode?• What would a microassembler do?

Microprogramming

LabelALU

control SRC1 SRC2Register control Memory

PCWrite control Sequencing

Fetch Add PC 4 Read PC ALU SeqAdd PC Extshft Read Dispatch 1

Mem1 Add A Extend Dispatch 2LW2 Read ALU Seq

Write MDR FetchSW2 Write ALU FetchRformat1 Func code A B Seq

Write ALU FetchBEQ1 Subt A B ALUOut-cond FetchJUMP1 Jump address Fetch

Microinstruction formatField name Value Signals active Comment

Add ALUOp = 00 Cause the ALU to add.ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for

branches.Func code ALUOp = 10 Use the instruction's function code to determine ALU control.

SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input.A ALUSrcA = 1 Register A is the first ALU input.B ALUSrcB = 00 Register B is the second ALU input.

SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input.Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input.Extshft ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input.Read Read two registers using the rs and rt fields of the IR as the register

numbers and putting the data into registers A and B.Write ALU RegWrite, Write a register using the rd field of the IR as the register number and

Register RegDst = 1, the contents of the ALUOut as the data.control MemtoReg = 0

Write MDR RegWrite, Write a register using the rt field of the IR as the register number andRegDst = 0, the contents of the MDR as the data.MemtoReg = 1

Read PC MemRead, Read memory using the PC as address; write result into IR (and lorD = 0 the MDR).

Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR.lorD = 1

Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as thelorD = 1 data.

ALU PCSource = 00 Write the output of the ALU into the PC.PCWrite

PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contentsPCWriteCond of the register ALUOut.

jump address PCSource = 10, Write the PC with the jump address from the instruction.PCWrite

Seq AddrCtl = 11 Choose the next microinstruction sequentially.Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction.

Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1.Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2.


• No encoding:

– 1 bit for each datapath operation

– faster, requires more memory (logic)

– used for Vax 780 ?an astonishing 400K of memory!

• Lots of encoding:

– send the microinstructions through logic to get control signals

– uses less memory, slower

• Historical context of CISC:

– Too much logic to put on a single chip with everything else

– Use a ROM (or even RAM) to hold the microcode

– It easy to add new instructions

Maximally vs. Minimally Encoded


Microcode: Trade-offs

• Distinction between specification and implementation is sometimes blurred

• Specification Advantages:

– Easy to design and write

– Design architecture and microcode in parallel

• Implementation (off-chip ROM) Advantages

– Easy to change since values are in memory

– Can emulate other architectures

– Can make use of internal registers

• Implementation Disadvantages, SLOWER now that:

– Control is implemented on same chip as processor

– ROM is no longer faster than RAM

– No need to go back and make changes


The Big Picture

Initialrepresentation

Finite statediagram

Microprogram

Sequencingcontrol

Explicit nextstate function

Microprogram counter+ dispatch ROMS

Logicrepresentation

Logicequations

Truthtables

Implementationtechnique

Programmablelogic array

Read onlymemory

1 1998 Morgan Kaufmann Publishers & Ing-Jer Huang Chapter Five last upate: 6/24/2015.

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Transcript of 1 1998 Morgan Kaufmann Publishers & Ing-Jer Huang Chapter Five last upate: 6/24/2015.