06/05/08 Biscotti: a Framework for Token-Flow based Asynchronous Systems Charlie Brej.
-
Upload
howard-spall -
Category
Documents
-
view
216 -
download
0
Transcript of 06/05/08 Biscotti: a Framework for Token-Flow based Asynchronous Systems Charlie Brej.
06/05/08
Overview
The tool problem
Proposed system
Biscotti components
Their current state
Example uses
Conclusions
And future work
06/05/08
Wagging Flow ProblemTLF
Read
Async Trans.Desynchronise
NetlistFlatten
TimingLibrary
TimingExtract
NetlistFlatten
VerilogWrite
SimulationPerformance
VerilogRead
Async Trans.Wag
06/05/08
Commercial Tools
Unsuitable
Critical path extraction
Broken
Timing extraction of cyclic designs
Inflexible
Limited simulation trace extraction
Unimplemented
DI logic synthesis
06/05/08
Biscotti Aims
Complete framework for token flow systems
Aims to recreate all tools required to make a design
Modular
Set of libraries
Open Source
GPLv3
Expandable and Customisable
Trivial to add or replace any part with own version
06/05/08 8
Parts
Verilog TLF
Verilog SDF
SimulationNetlist
Operations
Timing Wagging
Async Transformations
Tech-map
06/05/08 9
Input
Verilog
Modules, Gates
UDPs with MVL extensions
No behavioral
TLF
Cell characterisations
Splines
In: Capacitance and Slew
Out: Delay and Slew
primitive trinary_C(Z,A,B); output Z; input A, B; reg Z; table
// A B : Z : Z’ 0 0 : ? : 0; 1 1 : ? : 1; 2 2 : ? : 2; ? ? : ? : -; endtableendprimitive
06/05/08 10
Output Verilog
Patchy
Generates verilog executable with NC-Verilog
SDF
Timing extraction files used by external simulators
06/05/08 11
Processing 1 Netlist Operations
Internal netlist representation
Allows constructing, altering, flattening...
The basis of all other tools
Timing
Cell timing characteristics (TLF)
Circuit timing extraction
Characterisation of constructed modules
06/05/08 12
Processing 2
Pipeline Synthesis
Takes a directed flow graph (DFG) style circuit
Constructs latches and acknowledge trees
Can expand to early output, DIMS or MVL
Creates RAM wrappers and wagging fork/join blocks
06/05/08
C
Pipeline Synthesis
LogicAsyncLogic Async
Latch
AsyncLatch
AsyncLatch
AsyncLatch
AsyncLatch
06/05/08 14
Processing 2
Pipeline Synthesis
Takes a directed flow graph (DFG) style circuit
Constructs latches and acknowledge trees
Can expand to early output, DIMS or MVL
Creates RAM wrappers and wagging fork/join blocks
06/05/08 15
Processing 3
Wagging
Duplicates circuit and reconnects latches to form a ring
Inserts abstract fork/join blocks Simulation
Fast simulator
Slowest trace extraction
MVL capable
Allows simulation at an abstract level
06/05/08 16
Processing 4
Tech mapping
Dumb generation of large primitives (balanced trees)
Table based re-synthesis of C-element blocks
Logic blocks in the future
Slowest trace based gate replacement (drive strength)
06/05/08 18
Timing extraction
VerilogRead
TLFRead
NetlistFlatten
TimingExtract
VerilogWrite
SDFWrite
06/05/08 19
Extract Slowest PathVerilogRead
TLFRead
NetlistFlatten
TimingExtract
SimulationSlowest Trace
Slowest PathWrite
06/05/08 20
Drive Strength OptimisationVerilogRead
TLFRead
NetlistFlatten
TimingExtract
SimulationSlowest Trace
Tech-mapFind Better Cell
NetlistReplace Element
VerilogWrite
06/05/08
Large C-element generationVerilogRead
TLFRead
Async TransC-element Gen
TimingExtract
Tech-mapFind Better Cell
VerilogWrite
TimingGenerate Splines
TLFWrite
06/05/08
Current state
Pre-alpha
Pretty unusable
Used to generate RedStar
Parts implemented when needed
About 6 months from public beta
Currently available on request
06/05/08
Future Work
Implement RedStar using system
Using as few commercial tools as possible
Example design
Complete system back-end components
Implement front-end
Scripting of operations
GUI
Benchmark suite
06/05/08
Biscotti Conclusions
Allows implementation of asynchronous designs
Without relying on commercial tools
Tools suited to asynchronous designs
Easy expansion
Allows rapid evaluation of researched techniques
Fairly compare to existing methods
Useful analysis techniques
Still incomplete