00 Cover & Contents

AM335x ARM Cortex-A8 Microprocessors(MPUs)

Technical Reference Manual

Literature Number: SPRUH73EOctober 2011Revised May 2012

Contents

Preface .................................................................................................................................... 1531 Introduction .................................................................................................................... 154

1.1 AM335x Family ........................................................................................................... 1541.1.1 Device Features ................................................................................................. 1541.1.2 Device Identification ............................................................................................ 1551.1.3 Feature Identification ........................................................................................... 156

2 Memory Map ................................................................................................................... 1582.1 ARM Cortex-A8 Memory Map .......................................................................................... 1582.2 ARM Cortex-M3 Memory Map ......................................................................................... 167

3 ARM MPU Subsystem ....................................................................................................... 1693.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 170

3.1.1 Features .......................................................................................................... 1713.1.2 MPU Subsystem Integration ................................................................................... 1713.1.3 MPU Subsystem Clock and Reset Distribution ............................................................. 1723.1.4 ARM Subchip .................................................................................................... 1753.1.5 Interrupt Controller .............................................................................................. 1763.1.6 Power Management ............................................................................................ 1763.1.7 ARM Programming Model ..................................................................................... 179

4 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) ............. 1814.1 Introduction ............................................................................................................... 182

5 Graphics Accelerator (SGX) .............................................................................................. 1835.1 Introduction ............................................................................................................... 184

5.1.1 POWERVR SGX Main Features .............................................................................. 1845.1.2 SGX 3D Features ............................................................................................... 1845.1.3 Universal Scalable Shader Engine (USSE) Key Features .............................................. 1855.1.4 Unsupported Features .......................................................................................... 186

5.2 Integration ................................................................................................................. 1875.2.1 SGX530 Connectivity Attributes ............................................................................... 1875.2.2 SGX530 Clock and Reset Management ..................................................................... 1875.2.3 SGX530 Pin List ................................................................................................. 188

5.3 Functional Description ................................................................................................... 1895.3.1 SGX Block Diagram ............................................................................................ 1895.3.2 SGX Elements Description .................................................................................... 189

6 Interrupts ........................................................................................................................ 1916.1 Functional Description ................................................................................................... 192

6.1.1 Interrupt Processing ............................................................................................ 1936.1.2 Register Protection ............................................................................................. 1946.1.3 Module Power Saving .......................................................................................... 1946.1.4 Error Handling ................................................................................................... 1946.1.5 Interrupt Handling ............................................................................................... 1946.1.6 Basic Programming Model ..................................................................................... 195

6.2 ARM Cortex-A8 Interrupts .............................................................................................. 2046.3 ARM Cortex-M3 Interrupts .............................................................................................. 2086.4 PWM Events .............................................................................................................. 210

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6.5 Interrupt Controller Registers ........................................................................................... 2116.5.1 INTC Registers .................................................................................................. 211

7 Memory Subsystem ......................................................................................................... 3867.1 GPMC ..................................................................................................................... 387

7.1.1 Introduction ...................................................................................................... 3877.1.2 Integration ........................................................................................................ 3907.1.3 Functional Description .......................................................................................... 3927.1.4 Use Cases ....................................................................................................... 4917.1.5 Registers ......................................................................................................... 502

7.2 OCMC-RAM .............................................................................................................. 5357.2.1 Introduction ...................................................................................................... 5357.2.2 Integration ........................................................................................................ 536

7.3 EMIF ....................................................................................................................... 5377.3.1 Introduction ...................................................................................................... 5377.3.2 Integration ........................................................................................................ 5397.3.3 Functional Description .......................................................................................... 5417.3.4 Use Cases ....................................................................................................... 5597.3.5 EMIF4D Registers .............................................................................................. 5597.3.6 DDR2/3/mDDR PHY Registers ............................................................................... 600

7.4 ELM ........................................................................................................................ 6097.4.1 Introduction ...................................................................................................... 6097.4.2 Integration ........................................................................................................ 6107.4.3 Functional Description .......................................................................................... 6117.4.4 Basic Programming Model ..................................................................................... 6147.4.5 ELM Registers ................................................................................................... 620

8 Power, Reset, and Clock Management (PRCM) .................................................................... 6328.1 Power, Reset, and Clock Management ............................................................................... 633

8.1.1 Introduction ...................................................................................................... 6338.1.2 Device Power-Management Architecture Building Blocks ................................................. 6338.1.3 Clock Management ............................................................................................. 6338.1.4 Power Management ............................................................................................ 6398.1.5 PRCM Module Overview ....................................................................................... 6478.1.6 Clock Generation and Management .......................................................................... 6488.1.7 Reset Management ............................................................................................. 6648.1.8 Power-Up/Down Sequence .................................................................................... 6738.1.9 IO State ........................................................................................................... 6738.1.10 Voltage and Power Domains ................................................................................. 6738.1.11 Device Modules and Power Management Attributes List ................................................. 6748.1.12 Clock Module Registers ....................................................................................... 6778.1.13 Power Management Registers ............................................................................... 834

9 Control Module ................................................................................................................ 8759.1 Introduction ............................................................................................................... 8769.2 Functional Description ................................................................................................... 876

9.2.1 Control Module Initialization ................................................................................... 8769.2.2 Pad Control Registers .......................................................................................... 8769.2.3 EDMA Event Multiplexing ...................................................................................... 8779.2.4 Device Control and Status ..................................................................................... 8789.2.5 DDR PHY ........................................................................................................ 884

9.3 CONTROL_MODULE Registers ....................................................................................... 8859.3.1 control_revision Register (offset = 0h) [reset = 0h] ......................................................... 8929.3.2 device_id Register (offset = 600h) [reset = 0x] ............................................................. 8939.3.3 control_hwinfo Register (offset = 4h) [reset = 0h] .......................................................... 8949.3.4 control_sysconfig Register (offset = 10h) [reset = 0h] ..................................................... 895

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9.3.5 control_status Register (offset = 40h) [reset = 0h] ......................................................... 8969.3.6 cortex_vbbldo_ctrl Register (offset = 41Ch) [reset = 0h] .................................................. 8979.3.7 core_sldo_ctrl Register (offset = 428h) [reset = 0h] ........................................................ 8989.3.8 mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h] ....................................................... 8999.3.9 clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h] ................................................... 9009.3.10 bandgap_ctrl Register (offset = 448h) [reset = 0h] ........................................................ 9019.3.11 bandgap_trim Register (offset = 44Ch) [reset = 0h] ....................................................... 9029.3.12 pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h] .................................................. 9039.3.13 mosc_ctrl Register (offset = 468h) [reset = 0h] ............................................................ 9049.3.14 rcosc_ctrl Register (offset = 46Ch) [reset = 0h] ............................................................ 9059.3.15 deepsleep_ctrl Register (offset = 470h) [reset = 0h] ...................................................... 9069.3.16 dev_feature Register (offset = 604h) [reset = 0h] ......................................................... 9079.3.17 init_priority_0 Register (offset = 608h) [reset = 0h] ........................................................ 9089.3.18 init_priority_1 Register (offset = 60Ch) [reset = 0h] ....................................................... 9099.3.19 mmu_cfg Register (offset = 610h) [reset = 0h] ............................................................. 9109.3.20 tptc_cfg Register (offset = 614h) [reset = 0h] .............................................................. 9119.3.21 usb_ctrl0 Register (offset = 620h) [reset = 0h] ............................................................. 9129.3.22 usb_sts0 Register (offset = 624h) [reset = 0h] ............................................................. 9149.3.23 usb_ctrl1 Register (offset = 628h) [reset = 0h] ............................................................. 9159.3.24 usb_sts1 Register (offset = 62Ch) [reset = 0h] ............................................................ 9179.3.25 mac_id0_lo Register (offset = 630h) [reset = 0h] .......................................................... 9189.3.26 mac_id0_hi Register (offset = 634h) [reset = 0h] .......................................................... 9199.3.27 mac_id1_lo Register (offset = 638h) [reset = 0h] .......................................................... 9209.3.28 mac_id1_hi Register (offset = 63Ch) [reset = 0h] ......................................................... 9219.3.29 dcan_raminit Register (offset = 644h) [reset = 0h] ........................................................ 9229.3.30 usb_wkup_ctrl Register (offset = 648h) [reset = 0h] ...................................................... 9239.3.31 gmii_sel Register (offset = 650h) [reset = 0h] .............................................................. 9249.3.32 pwmss_ctrl Register (offset = 664h) [reset = 0h] .......................................................... 9259.3.33 mreqprio_0 Register (offset = 670h) [reset = 0h] .......................................................... 9269.3.34 mreqprio_1 Register (offset = 674h) [reset = 0h] .......................................................... 9279.3.35 hw_event_sel_grp1 Register (offset = 690h) [reset = 0h] ................................................ 9289.3.36 hw_event_sel_grp2 Register (offset = 694h) [reset = 0h] ................................................ 9299.3.37 hw_event_sel_grp3 Register (offset = 698h) [reset = 0h] ................................................ 9309.3.38 hw_event_sel_grp4 Register (offset = 69Ch) [reset = 0h] ................................................ 9319.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h] ............................................................. 9329.3.40 mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h] ............................................ 9339.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h] ............................................... 9349.3.42 vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h] ................................................. 9359.3.43 vdd_mpu_opp_100 Register (offset = 774h) [reset = 0h] ................................................. 9369.3.44 vdd_mpu_opp_120 Register (offset = 778h) [reset = 0h] ................................................. 9379.3.45 vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h] .............................................. 9389.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h] ................................................ 9399.3.47 vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h] ................................................ 9409.3.48 bb_scale Register (offset = 7D0h) [reset = 0h] ............................................................ 9419.3.49 usb_vid_pid Register (offset = 7F4h) [reset = 4516141h] ................................................ 9429.3.50 conf__ Register (offset = 800h) ........................................................... 9439.3.51 cqdetect_status Register (offset = E00h) [reset = 0h] .................................................... 9449.3.52 ddr_io_ctrl Register (offset = E04h) [reset = 0h] ........................................................... 9459.3.53 vtp_ctrl Register (offset = E0Ch) [reset = 0h] .............................................................. 9469.3.54 vref_ctrl Register (offset = E14h) [reset = 0h] .............................................................. 9479.3.55 tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h] ................................................. 9489.3.56 tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h] ................................................. 9499.3.57 tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h] ............................................... 950



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9.3.58 tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h] ............................................. 9519.3.59 tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h] .............................................. 9529.3.60 tpcc_evt_mux_20_23 Register (offset = FA4h) [reset = 0h] .............................................. 9539.3.61 tpcc_evt_mux_24_27 Register (offset = FA8h) [reset = 0h] .............................................. 9549.3.62 tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h] ............................................. 9559.3.63 tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h] .............................................. 9569.3.64 tpcc_evt_mux_36_39 Register (offset = FB4h) [reset = 0h] .............................................. 9579.3.65 tpcc_evt_mux_40_43 Register (offset = FB8h) [reset = 0h] .............................................. 9589.3.66 tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h] ............................................. 9599.3.67 tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h] ............................................. 9609.3.68 tpcc_evt_mux_52_55 Register (offset = FC4h) [reset = 0h] ............................................. 9619.3.69 tpcc_evt_mux_56_59 Register (offset = FC8h) [reset = 0h] ............................................. 9629.3.70 tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h] ............................................. 9639.3.71 timer_evt_capt Register (offset = FD0h) [reset = 0h] ..................................................... 9649.3.72 ecap_evt_capt Register (offset = FD4h) [reset = 0h] ..................................................... 9659.3.73 adc_evt_capt Register (offset = FD8h) [reset = 0h] ....................................................... 9669.3.74 reset_iso Register (offset = 1000h) [reset = 0h] ........................................................... 9679.3.75 ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h] ....................................................... 9689.3.76 sma2 Register (offset = 1320h) [reset = 0h] ................................................................ 9699.3.77 m3_txev_eoi Register (offset = 1324h) [reset = 0h] ....................................................... 9709.3.78 ipc_msg_reg0 Register (offset = 1328h) [reset = 0h] ..................................................... 9719.3.79 ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h] ..................................................... 9729.3.80 ipc_msg_reg2 Register (offset = 1330h) [reset = 0h] ..................................................... 9739.3.81 ipc_msg_reg3 Register (offset = 1334h) [reset = 0h] ..................................................... 9749.3.82 ipc_msg_reg4 Register (offset = 1338h) [reset = 0h] ..................................................... 9759.3.83 ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h] ..................................................... 9769.3.84 ipc_msg_reg6 Register (offset = 1340h) [reset = 0h] ..................................................... 9779.3.85 ipc_msg_reg7 Register (offset = 1344h) [reset = 0h] ..................................................... 9789.3.86 ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h] ................................................... 9799.3.87 ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h] ................................................... 9819.3.88 ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h] .................................................. 9839.3.89 ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h] ................................................... 9859.3.90 ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h] ................................................... 987

10 Interconnects .................................................................................................................. 98910.1 Introduction ............................................................................................................... 990

10.1.1 Terminology ..................................................................................................... 99010.1.2 L3 Interconnect ................................................................................................. 99010.1.3 L4 Interconnect ................................................................................................. 993

11 Enhanced Direct Memory Access (EDMA) ........................................................................... 99511.1 Introduction ............................................................................................................... 996

11.1.1 EDMA3 Controller Block Diagram ........................................................................... 99611.1.2 Third-Party Channel Controller (TPCC) Overview ......................................................... 99611.1.3 Third-Party Transfer Controller (TPTC) Overview ......................................................... 997

11.2 Integration ................................................................................................................. 99911.2.1 Third-Party Channel Controller (TPCC) Integration ....................................................... 99911.2.2 Third-Party Transfer Controller (TPTC) Integration ...................................................... 1000

11.3 Functional Description ................................................................................................. 100211.3.1 Functional Overview ......................................................................................... 100211.3.2 Types of EDMA3 Transfers ................................................................................. 100511.3.3 Parameter RAM (PaRAM) ................................................................................... 100711.3.4 Initiating a DMA Transfer .................................................................................... 101911.3.5 Completion of a DMA Transfer ............................................................................. 102211.3.6 Event, Channel, and PaRAM Mapping .................................................................... 1023



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11.3.7 EDMA3 Channel Controller Regions ....................................................................... 102511.3.8 Chaining EDMA3 Channels ................................................................................. 102711.3.9 EDMA3 Interrupts ............................................................................................ 102811.3.10 Memory Protection .......................................................................................... 103411.3.11 Event Queue(s) ............................................................................................. 103811.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................ 104011.3.13 Event Dataflow .............................................................................................. 104311.3.14 EDMA3 Prioritization ....................................................................................... 104311.3.15 EDMA3 Operating Frequency (Clock Control) .......................................................... 104411.3.16 Reset Considerations ....................................................................................... 104411.3.17 Power Management ........................................................................................ 104411.3.18 Emulation Considerations .................................................................................. 104411.3.19 EDMA Transfer Examples ................................................................................. 104611.3.20 EDMA Events ................................................................................................ 1062

11.4 EDMA3 Registers ...................................................................................................... 106511.4.1 EDMA3 Channel Controller Registers ..................................................................... 106511.4.2 EDMA3 Transfer Controller Registers ..................................................................... 1119

11.5 Appendix A .............................................................................................................. 114311.5.1 Debug Checklist .............................................................................................. 114311.5.2 Miscellaneous Programming/Debug Tips ................................................................. 114411.5.3 Setting Up a Transfer ........................................................................................ 1145

12 Touchscreen Controller .................................................................................................. 114712.1 Introduction .............................................................................................................. 1148

12.1.1 TSC_ADC Features .......................................................................................... 114812.1.2 Unsupported TSC_ADC_SS Features .................................................................... 1148

12.2 Integration ............................................................................................................... 114912.2.1 TSC_ADC Connectivity Attributes .......................................................................... 114912.2.2 TSC_ADC Clock and Reset Management ................................................................ 115012.2.3 TSC_ADC Pin List ............................................................................................ 1150

12.3 Functional Description ................................................................................................. 115112.3.1 HW Synchronized or SW Channels ........................................................................ 115112.3.2 Open Delay and Sample Delay ............................................................................. 115112.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................ 115112.3.4 One-Shot (Single) or Continuous Mode ................................................................... 115112.3.5 Interrupts ...................................................................................................... 115112.3.6 DMA Requests ................................................................................................ 115112.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1152

12.4 Operational Modes ..................................................................................................... 115312.4.1 PenCtrl and PenIRQ ......................................................................................... 1154

12.5 Touchscreen Controller Registers .................................................................................... 115712.5.1 TSC_ADC_SS Registers .................................................................................... 1157

13 LCD Controller ............................................................................................................... 122113.1 Introduction .............................................................................................................. 1222

13.1.1 Purpose of the Peripheral ................................................................................... 122213.1.2 Features ....................................................................................................... 1223

13.2 Integration ............................................................................................................... 122413.2.1 LCD Controller Connectivity Attributes .................................................................... 122413.2.2 LCD Controller Clock and Reset Management ........................................................... 122513.2.3 LCD Controller Pin List ...................................................................................... 1225

13.3 Functional Description ................................................................................................. 122613.3.1 Clocking ........................................................................................................ 122613.3.2 LCD External I/O Signals .................................................................................... 122813.3.3 DMA Engine ................................................................................................... 1229



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13.3.4 LIDD Controller ............................................................................................... 123013.3.5 Raster Controller ............................................................................................. 123213.3.6 Interrupt Conditions .......................................................................................... 124313.3.7 DMA ............................................................................................................ 124513.3.8 Power Management .......................................................................................... 1245

13.4 Programming Model .................................................................................................... 124613.4.1 LCD Character Displays ..................................................................................... 124613.4.2 Active Matrix Displays ....................................................................................... 124913.4.3 System Interaction ........................................................................................... 124913.4.4 Palette Lookup ................................................................................................ 124913.4.5 Test Logic ..................................................................................................... 125113.4.6 Disable and Software Reset Sequence ................................................................... 125113.4.7 Precedence Order for Determining Frame Buffer Type ................................................. 1252

13.5 LCD Registers .......................................................................................................... 125213.5.1 PID Register (offset = 0h) [reset = 0h] ..................................................................... 125413.5.2 CTRL Register (offset = 4h) [reset = 0h] .................................................................. 125513.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h] .......................................................... 125613.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h] .................................................. 125713.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h] .................................................. 125813.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h] .................................................. 125913.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h] ................................................. 126013.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h] .................................................. 126113.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h] .................................................. 126213.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h] ................................................... 126313.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h] ............................................. 126613.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h] ............................................. 126713.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h] ............................................. 126813.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h] ........................................... 127013.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h] ......................................... 127113.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h] .................................................. 127213.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h] ............................................ 127413.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h] ........................................ 127513.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h] ........................................... 127613.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h] ........................................ 127713.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h] ...................................................... 127813.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h] ............................................... 128013.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h] ...................................................... 128213.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h] ................................................ 128413.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h] ............................................ 128613.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h] .................................................. 128813.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h] .................................................... 1289

14 Ethernet Subsystem ....................................................................................................... 129014.1 Introduction .............................................................................................................. 1291

14.1.1 Features ....................................................................................................... 129114.1.2 Unsupported Features ....................................................................................... 1292

14.2 Integration ............................................................................................................... 129314.2.1 Ethernet Switch Connectivity Attributes ................................................................... 129314.2.2 Ethernet Switch Clock and Reset Management .......................................................... 129514.2.3 Ethernet Switch Pin List ..................................................................................... 129614.2.4 Ethernet Switch RMII Clocking Details .................................................................... 129614.2.5 GMII Interface Signal Connections and Descriptions .................................................... 129714.2.6 RMII Signal Connections and Descriptions ............................................................... 130014.2.7 RGMII Signal Connections and Descriptions ............................................................. 1301



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14.3 Functional Description ................................................................................................. 130314.3.1 CPSW_3G Subsystem ....................................................................................... 130314.3.2 CPSW_3G ..................................................................................................... 130814.3.3 Ethernet Mac Sliver (CPGMAC_SL) ....................................................................... 135014.3.4 Command IDLE ............................................................................................... 135214.3.5 RMII Interface ................................................................................................. 135314.3.6 RGMII Interface ............................................................................................... 135314.3.7 Common Platform Time Sync (CPTS) ..................................................................... 135614.3.8 MDIO ........................................................................................................... 1361

14.4 Software Operation ..................................................................................................... 136314.4.1 Transmit Operation ........................................................................................... 136314.4.2 Receive Operation ........................................................................................... 136514.4.3 Initializing the MDIO Module ................................................................................ 136614.4.4 Writing Data to a PHY Register ............................................................................ 136614.4.5 Reading Data from a PHY Register ........................................................................ 136714.4.6 Initialization and Configuration of CPSW .................................................................. 1367

14.5 Ethernet Subsystem Registers ....................................................................................... 136814.5.1 CPSW_ALE Registers ....................................................................................... 136814.5.2 CPSW_CPDMA Registers .................................................................................. 138314.5.3 CPSW_CPTS Registers ..................................................................................... 143614.5.4 CPSW_STATS Registers ................................................................................... 144914.5.5 CPDMA_STATERAM Registers ............................................................................ 144914.5.6 CPSW_PORT Registers ..................................................................................... 148314.5.7 CPSW_SL Registers ......................................................................................... 153914.5.8 CPSW_SS Registers ........................................................................................ 155314.5.9 CPSW_WR Registers ........................................................................................ 156614.5.10 Management Data Input/Output (MDIO) Registers ..................................................... 1602

15 Pulse-Width Modulation Subsystem (PWMSS) ................................................................... 161315.1 Pulse-Width Modulation Subsystem (PWMSS) .................................................................... 1614

15.1.1 Introduction .................................................................................................... 161415.1.2 Integration ..................................................................................................... 161615.1.3 PWMSS Configuration Registers ........................................................................... 1618

15.2 Enhanced PWM (ePWM) Module .................................................................................... 162315.2.1 Introduction .................................................................................................... 162315.2.2 Functional Description ....................................................................................... 162715.2.3 Use Cases ..................................................................................................... 168615.2.4 Registers ...................................................................................................... 1710

15.3 Enhanced Capture (eCAP) Module .................................................................................. 173615.3.1 Introduction .................................................................................................... 173615.3.2 Functional Description ....................................................................................... 173715.3.3 Use Cases ..................................................................................................... 174715.3.4 Registers ...................................................................................................... 1763

15.4 Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 177515.4.1 Introduction .................................................................................................... 177515.4.2 Functional Description ....................................................................................... 177815.4.3 eQEP Registers .............................................................................................. 1796

16 Universal Serial Bus (USB) .............................................................................................. 181416.1 Introduction .............................................................................................................. 1815

16.1.1 Acronyms, Abbreviations, and Definitions ................................................................. 181516.1.2 Unsupported USB OTG and PHY Features .............................................................. 1817

16.2 Integration ............................................................................................................... 181816.2.1 USB Connectivity Attributes ................................................................................. 181816.2.2 USB Clock and Reset Management ....................................................................... 1819



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16.2.3 USB Pin List ................................................................................................... 181916.2.4 USB GPIO Details ............................................................................................ 181916.2.5 USB Unbonded PHY Pads .................................................................................. 1820

16.3 Functional Description ................................................................................................. 182116.3.1 VBUS Voltage Sourcing Control ............................................................................ 182116.3.2 Pull-up/Pull-Down Resistors ................................................................................ 182116.3.3 Role Assuming Method ...................................................................................... 182216.3.4 Clock, PLL, and PHY Initialization ......................................................................... 182216.3.5 Indexed and Non-Indexed Register Spaces .............................................................. 182316.3.6 Dynamic FIFO Sizing ........................................................................................ 182316.3.7 USB Controller Host and Peripheral Modes Operation .................................................. 182416.3.8 Protocol Description(s) ....................................................................................... 182516.3.9 Communications Port Programming Interface (CPPI) 4.1 DMA ....................................... 185816.3.10 USB 2.0 Test Modes ....................................................................................... 1883

16.4 Supported Use Cases ................................................................................................. 188416.5 USB Registers .......................................................................................................... 1885

16.5.1 USBSS Registers ............................................................................................. 188516.5.2 USB0_CTRL Registers ...................................................................................... 192816.5.3 USB1_CTRL Registers ...................................................................................... 197816.5.4 USB2PHY Registers ......................................................................................... 202616.5.5 CPPI_DMA Registers ........................................................................................ 205316.5.6 CPPI_DMA_SCHEDULER Registers ...................................................................... 220916.5.7 QUEUE_MGR Registers .................................................................................... 2274

17 Interprocessor Communication ........................................................................................ 342517.1 Mailbox ................................................................................................................... 3426

17.1.1 Introduction .................................................................................................... 342617.1.2 Integration ..................................................................................................... 342717.1.3 Functional Description ....................................................................................... 342817.1.4 Programming Guide .......................................................................................... 343217.1.5 MAILBOX Registers .......................................................................................... 3435

17.2 Spinlock .................................................................................................................. 349617.2.1 SPINLOCK Registers ........................................................................................ 3496

18 Multimedia Card (MMC) ................................................................................................... 353418.1 Introduction .............................................................................................................. 3535

18.1.1 MMCHS Features ............................................................................................ 353518.1.2 Unsupported MMCHS Features ............................................................................ 3535

18.2 Integration ............................................................................................................... 353618.2.1 MMCHS Connectivity Attributes ............................................................................ 353718.2.2 MMCHS Clock and Reset Management .................................................................. 353818.2.3 MMCHS Pin List .............................................................................................. 3538

18.3 Functional Description ................................................................................................. 354018.3.1 MMC/SD/SDIO Functional Modes ......................................................................... 354018.3.2 Resets ......................................................................................................... 354718.3.3 Power Management .......................................................................................... 354818.3.4 Interrupt Requests ............................................................................................ 355118.3.5 DMA Modes ................................................................................................... 355318.3.6 Mode Selection ............................................................................................... 355618.3.7 Buffer Management .......................................................................................... 355618.3.8 Transfer Process ............................................................................................. 355918.3.9 Transfer or Command Status and Error Reporting ...................................................... 356018.3.10 Auto Command 12 Timings ................................................................................ 356518.3.11 Transfer Stop ................................................................................................ 356718.3.12 Output Signals Generation ................................................................................ 3568



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18.3.13 Card Boot Mode Management ............................................................................ 357018.3.14 CE-ATA Command Completion Disable Management ................................................ 357118.3.15 Test Registers ............................................................................................... 357118.3.16 MMC/SD/SDIO Hardware Status Features .............................................................. 357218.3.17 Low-Level Programming Models .......................................................................... 3573

18.4 Multimedia Card Registers ............................................................................................ 357818.4.1 MMC/SD/SDIO Registers ................................................................................... 3578

19 Universal Asynchronous Receiver/Transmitter (UART) ....................................................... 362519.1 Introduction .............................................................................................................. 3626

19.1.1 UART Mode Features ........................................................................................ 362619.1.2 IrDA Mode Features ......................................................................................... 362619.1.3 CIR Mode Features .......................................................................................... 362619.1.4 Unsupported UART Features ............................................................................... 3626

19.2 Integration ............................................................................................................... 362819.2.1 UART Connectivity Attributes ............................................................................... 362819.2.2 UART Clock and Reset Management ..................................................................... 362919.2.3 UART Pin List ................................................................................................. 3631

19.3 Functional Description ................................................................................................. 363219.3.1 Block Diagram ................................................................................................ 363219.3.2 Clock Configuration .......................................................................................... 363319.3.3 Software Reset ............................................................................................... 363319.3.4 Power Management .......................................................................................... 363319.3.5 Interrupt Requests ............................................................................................ 363519.3.6 FIFO Management ........................................................................................... 363819.3.7 Mode Selection ............................................................................................... 364619.3.8 Protocol Formatting .......................................................................................... 3652

19.4 UART/IrDA/CIR Basic Programming Model ......................................................................... 367519.4.1 UART Programming Model ................................................................................. 367519.4.2 IrDA Programming Model ................................................................................... 3681

19.5 UART Registers ........................................................................................................ 368419.5.1 UART Registers .............................................................................................. 3684

20 Timers .......................................................................................................................... 372820.1 DMTimer ................................................................................................................. 3729

20.1.1 Introduction .................................................................................................... 372920.1.2 Integration ..................................................................................................... 373120.1.3 Functional Description ....................................................................................... 373320.1.4 Use Cases ..................................................................................................... 374220.1.5 TIMER Registers ............................................................................................. 3742

20.2 DMTimer 1ms ........................................................................................................... 376020.2.1 Introduction .................................................................................................... 376020.2.2 Integration ..................................................................................................... 376220.2.3 Functional Description ....................................................................................... 376420.2.4 Use Cases ..................................................................................................... 377220.2.5 DMTIMER_1MS Registers .................................................................................. 3772

20.3 RTC_SS ................................................................................................................. 379620.3.1 Introduction .................................................................................................... 379620.3.2 Integration ..................................................................................................... 379720.3.3 Functional Description ....................................................................................... 379820.3.4 Use Cases ..................................................................................................... 380620.3.5 RTC Registers ................................................................................................ 3806

20.4 WATCHDOG ............................................................................................................ 384420.4.1 Introduction .................................................................................................... 384420.4.2 Integration ..................................................................................................... 3845



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20.4.3 Functional Description ....................................................................................... 384620.4.4 Use Cases ..................................................................................................... 385320.4.5 Watchdog Timer Registers .................................................................................. 3854

21 I2C ................................................................................................................................ 386521.1 Introduction .............................................................................................................. 3866

21.1.1 I2C Features .................................................................................................. 386621.1.2 Unsupported I2C Features .................................................................................. 3866

21.2 Integration ............................................................................................................... 386721.2.1 I2C Connectivity Attributes .................................................................................. 386721.2.2 I2C Clock and Reset Management ........................................................................ 386821.2.3 I2C Pin List .................................................................................................... 3868

21.3 Functional Description ................................................................................................. 386921.3.1 Functional Block Diagram ................................................................................... 386921.3.2 I2C Master/Slave Contoller Signals ........................................................................ 386921.3.3 I2C Reset ...................................................................................................... 387021.3.4 Data Validity ................................................................................................... 387021.3.5 START & STOP Conditions ................................................................................. 387221.3.6 I2C Operation ................................................................................................. 387221.3.7 Arbitration ...................................................................................................... 387421.3.8 I2C Clock Generation and I2C Clock Synchronization .................................................. 387421.3.9 Prescaler (SCLK/ICLK) ...................................................................................... 387521.3.10 Noise Filter ................................................................................................... 387521.3.11 I2C Interrupts ................................................................................................ 387521.3.12 DMA Events ................................................................................................. 387621.3.13 Interrupt and DMA Events ................................................................................. 387621.3.14 FIFO Management .......................................................................................... 387621.3.15 How to Program I2C ........................................................................................ 3880

21.4 Registers ................................................................................................................. 388221.4.1 I2C Registers ................................................................................................. 3882

22 Multichannel Audio Serial Port (McASP) ........................................................................... 392522.1 Introduction .............................................................................................................. 3926

22.1.1 Purpose of the Peripheral ................................................................................... 392622.1.2 Features ....................................................................................................... 392622.1.3 Protocols Supported ......................................................................................... 392622.1.4 Unsupported McASP Features ............................................................................. 3927

22.2 Integration ............................................................................................................... 392822.2.1 McASP Connectivity Attributes ............................................................................. 392822.2.2 McASP Clock and Reset Management .................................................................... 392922.2.3 McASP Pin List ............................................................................................... 3929

22.3 Functional Description ................................................................................................. 393022.3.1 Overview ....................................................................................................... 393022.3.2 Functional Block Diagram ................................................................................... 393122.3.3 Industry Standard Compliance Statement ................................................................ 393422.3.4 Definition of Terms ........................................................................................... 393822.3.5 Clock and Frame Sync Generators ........................................................................ 394022.3.6 Signal Descriptions ........................................................................................... 394422.3.7 Pin Multiplexing ............................................................................................... 394422.3.8 Transfer Modes ............................................................................................... 394522.3.9 General Architecture ......................................................................................... 395222.3.10 Operation ..................................................................................................... 395622.3.11 Reset Considerations ....................................................................................... 397322.3.12 Setup and Initialization ..................................................................................... 397322.3.13 Interrupts ..................................................................................................... 3978



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22.3.14 EDMA Event Support ....................................................................................... 398022.3.15 Power Management ........................................................................................ 398222.3.16 Emulation Considerations .................................................................................. 3982

22.4 McASP Registers ....................................................................................................... 398322.4.1 McASP CFG Registers ...................................................................................... 398322.4.2 McASP Data Port Registers ................................................................................ 4036

23 Controller Area Network (CAN) ........................................................................................ 403723.1 Introduction .............................................................................................................. 4038

23.1.1 DCAN Features ............................................................................................... 403823.1.2 Unsupported DCAN Features ............................................................................... 4038

23.2 Integration ............................................................................................................... 403923.2.1 DCAN Connectivity Attributes ............................................................................... 403923.2.2 DCAN Clock and Reset Management ..................................................................... 404023.2.3 DCAN Pin List ................................................................................................. 4040

23.3 Functional Description ................................................................................................. 404123.3.1 CAN Core ...................................................................................................... 404123.3.2 Message Handler ............................................................................................. 404223.3.3 Message RAM ................................................................................................ 404223.3.4 Message RAM Interface ..................................................................................... 404223.3.5 Registers and Message Object Access ................................................................... 404223.3.6 Module Interface .............................................................................................. 404223.3.7 Dual Clock Source ........................................................................................... 404223.3.8 CAN Operation ................................................................................................ 404323.3.9 Dual Clock Source ........................................................................................... 404923.3.10 Interrupt Functionality ...................................................................................... 405023.3.11 Local Power-Down Mode .................................................................................. 405223.3.12 Parity Check Mechanism .................................................................................. 405423.3.13 Debug/Suspend Mode ..................................................................................... 405523.3.14 Configuration of Message Objects ........................................................................ 405523.3.15 Message Handling .......................................................................................... 405823.3.16 CAN Bit Timing .............................................................................................. 406323.3.17 Message Interface Register Sets ......................................................................... 407123.3.18 Message RAM ............................................................................................... 407323.3.19 GIO Support ................................................................................................. 4078

23.4 DCAN Registers ........................................................................................................ 407923.4.1 DCAN Control Registers ..................................................................................... 4079

24 Multichannel Serial Port Interface (McSPI) ......................................................................... 412024.1 Introduction .............................................................................................................. 4121

24.1.1 McSPI Features .............................................................................................. 412124.1.2 Unsupported McSPI Features .............................................................................. 4121

24.2 Integration ............................................................................................................... 412124.2.1 McSPI Connectivity Attributes .............................................................................. 412324.2.2 McSPI Clock and Reset Management ..................................................................... 412324.2.3 McSPI Pin List ................................................................................................ 4123

24.3 Functional Description ................................................................................................. 412424.3.1 SPI Transmission ............................................................................................. 412424.3.2 Master Mode .................................................................................................. 413124.3.3 Slave Mode .................................................................................................... 414924.3.4 Interrupts ...................................................................................................... 415324.3.5 DMA Requests ................................................................................................ 415424.3.6 Emulation Mode .............................................................................................. 415524.3.7 Power Saving Management ................................................................................. 415624.3.8 System Test Mode ........................................................................................... 4157



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24.3.9 Reset ........................................................................................................... 415724.3.10 Access to Data Registers .................................................................................. 415824.3.11 Programming Aid ........................................................................................... 415824.3.12 Interrupt and DMA Events ................................................................................. 4159

24.4 Use Cases ............................................................................................................... 415924.5 McSPI Registers ........................................................................................................ 4159

24.5.1 SPI Registers ................................................................................................. 416025 General-Purpose Input/Output ......................................................................................... 4183

25.1 Introduction .............................................................................................................. 418425.1.1 Purpose of the Peripheral ................................................................................... 418425.1.2 GPIO Features ................................................................................................ 418425.1.3 Unsupported GPIO Features ............................................................................... 4184

25.2 Integration ............................................................................................................... 418525.2.1 GPIO Connectivity Attributes ............................................................................... 418525.2.2 GPIO Clock and Reset Management ...................................................................... 418625.2.3 GPIO Pin List ................................................................................................. 4187

25.3 Functional Description ................................................................................................. 418825.3.1 Operating Modes ............................................................................................. 418825.3.2 Clocking and Reset Strategy ................................................................................ 418825.3.3 Interrupt Features ............................................................................................ 418925.3.4 General-Purpose Interface Basic Programming Model ................................................. 4191

25.4 GPIO Registers ......................................................................................................... 419425.4.1 GPIO Registers ............................................................................................... 4194

26 Initialization ................................................................................................................... 421926.1 Functional Description ................................................................................................. 4220

26.1.1 Architecture ................................................................................................... 422026.1.2 Functionality ................................................................................................... 422026.1.3 Memory Map .................................................................................................. 422126.1.4 Start-up and Configuration .................................................................................. 422526.1.5 Booting ......................................................................................................... 422726.1.6 Fast External Booting ........................................................................................ 423626.1.7 Memory Booting .............................................................................................. 423826.1.8 Peripheral Booting ............................................................................................ 426526.1.9 Image Format ................................................................................................. 427026.1.10 Code Execution ............................................................................................ 427126.1.11 Wakeup ...................................................................................................... 427226.1.12 Tracing ....................................................................................................... 4273

A Revision History ............................................................................................................ 4277



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List of Figures3-1. Microprocessor Unit (MPU) Subsystem............................................................................... 1703-2. Microprocessor Unit (MPU) Subsystem Signal Interface ........................................................... 1723-3. MPU Subsystem Clocking Scheme ................................................................................... 1733-4. Reset Scheme of the MPU Subsystem ............................................................................... 1743-5. MPU Subsystem Power Domain Overview........................................................................... 1775-1. SGX530 Integration...................................................................................................... 1875-2. SGX Block Diagram ..................................................................................................... 1896-1. Interrupt Controller Block Diagram .................................................................................... 1926-2. IRQ/FIQ Processing Sequence ........................................................................................ 1986-3. Nested IRQ/FIQ Processing Sequence .............................................................................. 2026-4. INTC_REVISION Register .............................................................................................. 2156-5. INTC_SYSCONFIG Register ........................................................................................... 2166-6. INTC_SYSSTATUS Register........................................................................................... 2176-7. INTC_SIR_IRQ Register ................................................................................................ 2186-8. INTC_SIR_FIQ Register ................................................................................................ 2196-9. INTC_CONTROL Register.............................................................................................. 2206-10. INTC_PROTECTION Register ......................................................................................... 2216-11. INTC_IDLE Register ..................................................................................................... 2226-12. INTC_IRQ_PRIORITY Register........................................................................................ 2236-13. INTC_FIQ_PRIORITY Register ........................................................................................ 2246-14. INTC_THRESHOLD Register .......................................................................................... 2256-15. INTC_ITR0 Register ..................................................................................................... 2266-16. INTC_MIR0 Register .................................................................................................... 2276-17. INTC_MIR_CLEAR0 Register .......................................................................................... 2286-18. INTC_MIR_SET0 Register.............................................................................................. 2296-19. INTC_ISR_SET0 Register .............................................................................................. 2306-20. INTC_ISR_CLEAR0 Register .......................................................................................... 2316-21. INTC_PENDING_IRQ0 Register....................................................................................... 2326-22. INTC_PENDING_FIQ0 Register ....................................................................................... 2336-23. INTC_ITR1 Register ..................................................................................................... 2346-24. INTC_MIR1 Register .................................................................................................... 2356-25. INTC_MIR_CLEAR1 Register .......................................................................................... 2366-26. INTC_MIR_SET1 Register.............................................................................................. 2376-27. INTC_ISR_SET1 Register .............................................................................................. 2386-28. INTC_ISR_CLEAR1 Register .......................................................................................... 2396-29. INTC_PENDING_IRQ1 Register....................................................................................... 2406-30. INTC_PENDING_FIQ1 Register ....................................................................................... 2416-31. INTC_ITR2 Register ..................................................................................................... 2426-32. INTC_MIR2 Register .................................................................................................... 2436-33. INTC_MIR_CLEAR2 Register .......................................................................................... 2446-34. INTC_MIR_SET2 Register.............................................................................................. 2456-35. INTC_ISR_SET2 Register .............................................................................................. 2466-36. INTC_ISR_CLEAR2 Register .......................................................................................... 2476-37. INTC_PENDING_IRQ2 Register....................................................................................... 2486-38. INTC_PENDING_FIQ2 Register ....................................................................................... 2496-39. INTC_ITR3 Register ..................................................................................................... 2506-40. INTC_MIR3 Register .................................................................................................... 251

14 List of Figures SPRUH73EOctober 2011Revised May 2012Submit Documentation Feedback


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6-41. INTC_MIR_CLEAR3 Register .......................................................................................... 2526-42. INTC_MIR_SET3 Register.............................................................................................. 2536-43. INTC_ISR_SET3 Register .............................................................................................. 2546-44. INTC_ISR_CLEAR3 Register .......................................................................................... 2556-45. INTC_PENDING_IRQ3 Register....................................................................................... 2566-46. INTC_PENDING_FIQ3 Register ....................................................................................... 2576-47. INTC_ILR0 Register ..................................................................................................... 2586-48. INTC_ILR1 Register ..................................................................................................... 2596-49. INTC_ILR2 Register ..................................................................................................... 2606-50. INTC_ILR3 Register ..................................................................................................... 2616-51. INTC_ILR4 Register ..................................................................................................... 2626-52. INTC_ILR5 Register ..................................................................................................... 2636-53. INTC_ILR6 Register ..................................................................................................... 2646-54. INTC_ILR7 Register ..................................................................................................... 2656-55. INTC_ILR8 Register ..................................................................................................... 2666-56. INTC_ILR9 Register ..................................................................................................... 2676-57. INTC_ILR10 Register.................................................................................................... 2686-58. INTC_ILR11 Register.................................................................................................... 2696-59. INTC_ILR12 Register.................................................................................................... 2706-60. INTC_ILR13 Register.................................................................................................... 2716-61. INTC_ILR14 Register.................................................................................................... 2726-62. INTC_ILR15 Register.................................................................................................... 2736-63. INTC_ILR16 Register.................................................................................................... 2746-64. INTC_ILR17 Register.................................................................................................... 2756-65. INTC_ILR18 Register.................................................................................................... 2766-66. INTC_ILR19 Register.................................................................................................... 2776-67. INTC_ILR20 Register.................................................................................................... 2786-68. INTC_ILR21 Register.................................................................................................... 2796-69. INTC_ILR22 Register.................................................................................................... 2806-70. INTC_ILR23 Register.................................................................................................... 2816-71. INTC_ILR24 Register.................................................................................................... 2826-72. INTC_ILR25 Register.................................................................................................... 2836-73. INTC_ILR26 Register.................................................................................................... 2846-74. INTC_ILR27 Register.................................................................................................... 2856-75. INTC_ILR28 Register.................................................................................................... 2866-76. INTC_ILR29 Register.................................................................................................... 2876-77. INTC_ILR30 Register.................................................................................................... 2886-78. INTC_ILR31 Register.................................................................................................... 2896-79. INTC_ILR32 Register.................................................................................................... 2906-80. INTC_ILR33 Register.................................................................................................... 2916-81. INTC_ILR34 Register.................................................................................................... 2926-82. INTC_ILR35 Register.................................................................................................... 2936-83. INTC_ILR36 Register.................................................................................................... 2946-84. INTC_ILR37 Register.................................................................................................... 2956-85. INTC_ILR38 Register.................................................................................................... 2966-86. INTC_ILR39 Register.................................................................................................... 2976-87. INTC_ILR40 Register.................................................................................................... 2986-88. INTC_ILR41 Register.................................................................................................... 2996-89. INTC_ILR42 Register.................................................................................................... 300

15SPRUH73EOctober 2011Revised May 2012 List of FiguresSubmit Documentation Feedback


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6-90. INTC_ILR43 Register.................................................................................................... 3016-91. INTC_ILR44 Register.................................................................................................... 3026-92. INTC_ILR45 Register.................................................................................................... 3036-93. INTC_ILR46 Reg

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