© Digital Integrated Circuits 2nd Interconnect Digital Integrated Circuits A Design Perspective...

© Digital Integrated Circuits2nd Interconnect

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Coping withCoping withInterconnectInterconnect

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

Revised from Digital Integrated Circuits, © Jan M. Rabaey


Impact of Interconnect ParasiticsImpact of Interconnect Parasitics

• Reduce Robustness

• Affect Performance• Increase delay• Increase power dissipation

Classes of Parasitics

• Capacitive

• Resistive

• Inductive


INTERCONNECTINTERCONNECT


Capacitive Cross TalkCapacitive Cross Talk

X

YVX

CXY

CY


Capacitive Cross TalkCapacitive Cross TalkDynamic NodeDynamic Node

3 x 1 m overlap: 0.19 V disturbance

CY

CXY

VDD

PDN

CLK

CLK

In1

In2

In3

Y

X

2.5 V

0 V

A non-related signal Y is routed in Metal 1 wire over the polysilicon gate of the inverter gate.

Assume that CY=6fF and CXY= (3*1*0.057+

2*3*0.054)=0.5fF

Combined with charge redistribution and clock-feed through effects, this might cause circuit failure.


Wiring Capacitances (0.25Wiring Capacitances (0.25m CMOS)m CMOS)Rows represent the top plate, columns the bottom plate. Shaded row for fringing capacitance in aF/µm, unshaded for parallel plate capacitance (area capacitance) in aF/µm^2

smaller

40

95

85

85

85

115


Capacitive Cross Talk: Driven NodeCapacitive Cross Talk: Driven Node

XY = RY(CXY+CY)

If the rise time is comparable or larger than the time constant,the peak value of disturbance is diminished. So we need toKeep time-constant smaller than rise time, that is to decrease eithercapacitance or resistance (keeper transistor in dynamic design).

0

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

010.80.6

t (nsec)

0.40.2

X

YVX

RYCXY

CY

tr↑


Dealing with Capacitive Cross Dealing with Capacitive Cross TalkTalk Avoid floating nodes

Protect sensitive nodes

Make rise and fall times as large as possible (*?)

Do not run wires together for a long distance

Use shielding wires

Use shielding layers


ShieldingShielding

GND

GND

Shieldingwire

Substrate (GND )

Shieldinglayer

VDD

Interleave every signal layer with a GND or VDD metal plane


Cross Talk and PerformanceCross Talk and Performance

Cc

- When neighboring lines switch in opposite direction of victim line, delay increases

DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES

- Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0), Miller EffectMiller Effect

- Effective voltage is doubled and additional charge is needed (from Q=CV)


Impact of Cross Talk on Delay Impact of Cross Talk on Delay

r is ratio between capacitance to neighbor and to GND

Activity on bus of different bits


Encoding Data Avoids Worst-CaseEncoding Data Avoids Worst-CaseConditionsConditions

Encoder

Decoder

Bus

In

Out

It is possible to encode the data in such a way that the transitions that “victimize” delay are eliminated. This requires that the bus interface units include encode/decoder functions.


Structured Predictable InterconnectStructured Predictable Interconnect

S

S SV V S

G

S

SV

G

VS

S SV V S

G

S

SV

G

V

Example: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitance Also widely used in FPGAs

V: VDD S: signal G: GND


Interconnect ProjectionsInterconnect ProjectionsLow-k dielectricsLow-k dielectrics

Both delay and power are reduced by dropping interconnect capacitance

Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k)

The numbers below are on the conservative side of the NRTS roadmap


Driving Large CapacitancesDriving Large Capacitances

V in Vout

CL

VDD

• Transistor Sizing• Cascaded Buffers


Using Cascaded BuffersUsing Cascaded Buffers

CL = 20 pF

In Out

1 2 N

0.25 m processCin = 2.5 fFtp0 = 30 ps

F = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns

(See Chapter 5)


Delay as a Function of F and NDelay as a Function of F and N

101 3 5 7

Number of buffer stages N

9 11

10,000

1000

100

F = 100F = 1000

F = 10,000t p

/tp

0


Output Driver DesignOutput Driver Design

Trade off Performance for Area and Energy

Given tpmax find N and f Area Energy

minminmin12

1

1

1

1...1 A

f

FA

f

fAfffA

NN

driver

22212

11

1...1 DD

LDDiDDi

Ndriver V

f

CVC

f

FVCfffE

To a first order analysis, this simply says that small sizing factor f causes large area and power consumption!!!


Output Driver Design: design for right Output Driver Design: design for right speedspeed

Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns

Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns

0.25 m process, CL = 20 pF

Overall area of the later solution is 7 times smaller compared to the first one, while delay is increased by a factor of 2. Also, overall power dissipation of the load and buffer is reduced by 24%.

fopt = 3.6

fd = 20


How to Design Large TransistorsHow to Design Large Transistors

G(ate)

S(ource)

D(rain)

Multiple

Contacts

small transistors in parallel

Reduces diffusion capacitanceReduces gate resistance


Bonding Pad DesignBonding Pad DesignBonding Pad

Out

InVDD GND

100 m

GND

Out

Guard ring


Guard ringGuard ring Guard rings are grounded p+ diffusions in a p-well and supply-connected n+ diffusions in an n-well that are used to collect injected minority carriers before they reach the base of the parasitic bipolar transistors.

They should be used surrounding the NMOS/PMOS transistors in the final stage of the output pad driver.

Used a lot in analog VLSI design.


Chip PackagingChip Packaging

ChipL

L ´

Bonding wire

Mountingcavity

Leadframe

Pin

•Bond wires (~25m) are used to connect the package to the chip

• Pads are arranged in a frame around the chip

• Pads are relatively large (~100m in 0.25m technology)

•Many chips areas are ‘pad limited’


Pad FramePad Frame

Layout Die Photo


Tristate BuffersTristate Buffers Most of the driver circuits have been simple inverters.

Tristate buffers is a variant. Suppose that one device is sending information on the bus, all other transmitting devices should be disconnected from the bus. This can be achieved by putting the output buffers of those devices in an high-impedance state Z that effectively disconnects the gate from the output wire.


Tristate BuffersTristate Buffers

InEn

En

VDD

Out

Out = In.En + Z.En

VDD

In

En

En

Out

Increased output drive


INTERCONNECTINTERCONNECT


Impact of ResistanceImpact of Resistance Impact of resistance is commonly seen

in power supply distribution: IR drop Voltage variations Delay increases

Power supply is distributed to minimize the IR drop and the change in current due to switching of gates


IR Introduced NoiseIR Introduced Noise

M1

X

I

R9

RΔV

f pre

ΔV

VDD

VDD - ΔV

I

Ohmic voltage drop on the supply rails reduces the noise margins

A 2cm long, 1 µm wide Vdd or Gnd wire with 1mA current and sheet resistance of 0.05 Ohm/□ gives a voltage drop of 1V.


Power DistributionPower Distribution Low-level distribution is in Metal 1

Power is ‘strapped’ in higher layers of metal.

The spacing is set by IR drop, electromigration, inductive effects

Always use multiple contacts on straps


Power and Ground DistributionPower and Ground Distribution

GND

VDD

Logic

GND

VDD

Logic

GND

VDD

(a) Finger-shaped network (b) Network with multiple supply pins


3 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “thick” metal layer added to the

technology for EV4 designPower supplied from two sides of the die via 3rd metal layer

2nd metal layer used to form power grid

90% of 3rd metal layer used for power/clock routing

Metal 3

Metal 2

Metal 1

Courtesy Compaq


4 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “thick” metal layer added to the

technology for EV5 designPower supplied from four sides of the die

Grid strapping done all in metal

90% of 3rd and 4th metals used for power/clock routing

Metal 3

Metal 2

Metal 1

Metal 4

Courtesy Compaq


2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss

Significantly lowers resistance of gridLowers on-chip inductance

6 Metal Layer Approach – EV66 Metal Layer Approach – EV6

Metal 4

Metal 2Metal 1

RP2/Vdd

RP1/Vss

Metal 3

Courtesy Compaq

© Digital Integrated Circuits2nd Interconnect19

ASP DAC 2000

Power Dissipation TrendsPower Dissipation Trends

Power consumption is increasingPower consumption is increasing Better cooling technology neededBetter cooling technology needed

Supply current is increasing faster!Supply current is increasing faster!

OnOn--chip signal integrity will be a major chip signal integrity will be a major issueissue

Power and current distribution are criticalPower and current distribution are critical

Opportunities to slow power growthOpportunities to slow power growth Accelerate Accelerate VddVdd scalingscaling

Low Low κκ dielectrics & thinner (Cu) dielectrics & thinner (Cu) interconnectinterconnect

SOI circuit innovations SOI circuit innovations

Clock system designClock system design

micromicro--architecturearchitecture

Power Dissipation

020406080

100120140160

EV4 EV5 EV6 EV7 EV8

Po

we

r (W

)

0

0.5

1

1.5

2

2.5

3

3.5

Vol

tage

(V

)

Supply Current

0

20

40

60

80

100

120

140

EV4 EV5 EV6 EV7 EV8

Curr

ent (

A)

0

0.5

1

1.5

2

2.5

3

3.5

Vo

ltag

e (

V)


Resistance and the Power Resistance and the Power Distribution Problem: sizingDistribution Problem: sizing

Source: Cadence

• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction• Heavily influenced by packaging technologyHeavily influenced by packaging technology

BeforeBefore AfterAfter


Electromigration (1)Electromigration (1)

Limits dc-current to 1 mA/m

The current density in a metal wire is limited due to an effect called electromigration, which eventually causes the wire to break or to short-circuit to another wire.

Line open failure


Electromigration (2)Electromigration (2)

Open failure in contact

Average current density and temperature are two main factors


Resistivity and PerformanceResistivity and Performance

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

volta

ge

(V

)

x= L/10

x = L/4

x = L/2

x= L

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

volta

ge

(V

)

x= L/10

x = L/4

x = L/2

x= L

Diffused signal Diffused signal propagationpropagation

Delay ~ LDelay ~ L22

CN-1 CNC2

R1 R2

C1

Tr

Vin

RN-1 RN

The distributed rc-lineThe distributed rc-line


Driving an RC-lineDriving an RC-line

Vi n

Rs Vo ut

(rw,cw,L)


The Global Wire ProblemThe Global Wire ProblemChallenges No further improvements to be expected after the

introduction of Copper (superconducting, optical?)

Design solutions Use of fat wires Insert repeaters — but might become prohibitive (power,

area) Efficient chip floorplanning

Towards “communication-based” design How to deal with latency? Is synchronicity an absolute necessity?


Interconnect Projections: CopperInterconnect Projections: Copper Copper is planned in full sub-0.25

m process flows and large-scale designs (IBM, Motorola, IEDM97)

Cu ~ 2.2 -cm vs. 3.5 for Al(Cu) 40% reduction in resistance

Electromigration improvement; 100X longer lifetime (IBM, IEDM97) Electromigration is a limiting factor

beyond 0.18 m if Al is used (HP, IEDM95)

Vias


Interconnect:Interconnect:# of Wiring Layers# of Wiring Layers

# of metal layers is steadily increasing due to:

• Increasing die size and device count: we need more wires and longer wires to connect everything

• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC

substrate

poly

M1

M2

M3

M4

M5

M6

Tins

H

WS

= 2.2 -cm

0.25 m wiring stack

Minimum Widths (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

M5

M4

M3

M2

M1

Poly

Minimum Spacing (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

M5

M4

M3

M2

M1

Poly


Diagonal WiringDiagonal Wiring

y

x

destination

Manhattan

source

diagonal

• 20+% Interconnect length reduction• Clock speed Signal integrity Power integrity • 15+% Smaller chips plus 30+% via reduction

Courtesy Cadence X-initiative

The main problem is that incorporating diagonal design in Design Automation tools is harder


Reducing RC-delayReducing RC-delay

Repeater

Optimal number of wire segments for a long wire!

Lcrit=L / M

AS inverter chain, the optimum is achieved when the delay of each wire segment is equal to that of a repeater!


Wire pipeliningWire pipelining

Reg-

ister

Reg-

ister

Reg-

ister

clk

• Even with repeater, wire delay may still be larger than the clock cycle

• To accommodate this delay with GHz clock, wire pipelining techniques can be used


Delay in Transmission Gate NetworksDelay in Transmission Gate NetworksV 1 V i-1

C

2.5 2.5

0 0

V i V i+1

CC

2.5

0

V n-1 V n

CC

2.5

0

In

V 1 V i V i+1

C

V n-1 V n

CC

In

R eqR eq R eq R eq

CC

(a)

(b)

C

R eq R eq

C C

R eq

C C

R eq R eq

C C

R eq

C

In

m

(c)


Delay OptimizationDelay Optimization


Resistivity and PerformanceResistivity and Performance The signal delay in interconnect has been dominated by RC if the signal frequency is not too high.

In modern design, average length of global wires has been increasing.

At the same time, the average delay of individual gate goes down (since parasitics reduces).

This leads to a strange situation that it may take multiple clock cycles to transport a global signal to long distance.

Accurate synchronization becomes a big challenge (the timing issues we discussed before).

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