. Arquivos Data Sheets PIC18F4550 PIC18F4550 Datasheet

8/3/2019 . Arquivos Data Sheets PIC18F4550 PIC18F4550 Datasheet

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28/40/44-Pin, High-Performance,Enhanced Flash, USB Microcontrollerswith nanoWatt Technology

2009 Microchip Technology Inc. DS39632E


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Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.Microchip is willing to work with the customer who is concerned about the integr

ity of their code.Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as unbreakable.Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchips code protection feature may be a violationof the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely at

the buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,rfPIC and UNI/O are registered trademarks of MicrochipTechnology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,MXDEV, MXLAB, SEEVAL and The Embedded Control


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Solutions Company are registered trademarks of MicrochipTechnology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,ECONOMONITOR, FanSense, HI-TIDE, In-Circuit SerialProgramming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient CodeGeneration, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, TotalEndurance, TSHARC, UniWinDriver, WiperLock and ZENAare trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporatedin the U.S.A.All other trademarks mentioned herein are property of their

respective companies.

2009, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Companys quality system processes and proceduresare for its PIC MCUs and dsPIC DSCs, KEELOQ code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchips quality system for the designand manufacture of development systems is ISO 9001:2000 certified.

DS39632E-page ii2009 Microchip Technology Inc.


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0

28/40/44-Pin, High-Performance, Enhanced Flash,USB Microcontrollers with nanoWatt Technology

Universal Serial Bus Features:

USB V2.0 Compliant Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) Supports Control, Interrupt, Isochronous and BulkTransfers Supports up to 32 Endpoints (16 bidirectional) 1 Kbyte Dual Access RAM for USB On-Chip USB Transceiver with On-Chip VoltageRegulator Interface for Off-Chip USB Transceiver

Streaming Parallel Port (SPP) for USB streamingtransfers (40/44-pin devices only)Power-Managed Modes:

Run: CPU on, Peripherals on Idle: CPU off, Peripherals on Sleep: CPU off, Peripherals off Idle mode Currents Down to 5.8 A Typical Sleep mode Currents Down to 0.1 A Typical Timer1 Oscillator: 1.1 A Typical, 32 kHz, 2V Watchdog Timer: 2.1 A Typical Two-Speed Oscillator Start-upFlexible Oscillator Structure:

Four Crystal modes, including High-Precision PLLfor USB Two External Clock modes, Up to 48 MHz Internal Oscillator Block:-8 user-selectable frequencies, from 31 kHzto 8 MHz-User-tunable to compensate for frequency drift

Secondary Oscillator using Timer1 @ 32 kHz Dual Oscillator Options allow Microcontroller andUSB module to Run at Different Clock Speeds

Fail-Safe Clock Monitor:-Allows for safe shutdown if any clock stopsPeripheral Highlights:

High-Current Sink/Source: 25 mA/25 mA Three External Interrupts Four Timer modules (Timer0 to Timer3) Up to 2 Capture/Compare/PWM (CCP) modules:-Capture is 16-bit, max. resolution 5.2 ns (TCY/16)-Compare is 16-bit, max. resolution 83.3 ns (TCY)-PWM output: PWM resolution is 1 to 10-bit Enhanced Capture/Compare/PWM (ECCP) module:-Multiple output modes

-Selectable polarity-Programmable dead time-Auto-shutdown and auto-restart


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Enhanced USART module:-LIN bus support Master Synchronous Serial Port (MSSP) moduleSupporting 3-Wire SPI (all 4 modes) and I2CMaster and Slave modes 10-Bit, Up to 13-Channel Analog-to-Digital Converter(A/D) module with Programmable Acquisition Time

Dual Analog Comparators with Input MultiplexingSpecial Microcontroller Features:

C Compiler Optimized Architecture with OptionalExtended Instruction Set 100,000 Erase/Write Cycle Enhanced FlashProgram Memory Typical 1,000,000 Erase/Write Cycle Data EEPROMMemory Typical Flash/Data EEPROM Retention: > 40 Years Self-Programmable under Software Control Priority Levels for Interrupts

8 x 8 Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT):-Programmable period from 41 ms to 131s Programmable Code Protection Single-Supply 5V In-Circuit SerialProgramming (ICSP) via Two Pins In-Circuit Debug (ICD) via Two Pins Optional Dedicated ICD/ICSP Port (44-pin, TQFPpackage only) Wide Operating Voltage Range (2.0V to 5.5V)DeviceProgram Memory Data MemoryI/O 10-Bit

A/D (ch)CCP/ECCP(PWM) SPPMSSPEUSARTComparatorsTimers8/16-Bit Flash(bytes)# Single-WordInstructionsSRAM(bytes)EEPROM

(bytes) SPI MasterI2CPIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3

2009 Microchip Technology Inc. DS39632E-page 1


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PIC18F2455/2550/4455/4550

Pin Diagrams

40-Pin PDIP

PIC18F245528-Pin PDIP, SOICPIC18F255010112345618

79121314 151617181920232425

2627282221MCLR/VPP/RE3RA0/AN0RA1/AN1RA2/AN2/VREF-/CVREFRA3/AN3/VREF+RA4/T0CKI/C1OUT/RCVRA5/AN4/SS/HLVDIN/C2OUT

VSSOSC1/CLKIOSC2/CLKO/RA6RC0/T1OSO/T13CKIRC1/T1OSI/CCP2(1)/UOERC2/CCP1VUSBRB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/AN11/KBI0RB3/AN9/CCP2(1)/VPORB2/AN8/INT2/VMO

RB1/AN10/INT1/SCK/SCLRB0/AN12/INT0/FLT0/SDI/SDAVDD


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VSSRC7/RX/DT/SDORC6/TX/CKRC5/D+/VPRC4/D-/VMRB7/KBI3/PGDRB6/KBI2/PGC

RB5/KBI1/PGMRB4/AN11/KBI0/CSSPPRB3/AN9/CCP2(1)/VPORB2/AN8/INT2/VMORB1/AN10/INT1/SCK/SCLRB0/AN12/INT0/FLT0/SDI/SDAVDDVSSRD7/SPP7/P1DRD6/SPP6/P1CRD5/SPP5/P1BRD4/SPP4

RC7/RX/DT/SDORC6/TX/CKRC5/D+/VPRC4/D-/VMRD3/SPP3RD2/SPP2MCLR/VPP/RE3RA0/AN0RA1/AN1RA2/AN2/VREF-/CVREFRA3/AN3/VREF+RA4/T0CKI/C1OUT/RCVRA5/AN4/SS/HLVDIN/C2OUT

RE0/AN5/CK1SPPRE1/AN6/CK2SPPRE2/AN7/OESPPVDDVSSOSC1/CLKIOSC2/CLKO/RA6RC0/T1OSO/T13CKIRC1/T1OSI/CCP2(1)/UOERC2/CCP1/P1AVUSBRD0/SPP0

RD1/SPP1123456789101112

131415


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16171819204039

383736353433323130292827

262524232221PIC18F4455PIC18F4550Note 1: RB3 is the alternate pin for CCP2 multiplexing.DS39632E-page 2 2009 Microchip Technology Inc.


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PIC18F2455/2550/4455/4550

Pin Diagrams (Continued)

PIC18F4455

44-Pin TQFP44-Pin QFNPIC18F4455PIC18F4550PIC18F455010112361181920212212131415

388744434241403916172930313233232425

262728363435937RA3/AN3/VREF+RA2/AN2/VREF-/CVREFRA1/AN1RA0/

AN0MCLR/VPP/RE3NC/ICCK(2)/ICPGC(2)RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/AN11/KBI0/CSSPPNC/ICDT(2)/ICPGD(2)

RC6/TX/CKRC5/D+/VPRC4/D-/


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VMRD3/SPP3RD2/SPP2RD1/SPP1RD0/SPP0VUSBRC2/CCP1/P1ARC1/T1OSI/CCP2(1)/UOE

NC/ICPORTS(2)NC/ICRST(2)/ICVPP(2)RC0/T1OSO/T13CKIOSC2/CLKO/RA6OSC1/CLKIVSSVDDRE2/AN7/OESPPRE1/AN6/CK2SPPRE0/AN5/CK1SPPRA5/AN4/SS/HLVDIN/C2OUTRA4/T0CKI/C1OUT/RCVRC7/RX/DT/SDO

RD4/SPP4RD5/SPP5/P1BRD6/SPP6/P1CVSSVDDRB0/AN12/INT0/FLT0/SDI/SDARB1/AN10/INT1/SCK/SCLRB2/AN8/INT2/VMORB3/AN9/CCP2(1)/VPORD7/SPP7/P1D 541011236

1181920212212131415388744434241403916172930313233

232425262728363435937RA3/AN3/VREF+RA2/AN2/VREF-/CVREF

RA1/AN1RA0/


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AN0MCLR/VPP/RE3RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/

AN11/KBI0/CSSPP NCRC6/TX/CKRC5/D+/VPRC4/D-/VMRD3/SPP3RD2/SPP2RD1/SPP1RD0/SPP0VUSBRC2/CCP1/P1ARC1/T1OSI/CCP2(1)/UOERC0/T1OSO/T13CKI

OSC2/CLKO/RA6OSC1/CLKIVSSVDDRE2/AN7/OESPPRE1/AN6/CK2SPPRE0/AN5/CK1SPPRA5/AN4/SS/HLVDIN/C2OUTRA4/T0CKI/C1OUT/RCVRC7/RX/DT/SDORD4/SPP4RD5/SPP5/P1BRD6/SPP6/P1CVSSVDD

RB0/AN12/INT0/FLT0/SDI/SDARB1/AN10/INT1/SCK/SCLRB2/AN8/INT2/VMORB3/AN9/CCP2(1)/VPORD7/SPP7/P1D 54 VSSVDDVDDNote 1: RB3 is the alternate pin for CCP2 multiplexing.2: Special ICPORT features available in select circumstances. See Section 25.9 Special ICPORT Features (44-Pin TQFP

Package Only) for more information. 2009 Microchip Technology Inc. DS39632E-page 3


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PIC18F2455/2550/4455/4550

Table of Contents

1.0 Device Overview ............................................................

................................................................................

.............................. 7

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 35

4.0 Reset .......................................................................................................................................................................................... 45

5.0 Memory Organization ................................................................................................................................................................. 59

6.0 Flash Program Memory........................................................

................................................................................

...................... 81

7.0 Data EEPROM Memory ............................................................................................................................................................. 91

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 97

9.0 Interrupts .................................................................................................................................................................................... 99

10.0 I/O Ports ................................................................................................................................................................................... 113

11.0 Timer0 Module .............................................................

................................................................................

............................ 127


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12.0 Timer1 Module ......................................................................................................................................................................... 131

13.0 Timer2 Module .............................................................

................................................................................

............................ 137

14.0 Timer3 Module ......................................................................................................................................................................... 139

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 143

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................151

17.0 Universal Serial Bus (USB) ...................................................................................................................................................... 165

18.0 Streaming Parallel Port ...................................................

................................................................................

......................... 191

19.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 197

20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 243

21.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 265

22.0 Comparator Module.................................................................................................................................................................. 275

23.0 Comparator Voltage Reference Module........................................................................................................................

........... 281


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24.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 285

25.0 Special Features of the CPU................................................................................................................................

.................... 291

26.0 Instruction Set Summary .......................................................................................................................................................... 313

27.0 Development Support............................................................................................................................................................... 363

28.0 Electrical Characteristics .......................................................................................................................................................... 367

29.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 407

30.0 Packaging Information......................................................................................................................................

........................ 409Appendix A: Revision History............................................................................................................................................................. 419Appendix B: Device Differences......................................................................................................................................................... 419Appendix C: Conversion Considerations ........................................................................................................................................... 420Appendix D: Migration From Baseline to Enhanced Devices.........................................................................................................

.... 420Appendix E: Migration From Mid-Range to Enhanced Devices........................

................................................................................

. 421Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 421Index .................................................................................................................................................................................................. 423The Microchip Web Site ..................................................................................................................................................................... 433

Customer Change Notification Service .............................................................................................................................................. 433


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Customer Support.............................................................................................................................................................................. 433Reader Response .............................................................................................................................................................................. 434PIC18F2455/2550/4455/4550 Product Identification System ........................

................................................................................

.... 435

DS39632E-page 4 2009 Microchip Technology Inc.


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PIC18F2455/2550/4455/4550

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentationpossible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contactthe Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back ofthis data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at ourWorldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature numberfound on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon

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Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products.



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PIC18F2455/2550/4455/4550

NOTES:

DS39632E-page 6

2009 Microchip Technology Inc.


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PIC18F2455/2550/4455/4550

1.0 DEVICE OVERVIEWThis document contains device-specific information forthe following devices:

PIC18F2455 PIC18LF2455 PIC18F2550 PIC18LF2550 PIC18F4455 PIC18LF4455 PIC18F4550 PIC18LF4550This family of devices offers the advantages of allPIC18 microcontrollers namely, high computationalperformance at an economical price with the additionof high-endurance, Enhanced Flash programmemory. In addition to these features, thePIC18F2455/2550/4455/4550 family introduces designenhancements that make these microcontrollers a logical

choice for many high-performance, power sensitiveapplications.

1.1 New Core Features1.1.1nanoWatt TECHNOLOGYAll of the devices in the PIC18F2455/2550/4455/4550family incorporate a range of features that can significantlyreduce power consumption during operation.Key items include:

Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal oscillatorblock, power consumption during code executioncan be reduced by as much as 90%.Multiple Idle Modes: The controller can also runwith its CPU core disabled but the peripherals stillactive. In these states, power consumption can bereduced even further, to as little as 4%, of normaloperation requirements.On-the-Fly Mode Switching: Thepower-managed modes are invoked by user code

during operation, allowing the user to incorporatepower-saving ideas into their applicationssoftware design.Low Consumption in Key Modules: The powerrequirements for both Timer1 and the WatchdogTimer are minimized. See Section 28.0Electrical Characteristics for values.1.1.2UNIVERSAL SERIAL BUS (USB)Devices in the PIC18F2455/2550/4455/4550 familyincorporate a fully featured Universal Serial Buscommunications module that is compliant with the USB

Specification Revision 2.0. The module supports bothlow-speed and full-speed communication for all supporteddata transfer types. It also incorporates its own


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on-chip transceiver and 3.3V regulator and supportsthe use of external transceivers and voltage regulators.

1.1.3MULTIPLE OSCILLATOR OPTIONSAND FEATURESAll of the devices in the PIC18F2455/2550/4455/4550

family offer twelve different oscillator options, allowingusers a wide range of choices in developing applicationhardware. These include:

Four Crystal modes using crystals or ceramicresonators. Four External Clock modes, offering the option ofusing two pins (oscillator input and a divide-by-4clock output) or one pin (oscillator input, with thesecond pin reassigned as general I/O). An internal oscillator block which provides an8 MHz clock (2% accuracy) and an INTRC

source (approximately 31 kHz, stable overtemperature and VDD), as well as a range of6 user-selectable clock frequencies, between125 kHz to 4 MHz, for a total of 8 clockfrequencies. This option frees an oscillator pin foruse as an additional general purpose I/O.

A Phase Lock Loop (PLL) frequency multiplier,available to both the High-Speed Crystal andExternal Oscillator modes, which allows a widerange of clock speeds from 4 MHz to 48 MHz. Asynchronous dual clock operation, allowing theUSB module to run from a high-frequency

oscillator while the rest of the microcontroller isclocked from an internal low-power oscillator.Besides its availability as a clock source, the internaloscillator block provides a stable reference source thatgives the family additional features for robustoperation:

Fail-Safe Clock Monitor: This option constantlymonitors the main clock source against areference signal provided by the internaloscillator. If a clock failure occurs, the controller is

switched to the internal oscillator block, allowingfor continued low-speed operation or a safeapplication shutdown.Two-Speed Start-up: This option allows theinternal oscillator to serve as the clock sourcefrom Power-on Reset, or wake-up from Sleepmode, until the primary clock source is available. 2009 Microchip Technology Inc.DS39632E-page 7


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PIC18F2455/2550/4455/4550

1.2Other Special Features

Memory Endurance: The Enhanced Flash cellsfor both program memory and data EEPROM arerated to last for many thousands of erase/writecycles up to 100,000 for program memory and1,000,000 for EEPROM. Data retention withoutrefresh is conservatively estimated to be greaterthan 40 years.Self-Programmability: These devices can write totheir own program memory spaces under internalsoftware control. By using a bootloader routine,located in the protected Boot Block at the top of

program memory, it becomes possible to create anapplication that can update itself in the field.Extended Instruction Set: ThePIC18F2455/2550/4455/4550 family introducesan optional extension to the PIC18 instruction set,which adds 8 new instructions and an IndexedLiteral Offset Addressing mode. This extension,enabled as a device configuration option, hasbeen specifically designed to optimize re-entrantapplication code originally developed in high-levellanguages such as C.

Enhanced CCP Module: In PWM mode, thismodule provides 1, 2 or 4 modulated outputs forcontrolling half-bridge and full-bridge drivers.Other features include auto-shutdown fordisabling PWM outputs on interrupt or other selectconditions, and auto-restart to reactivate outputsonce the condition has cleared.Enhanced Addressable USART: This serialcommunication module is capable of standardRS-232 operation and provides support for the LINbus protocol. The TX/CK and RX/DT signals can

be inverted, eliminating the need for invertingbuffers. Other enhancements include AutomaticBaud Rate Detection and a 16-bit Baud RateGenerator for improved resolution. When themicrocontroller is using the internal oscillatorblock, the EUSART provides stable operation forapplications that talk to the outside world withoutusing an external crystal (or its accompanyingpower requirement).10-Bit A/D Converter: This module incorporatesprogrammable acquisition time, allowing for achannel to be selected and a conversion to be

initiated, without waiting for a sampling period andthus, reducing code overhead. Dedicated ICD/ICSP Port: These devices


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introduce the use of debugger and programmingpins that are not multiplexed with other microcontrollerfeatures. Offered as an option in selectpackages, this feature allows users to develop I/Ointensive applications while retaining the ability toprogram and debug in the circuit.1.3

Details on Individual FamilyMembersDevices in the PIC18F2455/2550/4455/4550 family areavailable in 28-pin and 40/44-pin packages. Blockdiagrams for the two groups are shown in Figure 1-1and Figure 1-2.

The devices are differentiated from each other in sixways:

1.Flash program memory (24 Kbytes for

PIC18FX455 devices, 32 Kbytes forPIC18FX550 devices).2.A/D channels (10 for 28-pin devices, 13 for40/44-pin devices).3.I/O ports (3 bidirectional ports and 1 input onlyport on 28-pin devices, 5 bidirectional ports on40/44-pin devices).4.CCP and Enhanced CCP implementation(28-pin devices have two standard CCPmodules, 40/44-pin devices have one standard

CCP module and one ECCP module).5.Streaming Parallel Port (present only on40/44-pin devices).All other features for devices in this family are identical.These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 andTable 1-3.

Like all Microchip PIC18 devices, members of thePIC18F2455/2550/4455/4550 family are available as

both standard and low-voltage devices. Standarddevices with Enhanced Flash memory, designated withan F in the part number (such as PIC18F2550),accommodate an operating VDD range of 4.2V to 5.5V.Low-voltage parts, designated by LF (such asPIC18LF2550), function over an extended VDD rangeof 2.0V to 5.5V.

DS39632E-page 82009 Microchip Technology Inc.


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PIC18F2455/2550/4455/4550

TABLE 1-1: DEVICE FEATURES

Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550

Operating Frequency DC 48 MHz DC 48 MHz DC 48 MHz DC 48 MHzProgram Memory (Bytes) 24576 32768 24576 32768Program Memory (Instructions) 12288 16384 12288 16384Data Memory (Bytes) 2048 2048 2048 2048Data EEPROM Memory (Bytes) 256 256 256 256Interrupt Sources 19 19 20 20I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B,C, D, ETimers 4 4 4 4Capture/Compare/PWM Modules 2 2 1 1Enhanced Capture/Compare/PWM Modules

0 0 1 1Serial Communications MSSP,Enhanced USARTMSSP,Enhanced USARTMSSP,Enhanced USARTMSSP,Enhanced USARTUniversal Serial Bus (USB)Module1 1 1 1Streaming Parallel Port (SPP) No No Yes Yes

10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input ChannelsComparators 2 2 2 2Resets (and Delays) POR, BOR,RESET Instruction,Stack Full,Stack Underflow(PWRT, OST),MCLR (optional),WDTPOR, BOR,RESET Instruction,

Stack Full,Stack Underflow(PWRT, OST),MCLR (optional),WDTPOR, BOR,RESET Instruction,Stack Full,Stack Underflow(PWRT, OST),MCLR (optional),WDTPOR, BOR,

RESET Instruction,Stack Full,Stack Underflow


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(PWRT, OST),MCLR (optional),WDTProgrammable Low-VoltageDetectYes Yes Yes YesProgrammable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;83 with ExtendedInstruction Setenabled75 Instructions;83 with ExtendedInstruction Setenabled75 Instructions;83 with ExtendedInstruction Setenabled

75 Instructions;83 with ExtendedInstruction SetenabledPackages 28-Pin PDIP28-Pin SOIC28-Pin PDIP28-Pin SOIC40-Pin PDIP44-Pin QFN44-Pin TQFP40-Pin PDIP44-Pin QFN

44-Pin TQFP



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PIC18F2455/2550/4455/4550

FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM

Data Latch

Data Memory(2 Kbytes)Address LatchData Address12Access BSR4 4PCH PCLPCLATH831 Level StackProgram Counter

PRO8 xALUAddress LatchProgram Memory(24/32 Kbytes)Data Latch208Table Pointerinc/dec logic218Data Bus

atch8IR123atchPCLATUPCUPORTEMCLR/VPP/RE3(1)Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resetsare disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Referto Section 2.0 Oscillator Configurations for additional information.3: RB3 is the alternate pin for CCP2 multiplexing.WInstruction Bus STKPTR Bank888BITOPFSR0FSR1

FSR2inc/decAddress


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12DecodelogicEUSART Comparator MSSP 10-BitADCTimer2 Timer1 Timer3 Timer0 HLVDCCP2

BOR DataEEPROMUSBInstructionDecode &ControlState MachineControl SignalsPower-upTimerOscillatorStart-up Timer

Power-onResetWatchdogTimerOSC1(2)OSC2(2)VDD,Brown-outResetInternalOscillatorFail-SafeClock MonitorReference

Band GapVSSMCLR(1)BlockINTRCOscillator8 MHzOscillatorSingle-SupplyProgrammingIn-CircuitDebugger

T1OSIT1OSOUSB VoltageRegulator VUSBPORTBPORTCRB0/AN12/INT0/FLT0/SDI/SDARC0/T1OSO/T13CKIRC1/T1OSI/CCP2(3)/UOERC2/CCP1RC4/D-/VMRC5/D+/VPRC6/TX/CK

RC7/RX/DT/SDORB1/AN10/INT1/SCK/SCLRB2/AN8/INT2/VMO


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RB3/AN9/CCP2(3)/VPORB4/AN11/KBI0RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDPORTARA4/T0CKI/C1OUT/RCV

RA5/AN4/SS/HLVDIN/C2OUTRA3/AN3/VREF+RA2/AN2/VREF-/CVREFRA1/AN1RA0/AN0OSC2/CLKO/RA6CCP1DS39632E-page 10 2009 Microchip Technology Inc.


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PIC18F2455/2550/4455/4550

FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM

Instruction

Decode &ControlData LatchData Memory(2 Kbytes)Address LatchData Address12Access BSR4 4PCH PCLPCLATH

831 Level StackProgram CounterPRO8 x 8BIALUAddress LatchProgram Memory(24/32 Kbytes)Data Latch208Table Pointer

inc/dec logic218Data Busatch8IR123atchPORTDRD0/SPP0:RD4/SPP4

PCLATUPCUPORTEMCLR/VPP/RE3(1)RE2/AN7/OESPPRE0/AN5/CK1SPPRE1/AN6/CK2SPPNote 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resetsare disabled.2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Referto Section 2.0 Oscillator Configurations for additional information.3: These pins are only available on 44-pin TQFP packages under certain condition

s. Refer to Section 25.9 Special ICPORT Features(44-Pin TQFP Package Only) for additional information.4: RB3 is the alternate pin for CCP2 multiplexing.


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EUSART Comparator MSSP 10-BitADCTimer2 Timer1 Timer3 Timer0CCP2HLVDECCP1BOR Data

EEPROMWInstruction Bus STKPTR Bank8State MachineControl Signals88Power-upTimerOscillator

Start-up TimerPower-onResetWatchdogTimerOSC1(2)OSC2(2)VDD, VSSBrown-outResetInternalOscillatorFail-SafeClock Monitor

ReferenceBand GapMCLR(1)BlockINTRCOscillator8 MHzOscillatorSingle-SupplyProgrammingIn-CircuitDebugger

T1OSIT1OSORD5/SPP5/P1BRD6/SPP6/P1CRD7/SPP7/P1DPORTAPORTBPORTCRA4/T0CKI/C1OUT/RCVRA5/AN4/SS/HLVDIN/C2OUTRB0/AN12/INT0/FLT0/SDI/SDARC0/T1OSO/T13CKIRC1/T1OSI/CCP2(4)/UOE

RC2/CCP1/P1ARC4/D-/VMRC5/D+/VP


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RC6/TX/CKRC7/RX/DT/SDORA3/AN3/VREF+RA2/AN2/VREF-/CVREFRA1/AN1RA0/AN0RB1/AN10/INT1/SCK/SCL

RB2/AN8/INT2/VMORB3/AN9/CCP2(4)/VPOOSC2/CLKO/RA6RB4/AN11/KBI0/CSSPPRB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDUSBFSR0FSR1FSR2inc/dec

Address12DecodelogicUSB VoltageRegulatorVUSBICRST(3)ICPGC(3)ICPGD(3)ICPORTS(3) 2009 Microchip Technology Inc. DS39632E-page 11


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PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS

Pin Name

PinNumber PinTypeBufferType DescriptionPDIP,SOICMCLR/VPP/RE3MCLRVPPRE31

IPISTSTMaster Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-lowReset to the device.Programming voltage input.Digital input.OSC1/CLKIOSC1CLKI

9IIAnalogAnalogOscillator crystal or external clock input.Oscillator crystal input or external clock source input.External clock source input. Always associated with pinfunction OSC1. (See OSC2/CLKO pin.)OSC2/CLKO/RA6OSC2CLKO

RA610OOI/OTTLOscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator inCrystal Oscillator mode.In select modes, OSC2 pin outputs CLKO which has 1/4 thefrequency of OSC1 and denotes the instruction cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output


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ST = Schmitt Trigger input with CMOS levels I = InputO = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.



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PIC18F2455/2550/4455/4550

TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

PinNumber PinTypeBufferType DescriptionPDIP,SOICRA0/AN0RA0AN0RA1/AN1RA1

AN1RA2/AN2/VREF-/CVREFRA2AN2VREFCVREFRA3/AN3/VREF+RA3AN3VREF+RA4/T0CKI/C1OUT/RCVRA4T0CKIC1OUT

RCVRA5/AN4/SS/HLVDIN/C2OUTRA5AN4SSHLVDINC2OUTRA6234

567I/OII/OII/OIIOI/O

III/O


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IOII/OIII

OTTLAnalogTTLAnalogTTLAnalogAnalogAnalogTTLAnalog

AnalogSTSTTTLTTLAnalogTTLAnalogPORTA is a bidirectional I/O port.Digital I/O.

Analog input 0.Digital I/O.Analog input 1.Digital I/O.Analog input 2.A/D reference voltage (low) input.Analog comparator reference output.Digital I/O.Analog input 3.A/D reference voltage (high) input.Digital I/O.Timer0 external clock input.

Comparator 1 output.External USB transceiver RCV input.Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.Comparator 2 output.See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2: Default assignment for CCP2 when CCP2MX Configuration bit is set.



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PIC18F2455/2550/4455/4550


Pin Name

PinNumber PinTypeBufferType DescriptionPDIP,SOICPORTB is a bidirectional I/O port. PORTB can be softwareprogrammed for internal weak pull-ups on all inputs.RB0/AN12/INT0/FLT0/SDI/SDARB0

AN12INT0FLT0SDISDA21I/OIIIII/OTTL

AnalogSTSTSTSTDigital I/O.Analog input 12.External interrupt 0.PWM Fault input (CCP1 module).SPI data in.I2C data I/O.RB1/AN10/INT1/SCK/

SCLRB1AN10INT1SCKSCL22I/OIII/OI/OTTL

AnalogSTST


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STDigital I/O.Analog input 10.External interrupt 1.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.RB2/AN8/INT2/VMO

RB2AN8INT2VMO23I/OIIOTTLAnalogST

Digital I/O.Analog input 8.External interrupt 2.External USB transceiver VMO output.RB3/AN9/CCP2/VPORB3AN9CCP2(1)VPO24I/OI

I/OOTTLAnalogSTDigital I/O.Analog input 9.Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver VPO output.RB4/AN11/KBI0RB4

AN11KBI025I/OIITTLAnalogTTLDigital I/O.Analog input 11.Interrupt-on-change pin.RB5/KBI1/PGM

RB5KBI1PGM


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26I/OII/OTTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.RB6/KBI2/PGCRB6KBI2PGC27I/OII/OTTL

TTLSTDigital I/O.Interrupt-on-change pin.In-Circuit Debugger and ICSP programming clock pin.RB7/KBI3/PGDRB7KBI3PGD28I/OII/O

TTLTTLSTDigital I/O.Interrupt-on-change pin.In-Circuit Debugger and ICSP programming data pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.



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PIC18F2455/2550/4455/4550


Pin Name

PinNumber PinTypeBufferType DescriptionPDIP,SOICPORTC is a bidirectional I/O port.RC0/T1OSO/T13CKIRC0T1OSOT13CKI

11I/OOISTSTDigital I/O.Timer1 oscillator output.Timer1/Timer3 external clock input.RC1/T1OSI/CCP2/UOERC1T1OSI

CCP2(2)UOE12I/OII/OOSTCMOSSTDigital I/O.

Timer1 oscillator input.Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver OE output.RC2/CCP1RC2CCP113I/OI/OSTSTDigital I/O.Capture 1 input/Compare 1 output/PWM1 output.

RC4/D-/VMRC4DVM


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15II/OITTLTTL

Digital input.USB differential minus line (input/output).External USB transceiver VM input.RC5/D+/VPRC5D+VP16II/OOTTL

TTLDigital input.USB differential plus line (input/output).External USB transceiver VP input.RC6/TX/CKRC6TXCK17I/OOI/O

STSTDigital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see RX/DT).RC7/RX/DT/SDORC7RXDTSDO18

I/OII/OOSTSTSTDigital I/O.EUSART asynchronous receive.EUSART synchronous data (see TX/CK).SPI data out.RE3 See MCLR/VPP/RE3 pin.

VUSB 14 P Internal USB 3.3V voltage regulator output, positive supply forinternal USB transceiver.VSS 8, 19 P Ground reference for logic and I/O pins.


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VDD 20 P Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.



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PIC18F2455/2550/4455/4550

TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number PinTypeBufferType DescriptionPDIP QFN TQFPMCLR/VPP/RE3MCLRVPPRE31 18 18IP

ISTSTMaster Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-lowReset to the device.Programming voltage input.Digital input.OSC1/CLKIOSC1CLKI13 32 30I

IAnalogAnalogOscillator crystal or external clock input.Oscillator crystal input or external clock source input.External clock source input. Always associated withpin function OSC1. (See OSC2/CLKO pin.)OSC2/CLKO/RA6OSC2CLKORA614 33 31

OOI/OTTLOscillator crystal or clock output.Oscillator crystal output. Connects to crystal orresonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4the frequency of OSC1 and denotes the instructioncycle rate.General purpose I/O pin.

Legend:TTL = TTL compatible input CMOS = CMOS compatible input or output


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ST = Schmitt Trigger input with CMOS levels I = InputO = Output P = Power

Note 1:Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2:

Default assignment for CCP2 when CCP2MX Configuration bit is set.3:These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is NoConnect unless ICPRT is set and the DEBUG Configuration bit is cleared.DS39632E-page 162009 Microchip Technology Inc.


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PIC18F2455/2550/4455/4550


Pin Name

Pin Number PinTypeBufferType DescriptionPDIP QFN TQFPRA0/AN0RA0AN0RA1/AN1RA1AN1RA2/AN2/VREF-/

CVREFRA2AN2VREFCVREFRA3/AN3/VREF+RA3AN3VREF+RA4/T0CKI/C1OUT/RCVRA4T0CKIC1OUT

RCVRA5/AN4/SS/HLVDIN/C2OUTRA5AN4SSHLVDINC2OUTRA6234

5671920212223241920

212223


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24I/OII/OII/O

IIOI/OIII/OIOII/OI

IIOTTLAnalogTTLAnalogTTLAnalogAnalogAnalogTTL

AnalogAnalogSTSTTTLTTLAnalogTTLAnalog

PORTA is a bidirectional I/O port.Digital I/O.Analog input 0.Digital I/O.Analog input 1.Digital I/O.Analog input 2.A/D reference voltage (low) input.Analog comparator reference output.Digital I/O.Analog input 3.A/D reference voltage (high) input.Digital I/O.

Timer0 external clock input.Comparator 1 output.External USB transceiver RCV input.


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Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.Comparator 2 output.See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is NoConnect unless ICPRT is set and the DEBUG Configuration bit is cleared.



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PIC18F2455/2550/4455/4550


Pin Name

Pin Number PinTypeBufferType DescriptionPDIP QFN TQFPPORTB is a bidirectional I/O port. PORTB can be softwareprogrammed for internal weak pull-ups on all inputs.RB0/AN12/INT0/FLT0/SDI/SDARB0AN12INT0

FLT0SDISDA33 9 8I/OIIIII/OTTLAnalogST

STSTSTDigital I/O.Analog input 12.External interrupt 0.Enhanced PWM Fault input (ECCP1 module).SPI data in.I2C data I/O.RB1/AN10/INT1/SCK/SCLRB1

AN10INT1SCKSCL34 10 9I/OIII/OI/OTTLAnalogST

STSTDigital I/O.


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Analog input 10.External interrupt 1.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.RB2/AN8/INT2/VMORB2AN8

INT2VMO35 11 10I/OIIOTTLAnalogSTDigital I/O.

Analog input 8.External interrupt 2.External USB transceiver VMO output.RB3/AN9/CCP2/VPORB3AN9CCP2(1)VPO36 12 11I/OII/OO

TTLAnalogSTDigital I/O.Analog input 9.Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver VPO output.RB4/AN11/KBI0/CSSPPRB4AN11KBI0

CSSPP37 14 14I/OIIOTTLAnalogTTLDigital I/O.Analog input 11.Interrupt-on-change pin.

SPP chip select control output.RB5/KBI1/PGMRB5


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KBI1PGM38 15 15I/OII/OTTL

TTLSTDigital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.RB6/KBI2/PGCRB6KBI2PGC39 16 16I/OI

I/OTTLTTLSTDigital I/O.Interrupt-on-change pin.In-Circuit Debugger and ICSP programming clock pin.RB7/KBI3/PGDRB7KBI3PGD40 17 17I/O

II/OTTLTTLSTDigital I/O.Interrupt-on-change pin.In-Circuit Debugger and ICSP programming data pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = Power

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is NoConnect unless ICPRT is set and the DEBUG Configuration bit is cleared.



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PIC18F2455/2550/4455/4550


Pin Name

Pin Number PinTypeBufferType DescriptionPDIP QFN TQFPPORTC is a bidirectional I/O port.RC0/T1OSO/T13CKIRC0T1OSOT13CKI15 34 32I/O

OISTSTDigital I/O.Timer1 oscillator output.Timer1/Timer3 external clock input.RC1/T1OSI/CCP2/UOERC1T1OSICCP2(2)

UOE16 35 35I/OII/OOSTCMOSSTDigital I/O.Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver OE output.RC2/CCP1/P1ARC2CCP1P1A17 36 36I/OI/OOSTSTTTL

Digital I/O.Capture 1 input/Compare 1 output/PWM1 output.Enhanced CCP1 PWM output, channel A.


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RC4/D-/VMRC4DVM23 42 42II/OI

TTLTTLDigital input.USB differential minus line (input/output).External USB transceiver VM input.RC5/D+/VPRC5D+VP24 43 43I

I/OITTLTTLDigital input.USB differential plus line (input/output).External USB transceiver VP input.RC6/TX/CKRC6TXCK25 44 44

I/OOI/OSTSTDigital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see RX/DT).RC7/RX/DT/SDORC7RX

DTSDO26 1 1I/OII/OOSTSTSTDigital I/O.EUSART asynchronous receive.

EUSART synchronous data (see TX/CK).SPI data out.


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Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No

Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.



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PIC18F2455/2550/4455/4550


Pin Name

Pin Number PinTypeBufferType DescriptionPDIP QFN TQFPPORTD is a bidirectional I/O port or a StreamingParallel Port (SPP). These pins have TTL input bufferswhen the SPP module is enabled.RD0/SPP0 19 38 38RD0 I/O ST Digital I/O.SPP0 I/O TTL Streaming Parallel Port data.RD1/SPP1 20 39 39

RD1 I/O ST Digital I/O.SPP1 I/O TTL Streaming Parallel Port data.RD2/SPP2 21 40 40RD2 I/O ST Digital I/O.SPP2 I/O TTL Streaming Parallel Port data.RD3/SPP3 22 41 41RD3 I/O ST Digital I/O.SPP3 I/O TTL Streaming Parallel Port data.RD4/SPP4 27 2 2RD4 I/O ST Digital I/O.SPP4 I/O TTL Streaming Parallel Port data.RD5/SPP5/P1B 28 3 3RD5 I/O ST Digital I/O.

SPP5 I/O TTL Streaming Parallel Port data.P1B O Enhanced CCP1 PWM output, channel B.RD6/SPP6/P1C 29 4 4RD6 I/O ST Digital I/O.SPP6 I/O TTL Streaming Parallel Port data.P1C O Enhanced CCP1 PWM output, channel C.RD7/SPP7/P1D 30 5 5RD7 I/O ST Digital I/O.SPP7 I/O TTL Streaming Parallel Port data.P1D O Enhanced CCP1 PWM output, channel D.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = InputO = Output P = PowerNote 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is NoConnect unless ICPRT is set and the DEBUG Configuration bit is cleared.



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PIC18F2455/2550/4455/4550


Pin Name

Pin Number PinTypeBufferType DescriptionPDIP QFN TQFPRE0/AN5/CK1SPPRE0AN5CK1SPPRE1/AN6/CK2SPPRE1AN6

CK2SPPRE2/AN7/OESPPRE2AN7OESPP89102526272526

27I/OIOI/OIOI/OIOSTAnalog

STAnalogSTAnalogPORTE is a bidirectional I/O port.Digital I/O.Analog input 5.SPP clock 1 output.Digital I/O.Analog input 6.

SPP clock 2 output.Digital I/O.Analog input 7.


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SPP output enable output.RE3 See MCLR/VPP/RE3 pin.VSS 12, 31 6, 30,316, 29 P Ground reference for logic and I/O pins.VDD 11, 32 7, 8,28, 29

7, 28 P Positive supply for logic and I/O pins.VUSB 18 37 37 P Internal USB 3.3V voltage regulator output, positivesupply for the USB transceiver.NC/ICCK/ICPGC(3)ICCKICPGC 12I/OI/OSTSTNo Connect or dedicated ICD/ICSP port clock.

In-Circuit Debugger clock.ICSP programming clock.NC/ICDT/ICPGD(3)ICDTICPGD 13I/OI/OSTSTNo Connect or dedicated ICD/ICSP port clock.In-Circuit Debugger data.ICSP programming data.

NC/ICRST/ICVPP(3)ICRSTICVPP 33IPNo Connect or dedicated ICD/ICSP port Reset.Master Clear (Reset) input.Programming voltage input.NC/ICPORTS(3)

ICPORTS 34 P No Connect or 28-pin device emulation.Enable 28-pin device emulation when connectedto VSS.NC 13 No Connect.

Legend:TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = Power

Note 1:Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

2:Default assignment for CCP2 when CCP2MX Configuration bit is set.


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3:These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is NoConnect unless ICPRT is set and the DEBUG Configuration bit is cleared. 2009 Microchip Technology Inc.DS39632E-page 21


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PIC18F2455/2550/4455/4550

NOTES:

DS39632E-page 22

2009 Microchip Technology Inc.


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PIC18F2455/2550/4455/4550

2.0OSCILLATORCONFIGURATIONS

2.1OverviewDevices in the PIC18F2455/2550/4455/4550 familyincorporate a different oscillator and microcontrollerclock system than previous PIC18F devices. The additionof the USB module, with its unique requirementsfor a stable clock source, make it necessary to providea separate clock source that is compliant with bothUSB low-speed and full-speed specifications.

To accommodate these requirements, PIC18F2455/2550/4455/4550 devices include a new clock branch to

provide a 48 MHz clock for full-speed USB operation.Since it is driven from the primary clock source, anadditional system of prescalers and postscalers hasbeen added to accommodate a wide range of oscillatorfrequencies. An overview of the oscillator structure isshown in Figure 2-1.

Other oscillator features used in PIC18 enhancedmicrocontrollers, such as the internal oscillator blockand clock switching, remain the same. They arediscussed later in this chapter.

2.1.1

OSCILLATOR CONTROLThe operation of the oscillator in PIC18F2455/2550/4455/4550 devices is controlled through two Configurationregisters and two control registers. Configurationregisters, CONFIG1L and CONFIG1H, select theoscillator mode and USB prescaler/postscaler options.As Configuration bits, these are set when the device isprogrammed and left in that configuration until thedevice is reprogrammed.

The OSCCON register (Register 2-2) selects the ActiveClock mode; it is primarily used in controlling clock

switching in power-managed modes. Its use isdiscussed in Section 2.4.1 Oscillator ControlRegister.

The OSCTUNE register (Register 2-1) is used to trimthe INTRC frequency source, as well as select thelow-frequency clock source that drives several specialfeatures. Its use is described in Section 2.2.5.2OSCTUNE Register.

2.2Oscillator TypesPIC18F2455/2550/4455/4550 devices can be operated

in twelve distinct oscillator modes. In contrast with previousPIC18 enhanced microcontrollers, four of thesemodes involve the use of two oscillator types at once.


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Users can program the FOSC3:FOSC0 Configurationbits to select one of these modes:

1. XTCrystal/Resonator2. HSHigh-Speed Crystal/Resonator

3.HSPLL High-Speed Crystal/Resonatorwith PLL Enabled4. ECExternal Clock with FOSC/4 Output5. ECIOExternal Clock with I/O on RA66.ECPLL External Clock with PLL Enabledand FOSC/4 Output on RA67.ECPIO External Clock with PLL Enabled,

I/O on RA68.INTHS Internal Oscillator used asMicrocontroller Clock Source, HSOscillator used as USB Clock Source9.INTIO Internal Oscillator used asMicrocontroller Clock Source, ECOscillator used as USB Clock Source,Digital I/O on RA610.INTCKO Internal Oscillator used asMicrocontroller Clock Source, EC

Oscillator used as USB Clock Source,FOSC/4 Output on RA62.2.1OSCILLATOR MODES ANDUSB OPERATIONBecause of the unique requirements of the USB module,a different approach to clock operation is necessary. Inprevious PIC devices, all core and peripheral clockswere driven by a single oscillator source; the usualsources were primary, secondary or the internal oscillator.With PIC18F2455/2550/4455/4550 devices, the primaryoscillator becomes part of the USB module and

cannot be associated to any other clock source. Thus,the USB module must be clocked from the primary clocksource; however, the microcontroller core and otherperipherals can be separately clocked from thesecondary or internal oscillators as before.

Because of the timing requirements imposed by USB,an internal clock of either 6 MHz or 48 MHz is requiredwhile the USB module is enabled. Fortunately, themicrocontroller and other peripherals are not requiredto run at this clock speed when using the primaryoscillator. There are numerous options to achieve theUSB module clock requirement and still provide flexibility

for clocking the rest of the device from the primaryoscillator source. These are detailed in Section 2.3Oscillator Settings for USB.


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2009 Microchip Technology Inc.DS39632E-page 23


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FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM

PIC18F2455/2550/4455/4550

FOSC3:FOSC0Secondary OscillatorT1OSCENEnableOscillatorT1OSOT1OSIClock Source Optionfor Other ModulesOSC1OSC2Sleep

Primary OscillatorXT, HS, EC, ECIOT1OSCCPUPeripheralsIDLENINTOSC PostscalerMUXMUX8 MHz4 MHz2 MHz1 MHz

500 kHz125 kHz250 kHzOSCCON11111010110001101000100031 kHz

INTRCSourceInternalOscillatorBlockWDT, PWRT, FSCM8 MHzInternal Oscillator(INTOSC)ClockControlOSCCON Source8 MHz

31 kHz (INTRC)01


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OSCTUNEand Two-Speed Start-up96 MHzPLLPLLDIVCPUDIV0

101 2PLLPrescalerMUX111110101100011010001000 1

2 3 4 5 6 10 1211100100PLLPostscaler 2 3

4 6USBUSBDIVFOSC3:FOSC0HSPLL, ECPLL,11100100OscillatorPostscaler 1 2

3 4CPUDIV10PeripheralFSEN 4USB Clock SourceXTPLL, ECPIOPrimaryClock(4 MHz Input Only)



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2.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 2-1: CAPACITOR SELECTION FORRESONATORS CERAMIC RESONATORSIn HS, HSPLL, XT and XTPLL Oscillator modes, a

crystal or ceramic resonator is connected to the OSC1and OSC2 pins to establish oscillation. Figure 2-2shows the pin connections.

The oscillator design requires the use of a parallel cutcrystal.

Note:Use of a series cut crystal may give a frequencyout of the crystal manufacturersspecifications.

FIGURE 2-2:CRYSTAL/CERAMICRESONATOR OPERATION(XT, HS OR HSPLL

CONFIGURATION)Note 1: See Table 2-1 and Table 2-2 for initial values ofC1 and C2.2: A series resistor (RS) may be required for ATstrip cut crystals.3: RF varies with the oscillator mode chosen.C1(1)C2(1)

XTALOSC2OSC1RF(3)SleepToLogicPIC18FXXXXRS(2)InternalTypical Capacitor Values Used:Mode Freq OSC1 OSC2

XT 4.0 MHz 33 pF 33 pFHS 8.0 MHz16.0 MHz27 pF22 pF27 pF22 pFCapacitor values are for design guidance only.These capacitors were tested with the resonatorslisted below for basic start-up and operation. Thesevalues are not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should test

the performance of the oscillator over the expectedVDD and temperature range for the application.See the notes following Table 2-2 for additional


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information.Resonators Used:4.0 MHz8.0 MHz16.0 MHzWhen using ceramic resonators with frequenciesabove 3.5 MHz, HS mode is recommended over XT

mode. HS mode may be used at any VDD for whichthe controller is rated. If HS is selected, the gain of theoscillator may overdrive the resonator. Therefore, aseries resistor should be placed between the OSC2pin and the resonator. As a good starting point, therecommended value of RS is 330 O.



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PIC18F2455/2550/4455/4550:CAPACITOR SELECTION FOR FIGURE 2-3: EXTERNAL CLOCK INPUTCRYSTAL OSCILLATOR OPERATION (HS OSC

Osc Type CrystalFreqTypical Capacitor ValuesTested:C1 C2XT 4 MHz 27 pF 27 pFHS 4 MHz 27 pF 27 pF8 MHz 22 pF 22 pF20 MHz 15 pF 15 pFCapacitor values are for design guidance only.These capacitors were tested with the crystals listed

below for basic start-up and operation. These valuesare not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.See the notes following this table for additionalinformation.Crystals Used:4 MHz8 MHz20 MHz

Note 1:Higher capacitance increases the stabilityof oscillator but also increases thestart-up time.

2:When operating below 3V VDD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use theHS mode or switch to a crystal oscillator.3:Since each resonator/crystal has its own

characteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.4:Rs may be required to avoid overdrivingcrystals with low drive level specification.5:Always verify oscillator performance overthe VDD and temperature range that isexpected for the application.An internal postscaler allows users to select a clockfrequency other than that of the crystal or resonator.

Frequency division is determined by the CPUDIVConfiguration bits. Users may select a clock frequencyof the oscillator frequency, or 1/2, 1/3 or 1/4 of the


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frequency.

An external clock may also be used when the microcontrolleris in HS Oscillator mode. In this case, theOSC2/CLKO pin is left open (Figure 2-3).

CONFIGURATION)

OSC1OSC2 OpenClock fromExt. System PIC18FXXXX(HS Mode)2.2.3 EXTERNAL CLOCK INPUTThe EC, ECIO, ECPLL and ECPIO Oscillator modesrequire an external clock source to be connected to theOSC1 pin. There is no oscillator start-up time requiredafter a Power-on Reset or after an exit from Sleepmode.

In the EC and ECPLL Oscillator modes, the oscillatorfrequency divided by 4 is available on the OSC2 pin.This signal may be used for test purposes or tosynchronize other logic. Figure 2-4 shows the pinconnections for the EC Oscillator mode.

FIGURE 2-4:EXTERNAL CLOCKINPUT OPERATION(EC AND ECPLLCONFIGURATION)

OSC1/CLKI

OSC2/CLKO FOSC/4Clock fromExt. System PIC18FXXXXThe ECIO and ECPIO Oscillator modes function like theEC and ECPLL modes, except that the OSC2 pinbecomes an additional general purpose I/O pin. The I/Opin becomes bit 6 of PORTA (RA6). Figure 2-5 showsthe pin connections for the ECIO Oscillator mode.

FIGURE 2-5:EXTERNAL CLOCKINPUT OPERATION

(ECIO AND ECPIOCONFIGURATION)

The internal postscaler for reducing clock frequency inXT and HS modes is also available in EC and ECIOmodes.OSC1/CLKII/O (OSC2) RA6Clock fromExt. System PIC18FXXXXDS39632E-page 262009 Microchip Technology Inc.


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2.2.4 PLL FREQUENCY MULTIPLIERPIC18F2455/2550/4255/4550 devices include a PhaseLocked Loop (PLL) circuit. This is provided specifically

for USB applications with lower speed oscillators andcan also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL andECPIO Oscillator modes. It is designed to produce afixed 96 MHz reference clock from a fixed 4 MHz input.The output can then be divided and used for both theUSB and the microcontroller core clock. Because thePLL has a fixed frequency input and output, there areeight prescaling options to match the oscillator inputfrequency to the PLL.

There is also a separate postscaler option for derivingthe microcontroller clock from the PLL. This allows theUSB peripheral and microcontroller to use the sameoscillator input and still operate at different clockspeeds. In contrast to the postscaler for XT, HS and ECmodes, the available options are 1/2, 1/3, 1/4 and 1/6of the PLL output.

The HSPLL, ECPLL and ECPIO modes make use ofthe HS mode oscillator for frequencies up to 48 MHz.The prescaler divides the oscillator input by up to 12 toproduce the 4 MHz drive for the PLL. The XTPLL modecan only use an input frequency of 4 MHz which drives

the PLL directly.

FIGURE 2-6:PLL BLOCK DIAGRAM(HS MODE)

MUXVCOLoopFilterandPrescalerOSC2

OSC1PLL EnableFINFOUTSYSCLKPhaseComparatorHS/EC/ECIO/XT Oscillator Enable24(from CONFIG1H Register)Oscillator2.2.5 INTERNAL OSCILLATOR BLOCKThe PIC18F2455/2550/4455/4550 devices include an

internal oscillator block which generates two differentclock signals; either can be used as the microcontrollersclock source. If the USB peripheral is not used, the


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internal oscillator may eliminate the need for externaloscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock sourcewhich can be used to directly drive the device clock. Italso drives the INTOSC postscaler which can provide arange of clock frequencies from 31 kHz to 4 MHz. The

INTOSC output is enabled when a clock frequencyfrom 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator(INTRC) which provides a nominal 31 kHz output.INTRC is enabled if it is selected as the device clocksource; it is also enabled automatically when any of thefollowing are enabled:

Power-up Timer Fail-Safe Clock Monitor Watchdog Timer

Two-Speed Start-upThese features are discussed in greater detail inSection 25.0 Special Features of the CPU.

The clock source frequency (INTOSC direct, INTRCdirect or INTOSC postscaler) is selected by configuringthe IRCF bits of the OSCCON register (page 33).

2.2.5.1 Internal Oscillator ModesWhen the internal oscillator is used as the microcontrollerclock source, one of the other oscillatormodes (External Clock or External Crystal/Resonator)must be used as the USB clock source. The choice of

the USB clock source is determined by the particularinternal oscillator mode.

There are four distinct modes available:

1.INTHS mode: The USB clock is provided by theoscillator in HS mode.2.INTXT mode: The USB clock is provided by theoscillator in XT mode.3.

INTCKO mode: The USB clock is provided by anexternal clock input on OSC1/CLKI; the OSC2/CLKO pin outputs FOSC/4.4.INTIO mode: The USB clock is provided by anexternal clock input on OSC1/CLKI; the OSC2/CLKO pin functions as a digital I/O (RA6).Of these four modes, only INTIO mode frees up anadditional pin (OSC2/CLKO/RA6) for port I/O use.



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2.2.5.2OSCTUNE RegisterThe internal oscillators output has been calibrated at

the factory but can be adjusted in the users application.This is done by writing to the OSCTUNE register(Register 2-1). The tuning sensitivity is constantthroughout the tuning range.

The INTOSC clock will stabilize within 1 ms. Code executioncontinues during this shift. There is no indicationthat the shift has occurred.

The OSCTUNE register also contains the INTSRC bit.The INTSRC bit allows users to select which internaloscillator provides the clock source when the 31 kHz

frequency option is selected. This is covered in greaterdetail in Section 2.4.1 Oscillator Control Register.

2.2.5.3Internal Oscillator Output Frequencyand DriftThe internal oscillator block is calibrated at the factoryto produce an INTOSC output frequency of 8.0 MHz.However, this frequency may drift as VDD or temperaturechanges, which can affect the controller operationin a variety of ways.

The low-frequency INTRC oscillator operates independently

of the INTOSC source. Any changes in INTOSCacross voltage and temperature are not necessarilyreflected by changes in INTRC and vice versa.

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0INTSRC TUN4 TUN3 TUN2 TUN1 TUN0bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 7INTSRC: Internal Oscillator Low-Frequency Source Select bit1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)

0 = 31 kHz device clock derived directly from INTRC internal oscillatorbit 6-5 Unimplemented: Read as 0bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

0000100000 = Center frequency. Oscillator module is running at the calibrated frequency.


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11111

10000 = Minimum frequency



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2.2.5.4 Compensating for INTOSC DriftIt is possible to adjust the INTOSC frequency bymodifying the value in the OSCTUNE register. This has

no effect on the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when tomake the adjustment, in which direction it should bemade and in some cases, how large a change isneeded. When using the EUSART, for example, anadjustment may be required when it begins to generateframing errors or receives data with errors while inAsynchronous mode. Framing errors indicate that thedevice clock frequency is too high; to adjust for this,decrement the value in OSCTUNE to reduce the clockfrequency. On the other hand, errors in data may suggest

that the clock speed is too low; to compensate,increment OSCTUNE to increase the clock frequency.

It is also possible to verify device clock speed againsta reference clock. Two timers may be used: one timeris clocked by the peripheral clock, while the other isclocked by a fixed reference source, such as theTimer1 oscillator. Both timers are cleared but the timerclocked by the reference generates interrupts. Whenan interrupt occurs, the internally clocked timer is readand both timers are cleared. If the internally clockedtimer value is greater than expected, then the internaloscillator block is running too fast. To adjust for this,

decrement the OSCTUNE register.

Finally, a CCP module can use free-running Timer1 (orTimer3), clocked by the internal oscillator block and anexternal event with a known period (i.e., AC powerfrequency). The time of the first event is captured in theCCPRxH:CCPRxL registers and is recorded for uselater. When the second event causes a capture, thetime of the first event is subtracted from the time of thesecond event. Since the period of the external event isknown, the time difference between events can becalculated.

If the measured time is much greater than the calculatedtime, the internal oscillator block is running toofast; to compensate, decrement the OSCTUNE register.If the measured time is much less than the calculatedtime, the internal oscillator block is running too slow; tocompensate, increment the OSCTUNE register.



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2.3 Oscillator Settings for USBWhen these devices are used for USB connectivity,they must have either a 6 MHz or 48 MHz clock for

USB operation, depending on whether Low-Speed orFull-Speed mode is being used. This may require someforethought in selecting an oscillator frequency andprogramming the device.

The full range of possible oscillator configurationscompatible with USB operation is shown in Table 2-3.

2.3.1LOW-SPEED OPERATIONThe USB clock for Low-Speed mode is derived from theprimary oscillator chain and not directly from the PLL. It

is divided by 4 to produce the actual 6 MHz clock.Because of this, the microcontroller can only use aclock frequency of 24 MHz when the USB module is

active and the controller clock source is one of theprimary oscillator modes (XT, HS or EC, with or withoutthe PLL).

This restriction does not apply if the microcontrollerclock source is the secondary oscillator or internaloscillator block.

2.3.2

RUNNING DIFFERENT USB ANDMICROCONTROLLER CLOCKSThe USB module, in either mode, can run asynchronouslywith respect to the microcontroller core andother peripherals. This means that applications can usethe primary oscillator for the USB clock while the microcontrollerruns from a separate clock source at a lowerspeed. If it is necessary to run the entire applicationfrom only one clock source, full-speed operationprovides a greater selection of microcontroller clockfrequencies.

TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION

Input OscillatorFrequencyPLL Division(PLLDIV2:PLLDIV0)Clock Mode(FOSC3:FOSC0)MCU Clock Division(CPUDIV1:CPUDIV0)MicrocontrollerClock Frequency48 MHz N/A(1) EC, ECIO None (00) 48 MHz

2 (01) 24 MHz3 (10) 16 MHz4 (11) 12 MHz


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48 MHz 12 (111) EC, ECIO None (00) 48 MHz2 (01) 24 MHz3 (10) 16 MHz4 (11) 12 MHzECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz

6 (11) 16 MHz40 MHz 10 (110) EC, ECIO None (00) 40 MHz2 (01) 20 MHz3 (10) 13.33 MHz4 (11) 10 MHzECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz24 MHz 6 (101) HS, EC, ECIO None (00) 24 MHz2 (01) 12 MHz3 (10) 8 MHz

4 (11) 6 MHzHSPLL, ECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz

Legend:All clock frequencies, except 24 MHz, are exclusively associated with full-speedUSB operation (USB clock of 48 MHz).Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,USB clock of 6 MHz).

Note 1:Only valid when the USBDIV Configuration bit is cleared.



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TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)

Input Oscillator

FrequencyPLL Division(PLLDIV2:PLLDIV0)Clock Mode(FOSC3:FOSC0)MCU Clock Division(CPUDIV1:CPUDIV0)MicrocontrollerClock Frequency20 MHz 5 (100) HS, EC, ECIO None (00) 20 MHz2 (01) 10 MHz3 (10) 6.67 MHz

4 (11) 5 MHzHSPLL, ECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz16 MHz 4 (011) HS, EC, ECIO None (00) 16 MHz2 (01) 8 MHz3 (10) 5.33 MHz4 (11) 4 MHzHSPLL, ECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz

12 MHz 3 (010) HS, EC, ECIO None (00) 12 MHz2 (01) 6 MHz3 (10) 4 MHz4 (11) 3 MHzHSPLL, ECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz8MHz 2 (001) HS, EC, ECIO None (00) 8 MHz2 (01) 4 MHz3 (10) 2.67 MHz4 (11) 2 MHz

HSPLL, ECPLL, ECPIO 2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz6 (11) 16 MHz4MHz 1 (000) XT, HS, EC, ECIO None (00) 4 MHz2 (01) 2 MHz3 (10) 1.33 MHz4 (11) 1 MHzHSPLL, ECPLL, XTPLL,ECPIO2 (00) 48 MHz3 (01) 32 MHz4 (10) 24 MHz

6 (11) 16 MHz

Legend:


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All clock frequencies, except 24 MHz, are exclusively associated with full-speedUSB operation (USB clock of 48 MHz).Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,USB clock of 6 MHz).

Note 1:

Only valid when the USBDIV Configuration bit is cleared.



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2.4 Clock Sources and OscillatorSwitchingLike previous PIC18 enhanced devices, the

PIC18F2455/2550/4455/4550 family includes a featurethat allows the device clock source to be switched fromthe main oscillator to an alternate, low-frequency clocksource. These devices offer two alternate clocksources. When an alternate clock source is enabled,the various power-managed operating modes areavailable.

Essentially, there are three clock sources for thesedevices:

Primary oscillators Secondary oscillators Internal oscillator blockThe primary oscillators include the External Crystaland Resonator modes, the External Clock modes andthe internal oscillator block. The particular mode isdefined by the FOSC3:FOSC0 Configuration bits. Thedetails of these modes are covered earlier in thischapter.

The secondary oscillators are those external sourcesnot connected to the OSC1 or OSC2 pins. Thesesources may continue to operate even after the

controller is placed in a power-managed mode.

PIC18F2455/2550/4455/4550 devices offer the Timer1oscillator as a secondary oscillator. This oscillator, in allpower-managed modes, is often the time base forfunctions such as a Real-Time Clock (RTC). Mostoften, a 32.768 kHz watch crystal is connectedbetween the RC0/T1OSO/T13CKI and RC1/T1OSI/UOE pins. Like the XT and HS Oscillator mode circuits,loading capacitors are also connected from each pin toground. The Timer1 oscillator is discussed in greaterdetail in Section 12.3 Timer1 Oscillator.

In addition to being a primary clock source, the internaloscillator block is available as a power-managedmode clock source. The INTRC source is also used asthe clock source for several special features, such asthe WDT and Fail-Safe Clock Monitor.

2.4.1 OSCILLATOR CONTROL REGISTERThe OSCCON register (Register 2-2) controls severalaspects of the device clocks operation, both infull-power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the

clock source. The available clock sources are theprimary clock (defined by the FOSC3:FOSC0 Configurationbits), the secondary clock (Timer1 oscillator) and


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the internal oscillator block. The clock source changesimmediately after one or more of the bits is written to,following a brief clock transition interval. The SCS bitsare cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits,IRCF2:IRCF0, select the frequency output of the internal

oscillator block to drive the device clock. The choices arethe INTRC source, the INTOSC source (8 MHz) or oneof the frequencies derived from the INTOSC postscaler(31 kHz to 4 MHz). If the internal oscillator block issupplying the device clock, changing the states of thesebits will have an immediate change on the internal oscillatorsoutput. On device Resets, the default outputfrequency of the internal oscillator block is set at 1 MHz.

When an output frequency of 31 kHz is selected(IRCF2:IRCF0 = 000), users may choose which internaloscillator acts as the source. This is done with the

INTSRC bit in the OSCTUNE register (OSCTUNE).Setting this bit selects INTOSC as a 31.25 kHz clocksource by enabling the divide-by-256 output of theINTOSC postscaler. Clearing INTSRC selects INTRC(nominally 31 kHz) as the clock source.

This option allows users to select the tunable and moreprecise INTOSC as a clock source, while maintainingpower savings with a very low clock speed. Regardlessof the setting of INTSRC, INTRC always remains theclock source for features such as the Watchdog Timerand the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clocksource is currently providing the device clock. The OSTSbit indicates that the Oscillator Start-up Timer (OST) hastimed out and the primary clock is providing the deviceclock in primary clock modes. The IOFS bit indicateswhen the internal oscillator block has stabilized and isproviding the device clock in RC Clock modes. TheT1RUN bit (T1CON) indicates when the Timer1 oscillatoris providing the device clock in secondary clockmodes. In power-managed modes, only one of thesethree bits will be set at any time. If none of these bits areset, the INTRC is providing the clock or the internal

oscillator block has just started and is not yet stable.

The IDLEN bit determines if the device goes into Sleepmode, or one of the Idle modes, when the SLEEPinstruction is executed.

The use of the flag and control bits in the OSCCONregister is discussed in more detail in Section 3.0Power-Managed Modes.

Note 1:The Timer1 oscillator must be enabled toselect the secondary clock source. The

Timer1 oscillator is enabled by setting theT1OSCEN bit in the Timer1 Control register(T1CON). If the Timer1 oscillator is


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not enabled, then any attempt to select asecondary clock source will be ignored.

2:It is recommended that the Timer1oscillator be operating and stable prior toswitching to it as the clock source; otherwise,

a very long delay may occur whilethe Timer1 oscillator starts.DS39632E-page 322009 Microchip Technology Inc.


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2.4.2OSCILLATOR TRANSITIONS sum of two cycles of the old clock source and three tofour cycles of the new clock source. This formula

PIC18F2455/2550/4455/4550 devices contain circuitry

assumes that the new clock source is stable.

to prevent clock glitches when switching betweenclock sources. A short pause in the device clock occurs Clock transitions are discussed in greater detail induring the clock switch. The length of this pause is the Section 3.1.2 Entering Power-Managed Modes.

REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

bit 7IDLEN: Idle Enable bit1 = Device enters Idle mode on SLEEP instruction

0 = Device enters Sleep mode on SLEEP instruction

bit 6-4IRCF2:IRCF0: Internal Oscillator Frequency Select bits111 = 8 MHz (INTOSC drives clock directly)110 = 4 MHz101 = 2 MHz100 = 1 MHz(3)011 = 500 kHz010 = 250 kHz001 = 125 kHz000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3OSTS: Oscillator Start-up Time-out Status bit(1)1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2IOFS: INTOSC Frequency Stable bit1 = INTOSC frequency is stable0 = INTOSC frequency is not stable

bit 1-0SCS1:SCS0: System Clock Select bits1x = Internal oscillator


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01 = Timer1 oscillator00 = Primary oscillator

Note 1: Depends on the state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE), see text.3: Default output frequency of INTOSC on Reset.



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2.5Effects of Power-Managed Modeson the Various Clock Sources

When PRI_IDLE mode is selected, the designatedprimary oscillator continues to run without interruption.For all other power-managed modes, the oscillatorusing the OSC1 pin is disabled. Unless the USBmodule is enabled, the OSC1 pin (and OSC2 pin ifused by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN andSEC_IDLE), the Timer1 oscillator is operating andproviding the device clock. The Timer1 oscillator mayalso run in all power-managed modes if required toclock Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),the internal oscillator block provides the device clocksource. The 31 kHz INTRC output can be used directlyto provide the clock and may be enabled to supportvarious special features regardless of thepower-managed mode (see Section 25.2 WatchdogTimer (WDT), Section 25.3 Two-Speed Start-upand Section 25.4 Fail-Safe Clock Monitor for moreinformation on WDT, Fail-Safe Clock Monitor andTwo-Speed Start-up). The INTOSC output at 8 MHzmay be used directly to clock the device or may bedivided down by the postscaler. The INTOSC output is

disabled if the clock is provided directly from the INTRCoutput.

Regardless of the Run or Idle mode selected, the USBclock source will continue to operate. If the device isoperating from a crystal or resonator-based oscillator,that oscillator will continue to clock the USB module.The core and all other modules will switch to the newclock source.

If the Sleep mode is selected, all clock sources arestopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowestcurrent consumption of the device (only leakagecurrents).

Sleep mode should never be invoked while the USBmodule is operating and connected. The only exceptionis when the device has been issued a Suspend

command over the USB. Once the module has suspendedoperation and shifted to a low-power state, themicrocontroller may be safely put into Sleep mode.

Enabling any on-chip feature that will operate during

Sleep will increase the current consumed during Sleep.The INTRC is required to support WDT operation. TheTimer1 oscillator may be operating to support a

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