Volume 12 Issue 01 Published, February 21, 2008 ISSN 1535-864X DOI: 10.1535/itj.1201Volume 12 Issue 02 Published June 17, 2008 ISSN 1535-864X DOI: 10.1535/itj.1202

Intel’s 45nm CMOS Technology

Intel®TechnologyJournal

Intel Technology Journal Q2’08 (Volume 12, Issue 2) focuses on Intel® 45nm high-k metal gate silicon technology. To quote Gordon Moore, co-founder of Intel, “this is the biggest change in transistor technology in 40 years.” In this journal are seven papers that cover the details of transistors and interconnects, variation and design for manufacturability, and packaging and reliability.

45nm High-k+Metal Gate Strain-Enhanced Transistors

Process and Electrical Results for the On-die Interconnect Stack

for Intel’s 45nm Process Generation

Managing Process Variation in Intel’s 45nm CMOS Technology

45nm SRAM Technology Development and Technology Lead Vehicle

45nm Design for Manufacturing

45nm Transistor Reliability

More information, including current and past issues of Intel Technology Journal, can be found at: http://developer.intel.com/technology/itj/index.htm

Flip-Chip Packaging Technology for Enabling 45nm Products

Volume 12 Issue 01 Published, February 21, 2008 ISSN 1535-864X DOI: 10.1535/itj.1201Volume 12 Issue 02 Published June 17, 2008 ISSN 1535-864X DOI: 10.1535/itj.1202

Intel® Technology JournalIntel’s 45nm CMOS Technology

Articles

Preface iii

45nm High-k+Metal Gate Strain-Enhanced Transistors 77

Process and Electrical Results for the On-die Interconnect 87 Stack for Intel’s 45nm Process Generation

Managing Process Variation in Intel’s 45nm CMOS Technology 93

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Computational lithography solution

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Less wetting away from the die for lower KOZ

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