Post on 13-Sep-2020
Mirabilis Design™ Training
VisualSim© Training
Implement Imaginations
OVERVIEW ON MIRABILIS & VISUALSIM
About Mirabilis DesignFounded in 2003 and based in Sunnyvale, CA, USA.
Development and support centers in US, India, China, Korea and Czech Republic
Focused on system architecture exploration of electronics, semiconductors and softwaree
40+ customers worldwide in Semiconductors, Aerospace, Computing and Automotive
VisualSim- Modeling and simulation software
Largest source of system modeling IP with embedded timing and power
About VisualSim•Monte-Carlo simulation with random samples,
• parameters, connectivity, traffic and use-cases
•Models constructed with library of pre-defined
• Parameterized components- Resource, custom development and HW/SW/NW
•Graphical and hierarchical construction, debugging and
• Analysis of model
•Batch-mode simulation for large-scale analysis & experimentation
• Interfaces to languages, simulators and spreadsheets
Performance Analysis
Power Exploration
Functional Analysis
Failure Analysis
Hardware Software
Network
Introduction to Conceptual Design
• Translation from product concept to implementation is critical link
• Traditional methods are “ad-hoc”
• VisualSim approach reduces risk’s and speed’s design
Errors in early stage cannot be rectified with optimized manufacturing
Concept VisualSimWay
OldWay
Field Testing
HDL, Software & Schematics
Architecturerefinement
Field Testing
HDL, Software & Schematics
BehaviorMapping
SystemArchitecture
”Is this the Right Design?”
Purpose of System Modeling•Select the right platformProcessor, FPGA or SoCHardware-Software partitioningTrade-off power, performance and functionality
•Develop full system prototype
Visibility into complete system operationsView both implementation agnostic and effects
•When to perform system simulation
Identify capacity limitation and bottlenecksPerformance, Power or Functionality is non-deterministic
VisualSim Capabilities•Traffic Analysis
•Flow control and arbitration algorithms
•System sizing
•Micro Architecture modeling
•Software design and trade-off
Concept To Specification
Idea Discussion
Need to design a new phone-Must play MP3 files-Java games so, accelerator-Need a uP, DSP and FPGA
Customer Requirements
BuildOptimizeValidate
ArchitectureComponent/Device SelectionFunctional PartitioningParameters/AttributesInterfaces and Pin DefinitionsFrame/Packet Fields
Performance Analysis Resource Sharing Task PartitioningRequirements Checking
Specification
About Modeling Library•Setup and Test InfrastructureTraffic Generators and stimulusOver 2000 Results, Statistics, Plotter and ViewersPerformance and Resource modelingImplementation-accurate hardware/software components
•Embedded power modeling at software and hardware level
•Extensive Model TemplatesFramework for 40+ applications with an exampleExamples provided to explain and use library component
Over 400 building blocks and 600 RegEx functions to provide total solution
Largest Systems-Level IPTraffic
• Distribution • Sequence• Trace file• Instruction profile
Reports• Latency• Throughput• Utilization• Ave/peak power• Statistics
Support• Listeners• Debuggers• Tracers• Assertions
Power• Table• Energy harvesters• Battery
SoC• AMBA (AHB/ APB/
AXI)• Corelink• CoreConnect• Network-on-Chip• Virtual Channel• DMA• Crossbar• Serial Switch• Bridge
Board-Level• VME• PCI/PCI-X/PCIe• SPI 3.0• Rapid IO• 1553B• FlexRay• CAN-FD• AFDX• TTEthernet• OpenVPX
Processors• ARM (M-Series)• ARM (A8, A72, A53, A76)• RISC-V• Nvidia- Drive-PX• Configurable GPU, DSP, µP
and µC• PowerPC• X86- Intel and AMD• DSP- TI and ADI• Others: MIPS, Tensilica,
Renesas SH, Marvel
RTL-like• Clock, Wire-Delay• Registers, Latches and
Flip-flop• ALU and FSM• Mux, DeMux• Lookup table
RTOS• Generic RTOS• ARINC 653• AUTOSAR
Stochastic• Queue• Time Queue• Quantity Queue• System Resources• Scheduling
algorithms
Custom Creator• Script language• 600 RegEx• Task graph• Use cases• Programming
languages
Storage• Flash• NVMe• Disk• Memory Controller• MPMC• Fibre Channel• Fire Wire
Networking• Switched Ethernet• Resilient Packet Ring• RP3• Wireless LAN 802.11• Bluetooth and PAN• Spacewire• Audio-Video Bridging• IEEE802.1Q
FPGA• Xilinx- Zynq, Virtex, Kintex• Intel-Stratix, Arria• Microsemi- Smartfusion• Programmable logic generator• External links to I/O, Network
and Memory
Memory• Memory Controller• SDR• DDR DRAM 2,3,4• LPDDR 2, 3, 4• HBM, HMC• QDR, RDRAM
Other VisualSim Features•InfrastructureLibrary ManagerDynamic Instantiation
•MethodologyModeling, simulation and analysis environment Graphical and hierarchical modelingMixed abstractions & mixed-signal modeling
•Application-SpecificSignal, audio, video and image processing, analog, controlsWired Networking and Wireless Sensor Networks
Modeling libraries, mixed abstraction and hierarchical development
OVERVIEW ON MIRABILIS & VISUALSIM
FUNDAMENTALS OF USING VISUALSIM
VisualSim Organization•Modeling GUI available in VisualSim are:Block Diagram EditorExpression EvaluatorText Editor
•Simulation - Graphical Simulation and Batch Simulation
•Post Processor – In addition to the blocks in Result library Post Processor can be used to checkout the result
•Documentation – Every block contains documentation
•Demonstration Systems – Several demo models are available as examples
Parts of the Block Diagram
3. Libraries
5. Parameters6. Variables
11. Use cases Behavior
8. Traffic
7. Setup
4. Annotations
2. Toolbar1. Menu-Bar
10. Architecture
9. Report
12. Mapping
Block Diagram DetailsConfigure Ports
Relations and Connections
Block Context Menu
Input PortOutput Port
Relation
Understanding Port Types•Data types are polymorphic identified at the ports
•Ports can be specified as: int, double, long, float, boolean, string, arrays or data structure
Note: Port types on either side of link must match
•Ports can also be unspecified: general or unknownSimulator dynamically adapts to the connected ports, if both sides are unspecified
User-added ports must always be set to a minimum of General
•Port types of library blocksIf a port type is fixed such as int, string or double, this cannot be modified and the port
connected to it must be modified
Exceptional Cases: Only unknown and general can be modified
ParametersDefinition• Constant, start-up configuration attribute• Used to simulate scenarios• defined in the model window or a block
Usage• Any block in the BDE can access these values• Export block parameters to link to the BDE parameters• Vary Parameter dynamically during simulation - usage is restricted
To Create New ParameterModel parameter:
1. Drag-n-Drop the parameter from Library Folder Model Setup >Parameter ('parameter=') into an open Block Diagram Editor window.
2. Right-click to select Customize Name of parameter & enter a name. Name must be unique, else BDE will generate exception.
3. Double click the new parameter name to set the value of the parameter.
To Create New ParameterBlock Parameter :
Double click on the block and select Add. Enter the parameter name and value.
Parameter Values Types Values
String “Queue1” “file://C:/VisualSim/filename.txt”
IntegerDouble Long
1 1.0 123L
Boolean True
Array Matrix
{1,2,3} [1,2;3,4] Note: Can contain any data type
Expression (Parameter1==4)?Parameter2:Parameter4
Data Structure {first=1,second=”name”}
Parameter UsageParameter in Expression:• Parameters can be on the right hand
side of the expression
Parameter UsageParameters to set Block attributes
Types• Generic parameters - Scalar and String• Expression Parameter• Special Parameter - File Parameter String Parameter Color Parameter Port Parameter
• Shared Parameter
FUNDAMENTALS OF USING VISUALSIM
INTRODUCTION TO LIBRARIES
Library Folders•Blocks are grouped together based on functionality and arranged in the Library
Block Color CodingSwitches, Math and Basic Queues
Data Structure and RegEx
Virtual Connections
Resource
Hierarchical
Display and Plotting
INIT, RegEx, Const
Traffic, Reports and Interfaces• TrafficSequence, distribution-based, files and clocks
• Plotters and Debugging ToolsReal-time viewers, animation and breakpointText, export, statistics
• Pre-configured AnalysisPower- Instantaneous, average and dischargePerformance- Latency, buffer, hit-ratio, stall-times, utilization, throughput, I/Os second
•InterfacesC/C++/Java, Python, MatLab, Excel, XMLFile I/O, serial I/O, device I/O, CORBA and RMI, DatabaseSystemC, HDL, STK
No Post Processing Required- Development to Analysis together
Modeling Libraries•Performance ResourceChannels, pipeline, SystemResource (schedulers), queues, active and quantity resources
•Cycle-Accurate Architecture GeneratorsProcessor (uP, DSP and Custom), memory, cacheProfile-based software sequence generator Linear, switched and Req-Ack bus Pipeline, DMA, ControllersBridges, Switches (Blocking & non-blocking)
•BehaviorBlock-based, C-like scripting, Java/C/C++, SystemC
•Application-SpecificSignal and image processing, analog, controlsWired Networking and Wireless Sensor Networks
No Programming Required- Accelerate model development
Largest Systems-Level IPTraffic
• Distribution • Sequence• Trace file• Instruction profile
Reports• Latency• Throughput• Utilization• Ave/peak power• Statistics
Support• Listeners• Debuggers• Tracers• Assertions
Power• Table• Energy harvesters• Battery
SoC• AMBA (AHB/ APB/
AXI)• Corelink• CoreConnect• Network-on-Chip• Virtual Channel• DMA• Crossbar• Serial Switch• Bridge
Board-Level• VME• PCI/PCI-X/PCIe• SPI 3.0• Rapid IO• 1553B• FlexRay• CAN-FD• AFDX• TTEthernet• OpenVPX
Processors• ARM (M-Series)• ARM (A8, A72, A53, A76)• RISC-V• Nvidia- Drive-PX• Configurable GPU, DSP, µP
and µC• PowerPC• X86- Intel and AMD• DSP- TI and ADI• Others: MIPS, Tensilica,
Renesas SH, Marvel
RTL-like• Clock, Wire-Delay• Registers, Latches and
Flip-flop• ALU and FSM• Mux, DeMux• Lookup table
RTOS• Generic RTOS• ARINC 653• AUTOSAR
Stochastic• Queue• Time Queue• Quantity Queue• System Resources• Scheduling
algorithms
Custom Creator• Script language• 600 RegEx• Task graph• Use cases• Programming
languages
Storage• Flash• NVMe• Disk• Memory Controller• MPMC• Fibre Channel• Fire Wire
Networking• Switched Ethernet• Resilient Packet Ring• RP3• Wireless LAN 802.11• Bluetooth and PAN• Spacewire• Audio-Video Bridging• IEEE802.1Q
FPGA• Xilinx- Zynq, Virtex, Kintex• Intel-Stratix, Arria• Microsemi- Smartfusion• Programmable logic generator• External links to I/O, Network
and Memory
Memory• Memory Controller• SDR• DDR DRAM 2,3,4• LPDDR 2, 3, 4• HBM, HMC• QDR, RDRAM
Power Modeling•Used in concept stage and refined during design stage
•Based on dynamic activity using data sheet information
•ReportsPeak, instant and average powerGenerate power profile for verification
•MethodologySpreadsheet of the power level/state for each deviceCombines effects of transitions and controller speedRegEx Functions
Early Power estimation enables high quality specification
Modeling Abstraction Determines the Level of Accuracy
AbstractionLevel
Type ofLibrary
Example Accuracy Limited by
Blocks Generic Resource-based ~85% Available parameters
SpecificAXI, DDR3, Processor >97%
Branch prediction accuracy and minor proprietary details
Scriptsn/a
User’s Hardware/ Software 95%~ None (can be exactly
to the hardware)Coding n/a C/C++/RTL/S
ystemC
Selecting the right block- 1•Traffic, Test Bench, ClockTraffic>ClockTraffic>Traffic
•Analysis, Reports, DisplayResults-
>TimeDataPlotterResults->StatisticsResult->TextDisplay
•Math and LogicalUse RegEx language
•Write/Read FileTraffic ReaderFile ReaderFile WriterExcelXML
•ImportC CodeApplicationSystemCVerilog
Selecting the right block- 2•Event ResourcesQueuesEvent Queue
•Timed ResourcesOne Queue to One Server- Timed QSymmetrical: Server_N_ResourceCombine multiple parallel resources-
Server (a.k.a Smart_Timed_Resource)Distributed requests- SystemResources
•QuantityQuantity_Based
•ChannelUsed to define logic for each Server1-to-many or 1-to-1 channels
•BehaviorAlgorithm- ScriptExisting algorithm- C, JavaSequence- ProcessingSequence with routing- Decision
•LookupArrays or Database
•Temporary storageIf content is not important, then use
Queue
If content determines activity, use arrays
Selecting the Right Block- 3•Hardware Standard blocks
•RTOS Server: SLOT type Queues + Script for custom scheduling (Queues block is
also known as Smart_Resource)
INTRODUCTION TO LIBRARIES
VISUALSIM TOOL ORGANIZATION
Tool Organization•VisualSim ArchitectLibrary such as Hardware Architecture, Resources, Script etc. Interfaces such as Verilog, SystemC, Application etc.Utilities such as PowerTableTechnologies such as DDR3, Cache and PCIe
•VisualSim Post-Processor
•VisualSim Explorer
•VisualSim Batch Simulation
VisualSim Architect•Used for Model Construction, analysis and verification
•Users:Model developers of core components such Interconnects, Processors and Multimedia
Architects assembling systems
Firmware designers
•Usage: Import code from pre-built modelsConstruct models using the pre-built library or combine multiple blocks to create new libraries
Batch simulation and Post Processor•System analysis using pre-existing models
•Users:Chip architectsPerformance analystsRTL developers
•Usage:Batch simulation using existing models by varying parametersView results from batch simulation using Post Processor
VisualSim Explorer•Trade studies, documentation, reference designs, explore variations of the specification
•Users Marketing, Management, Customers (reference design) Create BoM (customization required) Casual users such as FAE and implementation teams
•Usage Training on Wiki Conduct complex analysis using pre-built models in a familiar graphical environment. Provide customers early view on a new device or system Remote access via the Web but no access to tool install Conduct offsite or customer demonstration with latest models
Use for sharing early specification with design teams, customers and partners from within documentation
Advantages of VisualSim Explorer• Zero learning curve• Does not consume Architect license and reduces cost• No cost for external and other teams to access models and results. Anyone anywhere
can conduct analysis, restrict visibility to details
• IP is not distributed to people or organization that have no need for them
VISUALSIM TOOL ORGANIZATION
Mirabilis Design™ Training
Introduction to Modeling
Mirabilis Design™ Training 2
Question answered by the Model• What is Cache Utilization and Latency?
Incorporating the Flow, Scalability and Reusability• Level of Abstraction, Speed vs. Accuracy
Incorporating System-level settings• Data Structures, Parameters and Variables
Architectural Concept to Executable Specification
Mirabilis Design™ Training 3
Top Down Modeling Process• Conceptualize -> Thinking -> Question, Abstraction
• Conceptualize -> Thinking -> DS, PARAM, VAR
• Conceptualize -> Thinking -> Blocks, Output
• Wait some time and Repeat
Bottom Up Modeling Process• Conceptualize -> Thinking -> Blocks, Output
• Conceptualize -> Thinking -> DS, PARAM, VAR
• Conceptualize -> Thinking -> Question, Abstraction
• Wait some time and Repeat
Concept to Specification
Best is a combination of both
Mirabilis Design™ Training 4
System Definition Methodology
Separation of Workload, Behavior, Architecture and Analysis
Data Structures carry information (Fields) through model
Manipulate Data Structure Fields to define algorithm
Variables to communicate between blocks and DS
Virtual Connections simplify data flow through the model
Mirabilis Design™ Training 5
AbstractionSub-system under study
Resource utilization, system latency or both?
Sub-system is defined in detail while abstracting rest of the system
Environment can be treated as traffic generators or sinks
Select required modeling abstraction
Performance/ queuing: Limited relevance to underlying circuits and software
Behavior/ functional: Functions to manipulate incoming data
Architecture/ transaction: Add implementation constraints to performance model
Software-driven: C/C++/Java
Implementation (RTL, Circuit and transistors): EDA Vendor
Mirabilis Design™ Training 6
Constructing a Performance Model
Break down model into elements
Traffic sources - Agreeing on traffic profiles
Defining behavior or actions performed in the system
Constructing the data flow and the control flow
Connectivity of hardware and software architectures
Mapping the behavior tasks to the architecture
Analysis expected
Determine regions for analysis
Types of results - latency, throughput, utilization etc.
Mirabilis Design™ Training
Design Methodologies
Data-flow drivenStatistical modeling of application with minimal implementation restriction
Sub-system design evaluating hardware topologies
Separation of Behavior and ArchitectureHardware-Software partitioning
Software code optimizationOptimize task or application for latency and power
6/22/2020
Mirabilis Design™ Training
Methodology Flow-Diagram
6/22/2020
Algorithm & Protocol
Development
Flow-chart of Application (s)
Annotate Flow Chart with delays and
contention
Define Architecture
Simulate& Analysis
Generate Specification
Verification & Software optimization
Mapping
Repeat toOptimize (or)
Mirabilis Design™ Training
In-Line Flow
Behavior flow contains timing and queuing information
Used to model flow control and single behavior flows
Can be used to describe software-only behaviors
9
Mirabilis Design™ Training
Separation of Behavior and Architecture
Behavior flow describes the sequence of processes or threadsEach function in the flow is mapped to a hardware platform componentAll timing and power-related are defined on the architecture segment
6/22/2020
Mirabilis Design™ Training
Separation Methodology:Model Construction Setup
6/22/2020
Algorithm- MatLab
Protocol -VisualSim
Input
ModelFunctional flowchart-One per
Application
Model hardware platform
with Cores and IP
Define Attributes
Assign Flowchart tasks to
cores and IP
Flowchart Mapping Platform
Mirabilis Design™ Training
Separation Methodology:Simulate and Analysis
6/22/2020
Simulate MeetRequirements
Plots &Statistics
Go ToRefinement
Change Parameters& Simulate
Restart withModel SetupVary mapping,
timing, size and power attributes
Good but has hot-sports
Need morestudy
Far-away
Mirabilis Design™ Training
Separation Methodology: Refinement
Software or parallel
flow
Hardware IP
RefineAlgorithm
Define data and interfaces
Move to Platform
ModifyFlow
Vary mapping, timing, size and power attributes
AttributeChange
RepeatSimulate &Analysis
Experiment
Mirabilis Design™ Training
Separation Methodology: Software Optimization and Verification
VendorISS
DetailedRefinement
RepeatSimulate &Analysis
Experiment
VisualSim Fast Functional
model
Vcd file orRTL
Compare with System
Model
Experiment
Mirabilis Design™ Training
Software Code Optimization
QEMU System Model in
VisualSim
Execute Trace on Model
(CORBA I/F)(File I/F)
Instruction & Deviceaccess trace
View Power and Performance Metrics
Run Iterations by varying system
attributes & traces
Code
Mirabilis Design™ Training
Trace from Instrumentation
Application ProcessorInstruction count and cyclesInstruction and Data cache- Read/WriteMemory Access
PeripheralsAccess by word lines for each device using memory map information
NoteSDK contains no timing information
Mirabilis Design™ Training
Trace Sample
{InstructionCount = 11299, InstructionCycle = 57455, ICacheHit = 4730, ICacheMiss = 952, DCacheReadHit = 4012, DCacheReadMiss = 383, DCacheWriteHit = 2752, DCacheWriteMiss = 65, DDR_Read = 1335, DDR_Write = 448, SimHostTime = 0.024972, SimTargetTime = 57456, Index = 0, ioReadCount={4, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34}, ioWriteCount={2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 2, 9}, processorID=0}
Mirabilis Design™ Training
VisualSim Platform Screen Shot
Mirabilis Design™ Training
Standard ProfilesPerformance
Response time per application or method
Utilization of system resources to identify system bottleneck
Cache/memory utilization
PowerPower consumed per application or method
Battery discharge
Device power profile
Mirabilis Design™ Training
VisualSim Profile Output
Application Performance Hardware Performance
Power Profile