A market leader in the field of technical training is glad to

organize a seminar on VLSI Design (VHDL) to shape the career

of bright students and to turn them into a great engineer. We

hope to have a good time with you..!!!

Your concern and co-operation is highly valuable to us.

___________

Team CETPA

To compress the digital world.

To explore the hidden perfection and create the

brain of a machine.

*The above two are considered as a very difficulttasks in the field of electronics engineering, wherein fact it’s a very simple technology.

VHDL is for coding models of a digital system.

Reasons for modeling:

◦ Requirements specification

◦ Documentation

◦ Testing using simulation

◦ Formal verification

◦ Synthesis

Goal:

◦ Most ‘reliable’ design process, with minimum cost and time

◦ Avoid design errors!

VHDL is a programming language that allows one tomodel and develop complex digital systems in adynamic environment.

Object Oriented methodology for you C people canbe observed -- modules can be used and reused.

Allows you to designate in/out ports (bits) andspecify behavior or response of the system.

C is procedural language whereas VHDL is semiconcurrent & semi sequential language.

C is Case Sensitive whereas VHDL is caseinsensitive.

There are some similarities, as with anyprogramming language, but syntax and logic arequite different.

• Interfaces (PORTS)

• Behavior

• Structure

• Test Benches

• Simulation

• Synthesis

Dataflow

Behavioral

Structural

Kind of BORING sounding huh??

Well, it gets more exciting with the details !!

:)

Uses statements that defines the actual flow of data.....

such as,

x <= y -- this is NOT less than equal to

-- told you its not C

this assigns the Boolean signal x to the value of Boolean signal y... i.e. x = y

this will occur whenever y changes....

Entity declaration…(Describes the input/output ports of a module)

entity reg4 is

port ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );

end entity reg4;

entity name port names port mode (direction)

port typereserved words

punctuation

Architecture body Describes an implementation of an entity

May be several per entity

Behavioral architecture Describes the algorithm performed by the

module

ContainsProcess statements, each containing Sequential statements, includingSignal assignment statements and

Wait statements

Omit entity at end of entity declaration.

Omit architecture at end of architecture body.

Omit is in process statement header.

architecture behav of reg4 is

begin

process (d0, ... )

...

begin

...

end process ;

end behav;

entity reg4 is

port ( d0, d1, d2 : in bit

d3, en, clk : in bit;

q0, q1, q2, q3 : out bit

);

end reg4;

Structural architecture

implements the module as a composition of subsystems

contains

○ signal declarations, for internal interconnections

the entity ports are also treated as signals

○ component instances instances of previously declared entity/architecture pairs

○ port maps in component instances

connect signals to component ports

An architecture can contain both behavioral and structural parts

Process statements and component instances○ Collectively called concurrent statements

Processes can read and assign to signals

Example: register-transfer-level (RTL) model

Data path described structurally

Control section described behaviorally

shift_reg

reg

shift_adder

control_section

multiplier multiplicand

product

• Testing a design by simulation

• Use a test bench model

– A model that uses your model

– Apply test sequences to your inputs

– Monitors values on output signals

• Either using simulator.

• Or with a process that verifies correct operation

• Or logic analyzer.

Discrete event simulation Time advances in discrete steps.

When signal values change—events occur.

A processes is sensitive to events on input signals Specified in wait statements.

Resumes and schedules new values on output signals.○ Schedules transactions.

○ Event on a signal if value changes.

Initial Design Entry

Logic Optimization

Technology Mapping

Placement

Routing

Programming Unit

VHDL, Schematic, State Diagram

Minimized Blocks- To minimize area

Optimize Boolean Expressioninto a standard form- To optimize area or speed

Where the logic block is placed ?- With optimum routing wire

Connection between cells- To minimize area.

Used to configure the final circuit

• Implement the VHDL portion of coding for synthesis.

• Identify the differences between behavioral and structural coding styles.

• Distinguish coding for synthesis versus coding for simulation.

• Use scalar and composite data types to represent information.

• Use concurrent and sequential control structure to regulate information flow.

• Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures).

• Executable specification.

• Functionality separated from implementation.

• Simulate early and fast (Manage complexity)

• Explore design alternatives.

• Get feedback (Produce better designs)

• Automatic synthesis and test generation (ATPG for ASICs)

• Increase productivity (Shorten time-to-market)

• Technology and tool independence.

• Portable design data (Protect investment)

• Digital Signal Processing.

• IC Testing & Analysis.

• FPGA Design Verification.

• FPGA Development.

• Hardware Design.

• IC designing.

• ASIC Development.

• THANK YOU

E-Mail Gaurav_rai@live.com

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