Sprinkler Buddy

Presentation #9:

“Layout and a

New Feature”

4/4/2007

Team M3Panchalam Ramanujan

Sasidhar UppuluriDevesh Nema

Kalyan KommineniKartik Murthy

Design Manager: Bowei Gai

“Low Cost Irrigation Management For Everyone ! ”

Current Status Determine Project Develop Project Specifications Plan Architectural Design

Determination of all components in design Detailed logical flowchart

Design a Floor Plan Create Structural Verilog Make Transistor Level Schematic Layout

(~85% done..all modules LVS, Some Global Routed, FSMs are incomplete)

Testing (Extraction, LVS, and Analog Sim.) Glitches removed from all logic

Updated Design SizeBlock (# used) Size (um)

40:20 Muxes (4) 20 x 80

60:20 Muxes (2) 20 x 120

Counter (2) 12 x 17

KC ROM (4 parts) 181 x 8

P ROM (1) 70 x 8

Metric Storage SRAMS (2)

181 x 60

Constant Storage ROM (1)

181 x 8

Floating Point Adder (4)

96x151

Floating Point Multiplier (2)

89 x 40

10 Bit Registers (8) 50 x 10

• 362um x 361 um• ~ 1 : 1.0001 aspect ratio• .129 mm^2 area• .232 Density

Layout: Progress

All Big Modules LVS Separate Operation Modes wired

Hourly Update, Computation Mode, and Feed Back are done

Daily Update is wired with the exception of the feedback loop

3/6 FSMs are not complete Sizes estimated Space left

Layout : Entire Chip

Power Logic

Gating Sections

Chip separated into 7 virtual VDD/GND sections1 in HU, 3 in DU, 3 in CMDistributes load and reduces power rail

bounce

Power Rail Bounce

“Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures”, Kim et al

Hourly Update Operation

Daily Update Operation

Computation Operation

Approximate Savings Components that remain on

Feedback Mode (3407T)Registers (1944T)FSMs (1514T)SRAMs (4304T)

63.1% of all Transistors are shut off most of the day

Layout : Power Gate Transistors

Density: .05 transistors/um2

V DD Gating

Layout : Power Gate Transistors

Density: .06 transistors/um2

GND Gating

Design Challenges and Implementation

DecisionsFor The Past Week

Design Challenge

Translation to HW

Low Power • Power Gating to reduce leakage current• Sacrificed Density for Power Savings

Problems/QuestionsFSM routing was much more complex

than expected

For Next TimeFinish