A brief description

A prototype of a 256-pixel 3D ASIC, proposed by the Italian VIPIX

Collaboration and implementing a fast readout architecture with

sparsification capabilities, was recently submitted. The chosen technology is

CMOS Chartered 130 nm. In particular, the readout logic exploits one of the

two layers of a 3D device. The readout logic can face an input hit rate of the

order of 100MHz/cm2, it can interface with a matrix of 256 pixels and

allows sweeping the matrix within 1μs. The architecture has been deeply

investigated in terms of efficiency and sparsification capabilities and a

parameterized VHDL code has been designed to match even larger matrices

of pixels. A fast readout might also match a data-driven tracking system.

The overall project leads to design a high-density thin vertex detector with

an on-chip sparsified digital readout system, for particle tracking, aimed at

matching the requirements of future high-energy physics experiments.

Readout circuit with sparsification

capabilities

256-pixels

Full-custom matrix

256-pixels

STD-cell-based matrixMain Features

- 2 matrixes of 256 pixels each

- 1 made of sensors 40x40mm2 from

the top layer

- 1 based on digital std-cell registers,

- to be used ONE at a time,

- Slow-Control for configuration,

- on-line data sparsification,

- 1 readout clocks @ 100 MHz,

- 1 slow-control clock,

- Stand-By in case of over-hit-rate

15000 std-cells for the digital

architecture

+

256 full-custom sensors

2- The Matrix

3- The Matrix Readout

• At each clock cycle, a full column (1-to-8 hits) is readout in parallel

• Each MC requires 4 clock cycles (read 4 columns) + 1 clock cycle to reset the MP

• Empty MC are skipped

XX

X

X

X

sweeping task

X

The hits are on-line associated with a 8-bit Time-Stamp

Columns being scanned – 1 column in 1 clock cycle

XX

X

X

X

X

• Some pixels get fired

The FastOR lines of the fired MP activates

• A Bunch Crossing (BC) edge arrives

BC clock edge XX

X

X

X

X

The fired MPs are frozen by the Latch Enable lines

• The readout continuously seek for fired MP to be scanned

• Only the columns of the fired MPs are scanned

• 1 Clock cycle per column regardless of the number of hits

X = hit.

A BC edge determines

the start of a new time

window. All the hits

already present on the

matrix belong to the

previous time window.Bump-Bonding

area for

256 matrix

interface

40x40mm2

15000 std-cell area

REDUNDANT!!

5- ASIC designed and SUBMITTED

The 256-pixel matrix is

arranged in:

- 32 columns 8 rows

- 16 MacroPixels (MP)

composed of 4 4 pixels

- 8 MacroColumns (MC)

2 MacroRows (MR)

Sparsified Fast Readout for a

256-Pixel 3D DeviceA. Gabrielli 1, F. Giorgi 1, F. Morsani2, M. Villa1

for the VIPIX Collaboration

1Bologna University & INFN-Bologna, IT2 Pisa University & INFN-Pisa, IT

17-bit formatted Output Data Bus:

Data Valid

4- The Hit Readout

Barrel (16 hit depth)

N Hit to write (0 to 8)

8-hit wide BUS

Sparsifier

Pixel Row Bus

• The Sparsifier encodes all the hits with an Address+Time Stamp word in 1 clock cycle

• The Barrel can store up to 8 hits per clock cycle

• The Barrel is a FIFO queue for the dataflow buffering. When full, matrix readout in stand-by

17-bit

Output

Data Bus

Pixel Row

Pixel Column within MP

MC Address

Time Stamp

1 bit 3 bit 2 bit 3 bit 8 bit

1- Abstract

Digital Design-FlowUsing 5 out of 6 metal layers

VHDL code

Synopsys

(design_analyzer/compiler)

Synthesis verilog flat netlist

ARM Chartered 130-nm library

Modelsim

pre-synthesis simulation

Cadence (SoC_encounter primetime

nanoroute)

Verilog netlist load & block cell

Floorplan

Placement & Timing-Analysis

Clock Tree Synthesis Routing

Detail Routing - Signal Integrity - Timing-

Analysis

ECO routing

DRC - Antennas - Timing-Analysis

GDSII, SDF, Verilog post-layout flat netlist

Cadence (Simvision-Verilog)

Verilog post-route simulation with SDF delays and cell

models

Optimization

Open Points ??

Corner Analysis

Timing Models -

Layer Maps

Tools’ Compatibility

Patch

Design-Flow through

Synopsys

and

Cadence Encounter

Italians

–University at Bergamo

–University at Pavia

–University at Perugia

–INFN Bologna

–INFN at Pisa

–INFN at Rome

• To join – NDA with Tezzaron

– LOI to Fermilab asking to participate in MPW run

– Only cost is for MPW space

• Members receive from Tezzaron– Cadence PDK for Chartered 0.13 um

– Calibre DRC/LVS/PEX(XRC) deck for Chartered 0.13 um CMOS with correct process options

– Calibre DRC deck for Tezzaron 3D design rules• Cu-cu bond interface

• Via formation

– Information for fabrication of 2D and 3D I/O pads

– ARM Artisan library (separate NDA)• Full-layout views

– Also available but not used (separate cost for each)• MicroMagic 3DMax (alternative to Virtuoso)

• Magma (working on 3D LVS)

Problems with the digital

Design-KIT from ARM

V.Re N02-3 and G. W.

Deptuch N27-1

Multi Project Wafer Consortium

Pixel-Column

Address inside a MP

Macro Column Address

Pixel

Row

Address

Tezzaron-Chartered

Consortium