MINI-PROJECTDIGITAL MULTIPLIER

(BOOTH MULTIPLIER)

Internal GuideT.Sireesha

Mohd Naseeruddin Ahmed 11621a0499Sajjanam Laxman 11621a04b6

CoordinatorI.V.S Rama Sastry

AECBHONGI

R

OUTLINEABSTRACT

Booth MultiplierINTRODUCTION

EXAMPLE

BLOCK DIAGRAM

(FLOW CHART)

CODING

RESULT

CONCLUSION

VHDL LANGUAGE

ALGORITHM

Simulation and development of VHDL based “Digital Multiplier” on Virtex -6 FPGA ML605 Evaluation kit

ABSTRACT

1. Thorough study an evaluating techniques for implementing digital multiplier(BA).

2. The implementation of this algorithm is required to be carried on FPGA using VHDL

3. Simulation of digital multiplier is to be carried out using ISIM simulator.

4. The algorithm is required to be tested and validated on a suitable FPGA based hardware platform which is capable of handling required rate.

Booth algorithm is used for Simulation and Development of Digital Multiplier. It is a powerful algorithm for signed-number multiplication, which treats both positive and negative numbers uniformly.

INTRODUCTION

Multipliers plays key components for many high performance systems such asa) FIR Filters

b) Microprocessors

c) Digital Signal Processors, etc.

With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets

i. High speed

ii. Low power consumption

iii. Regularity of layout

iv. Less area.

Or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation.

• There are many types of multipliers. For example:

• Array multiplier

• Booth multiplier

• Serial multiplier

• Shift and Add multiplier

• Wallace tree multiplier

• Baugh Woolley multiplier

• Braun multiplier, etc.

Andrew Donald Booth

BOOTH MULTIPLIER

Booth’s multiplication algorithm is the multiplication algorithm that multiplies two signed binary numbers in two's complement form.

The algorithm was invented by Andrew Donald Booth in 1951 while doing research on crystallography in London.

Booth used desk calculators that were faster at shifting than adding and created the algorithm to increase their speed.

Booth algorithm uses a small number of additions and shift operations to do the work of multiplication.

It is a powerful algorithm for signed-number multiplication which treats both:

Positive numbers

Negative numbers

Booth algorithm is a method that will reduce the number of multiplicand multiples.

BOOTH MULTIPLIER

Uniformly

Registers used by Booth’s algorithm.

BOOTH MULTIPLIER

BLOCK DIAGRAM

Booth’s Multiplier

Input a

Input b

Output c

STEP 1:

• Decide which operand will be the multiplier and which will be the multiplicand.

• Initialize the remaining registers to ‘0’.

• Initialize Count Register with the number of Multiplicand Bits.

THE ALGORITHM

For Example:

Multiplicand = 7 0111 M

Multiplier = 3 0011 Q

Register ‘A’ = 0 0000 A

Register = 0 0000

Register Count = 4 0100 Count

START

A 0 ; Q -10MMultiplicandQ Multiplier

Countn

Q-1Q-1

STEP 1:

• Use the LSB (least significant bit) and the previous LSB to determine the arithmetic action.

• If it is the FIRST pass, use 0 as the previous LSB.

START

A 0 ; Q -10MMultiplicandQ Multiplier

Countn

Q 0 ,Q -

1

THE ALGORITHM

STEP 2:

• Possible arithmetic actions:• 00 no arithmetic operation

• 11 no arithmetic operation

• 01 add multiplicand to left half of product

• 10 subtract multiplicand from left half of product

THE ALGORITHM START

A 0 ; Q -10MMultiplicandQ Multiplier

Countn

Q 0 ,Q -

1

AA-M A A+M

=01

=11=00

=10

STEP 3:

• Perform an arithmetic right shift (ASR) on the entire product.

THE ALGORITHM START

A 0 ; Q -10MMultiplicandQ Multiplier

Countn

Q 0 ,Q -

1

AA-M A A+M

=01

=11=00

=10

Arithmetic Shift right

A, Q, Q-1

Count Count -1

START

A 0 ; Q -10MMultiplicandQ Multiplier

Countn

Q 0 ,Q -

1

AA-M A A+M

=01

=11=00

=10

Arithmetic Shift right

A, Q, Q-1

Count Count -1

THE ALGORITHM

Count=0?

ENDYesN0

STEP 4:

• When Count register is not ‘0’ then continue the multiplication.

• If Count register is ‘0’ then END the Algorithm.

• (7) 0111 M

• (3) 0011 Q

• (-7)1001 -M

• 0A

• 0

• Count=no. of bits4

EXAMPLE

Q-1

0 0 0 01 0 0 1

1 0 0 1

-MA

A

• ARITHEMATIC SHIFT RIGHT

EXAMPLE

1 0 0 1 0 0 1 1 0

1 1BIN

1 0 0 1 0 0 1

EXAMPLE

• ARITHEMATIC SHIFT RIGHT

1 1 0 0 1 0 0 1 1

1 1BIN

1 1 0 0 1 0 0

EXAMPLE0 1 0 10 1 1 1

0 0 1 0

MA

A• ADDING A+M

ARITHEMATIC SHIFT RIGHT

EXAMPLE

0 1 0 1 0 1 0 0 1

0 0BIN

0 1 0 1 0 1 0

EXAMPLEA Q Q-1 Action Count

0 0 0 0 0 0 1 1 0 Initial 4

1 0 0 1 0 0 1 1 0 AA-M1 1 0 0 1 0 0 1 1 Shift 3

1 1 1 0 0 1 0 0 1 Shift 2

0 1 0 1 0 1 0 0 1 AA+M0 0 1 0 1 0 1 0 0 Shift 1

0 0 0 1 0 1 0 1 0 Shift 0

Step

1

22

3

44

5

• ARITHEMATIC SHIFT RIGHT

• FINAL PRODUCT 7*3 21

COUNT = ‘0’

0 1 0 1 0 1 0 0 0

0 0BIN

0 0 1 0 1 0 1

VHDL HIERARCHY

VHDL PACKAGES

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee.std_logic_signed.all;

Use ieee.std_logic_unsigned.all;

entity my_ckt is port (

A: in bit;B: in bit;S: in bit;X: out bit;Y: out bit

);end my_ckt;

my_ckt

A

B

S

X

Y

Name of the circuit User-defined Filename same as circuit

name Example.

Circuit name: my_ckt Filename: my_ckt.vhd

Port names or

Signal names

Name of the circuit User-defined Filename same as circuit

name recommended Example:

Circuit name: my_ckt Filename: my_ckt.vhd

Datatypes: In-built User-defined

Direction of port3 main types: in: Input out: Output inout: Bidirectional

Note the absence of semicolon “;” at the end of the last signal and the presence at the end of the closing bracket

VHDL ENTITY

VHDL ARCHITECTURE

Defines functionality of the chip

Example:

X <= A AND B;

Y <= C AND D;

E <= X OR Y;

ChipA

B

C

D

EX

Y

DIFFERENT TYPES OF MODELING

IN VHDL “Modeling” refers to the type of description styles i.e. code that can be written on the basis of logical structure, functionality, behavior of the design or it can be a combination of these three styles. Hence on the basis of this there are different type of modelling in VHDL.

MODELING STYLES

DATAFLOWMODELING

STRUCTURAL

MODELING

BEHAVIORALMODELING

MIXEDMODELING

DATAFLOW MODELING

A dataflow modeling specifies the functionality of the entity without explicitly specifying its structure.

This functionality shows the flow of information through the entity, which is expressed using concurrent signal assignment statements.

An architecture body can contain any number of concurrent signal assignment statements.

Conditional statement can also be used in dataflow modeling.

e.g. ‘WHEN’ conditional statement.

Dataflow modeling is used when the user knows the exact expressions for the desired outputs.

STRUCTURAL MODELING

• In structural style of modeling, the entity is described as a set of interconnected components.

• The component instantiation statement is the primary mechanism used for describing such a model of an entity.

• Implicit definition of I/O relationship is done through particular structure.

• There is no need of sequential or conditional statements in this type of modeling.

• A list of components and there connections in any language is used in this type of modeling which is also sometimes called net list.

• The behavior of the entity is not explicitly apparent from its model

Behavioral MODELLING

The behavioral modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order.

This set of sequential statements , which are specified inside a process statement , do not explicitly specify the structure of the entity but merely its functionality.

Behavioral code cannot be written without a process statement. A process statement is a concurrent statement that can appear within an

architecture body. Architecture body can have any number of processes . A process statement also has declarative part (before the keyword begin)

and a statement part (between the keywords begin and end process ). The statements appearing within the process statement are sequential

statements and executed sequentially.

MIXED MODELING

It is possible to mix the three modeling styles that we have seen so far in a single architecture body.

Within an architecture body , we can use :-

component instantiation statements( that represent structure ), concurrent signal assignment (that represent dataflow) andprocess statements (that represent behavior).

ADVANTAGES OF Behavioral MODELING:

Code become easier for complex design.

Code can be written block wise..

Sequential or conditional statements can be used.

Less time consuming.

TEST BENCHES We have concentrated on VHDL for synthesis

Can also use VHDL as a test language

Very important to conduct comprehensive verification on your design.

To simulate your design you need to produce an additional

ENTITY and ARCHITECTURE design.

Usually referred to as a TEST BENCH

Not hardware, just additional VHDL!

TEST BENCHES• A model used to exercise and verify the correctness of a

hardware model

• Test Benches are used in only in Simulation, not for synthesizing.

• Has three main purposes

– to generate stimulus for simulation(Waveform).

– to apply this stimulus to the entity under test and to collect output responses

– to compare output responses with expected values

• Test Bench should be created by a different engineer than the one who created the synthesizable VHDL.

TEST BENCHES

TEST BENCHES A Test Bench consists of

– Entity

• has no ports (empty entity header)

– Architecture

• declares, instantiates for the model under test.

ADVANTAGES:

It prevents wastage of time in programming the same design again and again.

Most Designs are tested using test bench in industries.

CODING

VHDL code for BOOTHS ALGORITHMlibrary IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity Booth_Con_RCI is

Port ( X : in STD_LOGIC_VECTOR(3 DOWNTO 0);

Y : in STD_LOGIC_VECTOR(3 DOWNTO 0);

Z : out STD_LOGIC_VECTOR(7 DOWNTO 0) );

end Booth_Con_RCI;

architecture Behavioral of Booth_Con_RCI is

 

SIGNAL A:STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL S:STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL P:STD_LOGIC_VECTOR(8 DOWNTO 0);

 

 

SIGNAL P1,P1_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL P2,P2_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL P3,P3_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL P4,P4_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL P5,P5_SHIFT:STD_LOGIC_VECTOR(8 DOWNTO 0);

Signals can only be defined in this place before the begin keyword

begin

A(8 DOWNTO 5)<=X;

A(4 DOWNTO 0)<=(OTHERS=>'0');

 

S(8 DOWNTO 5)<=NOT X + "0001";

S(4 DOWNTO 0)<=(OTHERS=>'0');

 

P(8 DOWNTO 5)<=(OTHERS=>'0');

P(4 DOWNTO 1)<=Y;

P(0)<='0';

  

P1<=P WHEN (P(1 DOWNTO 0)="00" OR P(1 DOWNTO 0)="11")ELSE

P+A WHEN P(1 DOWNTO 0)="01"ELSE

P+S WHEN P(1 DOWNTO 0)="10";

  

P1_SHIFT(7 DOWNTO 0)<=P1(8 DOWNTO 1);

P1_SHIFT(8)<=P1(8);

0111 0000 0A

1001 0000 0S

0000 0011 0P

INPUT Y=3

INPUT X=7

2’s Compliment X=-7

0000 001 1 0P

1001 0011 0P

P+S

P1

1 0 0 1 0 0 1 1 0P1

P1_SHIFT 1 1BIN

P1<=P

1 0 0 1 0 0 1

P2<=P1_SHIFT WHEN (P1_SHIFT(1 DOWNTO 0)="00" OR P1_SHIFT(1 DOWNTO 0)="11")ELSE

P1_SHIFT+A WHEN P1_SHIFT(1 DOWNTO 0)="01"ELSE

P1_SHIFT+S WHEN P1_SHIFT(1 DOWNTO 0)="10";

 

P2_SHIFT(7 DOWNTO 0)<=P2(8 DOWNTO 1);

P2_SHIFT(8)<=P2(8);

 

P3<=P2_SHIFT WHEN (P2_SHIFT(1 DOWNTO 0)="00" OR P2_SHIFT(1 DOWNTO 0)="11")ELSE

P2_SHIFT+A WHEN P2_SHIFT(1 DOWNTO 0)="01"ELSE

P2_SHIFT+S WHEN P2_SHIFT(1 DOWNTO 0)="10";

 

P3_SHIFT(7 DOWNTO 0)<=P3(8 DOWNTO 1);

P3_SHIFT(8)<=P3(8);

 

1100 100 1 1P1_shift

P3<=P2_SHIFT

ASR

1110 010 0 1P2_shift

P+A0101 0100 1P2_shiftP3

1 1 0 0 1 0 0 1 1P2

P2_SHIFT 1 1BIN

1 1 0 0 1 0 00111 0000 0A

0 1 0 1 0 1 0 0 1P3

P3_SHIFT 0 0BIN

0 1 0 1 0 1 0

P2<=P1_SHIFT

P2

P4<=P3_SHIFT WHEN (P3_SHIFT(1 DOWNTO 0)="00" OR P3_SHIFT(1 DOWNTO 0)="11")ELSE

P3_SHIFT+A WHEN P3_SHIFT(1 DOWNTO 0)="01"ELSE

P3_SHIFT+S WHEN P3_SHIFT(1 DOWNTO 0)="10";

P4_SHIFT(7 DOWNTO 0)<=P4(8 DOWNTO 1);

P4_SHIFT(8)<=P4(8);

Z<=P4_SHIFT(8 DOWNTO 1);

 

end Behavioral;

0010 101 0 0P3_SHIFT

ASR

P4

P4<=P3_SHIFT

0 0 1 0 1 0 1 0 0P4

P4_SHIFT 0 0BIN

0 0 1 0 1 0 1

0001 0101 0P4_SHIFTZ

UCF DECELERATION FOR BOOTHS

RESULT

DESIGN SUMMARY

RTL SCHEMATIC

TOP LEVEL LAYOUT

TOP LEVEL LAYOUT(TECHNOLOGY SCHEMATIC)

LUT’S

ISIM Simulator

X=0111(7)Y=0011(3)Z=00010101(21)

TEST BENCH ISIM

VALIDINPUTS

VALID OUTPUTS

• Our project gives a clear concept of multipliers and their implementation.

• Booth Multipliers are implemented, the complete process of the implementation.

• As compared to Radix-2 Booth Multiplier, Radix-4 gives higher speed and Circuit Complexity is also less.

• Secondarily, this thesis has shown that algorithms based upon the Booth partial product method are distinctly superior in power and area when compared to non-Booth encoded method.

• Reducing the number of partial product and creating efficient ways of driving the long wires needed in controlling and providing multiples to the partial product generators are areas where further work may prove fruitful.