Semiconductor Nanowire Heteroepitaxy on Semiconductor Nanowire Heteroepitaxy on Arbitrary Substrates for Optoelectronic Devices Arbitrary Substrates for Optoelectronic Devices y py p

and Massively Parallel Interconnectsand Massively Parallel Interconnects

M. Saif Islam Logeeswaran VJ, LinjieZhou & S. J. Ben Yoo

University of California – Davis

Sonia Grego and Kristin Gilchrist RTI International

N. P. KobayashiUniversity of California Santa Cruz

1M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 1

S. Y. Wang and R. Stanley WilliamsHP Labs

Outline

• Semiconductor nanowires to overcome issues of heteroepitaxy I Pheteroepitaxy– Constraints of substrates– Enabling Devices for Si Photonics Si

InP

• Nanowires as Interconnects SiO2cladding

Aucatalyst Si

nanowirescladding

Poly-Si

2M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 2

One-D NanowiresWang et. al.Lieber et. al.

Fukui et. al.

Yang et. al.

2

Kamins et. al.Busbee et. al.Gundiah et. al.

2 m Islam et. al.

Samuelson et. al.

Cao et. al.

33Integrated Nanodevices and Systems Research, University of California Davis

Martin et. al. Zhou, Meyyappan, Kim, Ng, Samuelson …..Ag, Au, Zn, InP, ZnO, Si, Ge, Si-Ge, ZnS, GaN, InGaAs, In2O3

The Challenge: Interconnecting Nanowire Devices

Research based approach

• Alignment by fluid flow & electric field• Contact formed by e-beam lithography

One device at a time• One device at a time• Helps characterize & explore novel nanostructure

device applications

Mayer, Penn State

pp

410/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 4

Lieber et. al., Harvard Heath et. al., UCLA/CaltechLieber et. al. Science 2001 26, 291, 630-633

Manipulation of NWs

510/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 5

Lieber et. al., Harvard

Growth Direction and “Epitaxy”

500 nm

(111)-4 substrate

[111]

Si(111)

[111]

T I K i t l

Borgstrom et. al., 2007

610/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 6

Good electrical and mechanical connection to the substrateT I Kamins et. al.

Simultaneous Growth of Nanowires and Connecting Electrodes

Metal on Si surfaceEvaporation at 45o angleEvaporation at 45o angle

Si SiO2[111]

1. Metal deposition, metal-silicide formation

SiO2Si

silicide formation

2. Growth of Nanowire 3. Nanowire Bridge

710/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 7

Saif Islam et. al., Nanotechnology 15 (2004) L5–L8

Connecting Nanostructures:Bridging Nanowires

Form trench anddeposit catalyst

M Saif Islam S Sharma T I Kamins and R Stanley

2 µm

810/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 8

M. Saif Islam, S. Sharma, T. I. Kamins, and R. StanleyWilliams, Nanotechnology 15, L5-L8 (May 2004)

Connecting Nanostructures:Bridging Nanowires

Form trench anddeposit catalyst

Nanowire grows perpendicularto (111)-oriented sidewall

2 µm

M Saif Islam S Sharma T I Kamins and R Stanley

2 µmµ

910/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 9

M. Saif Islam, S. Sharma, T. I. Kamins, and R. StanleyWilliams, Nanotechnology 15, L5-L8 (May 2004)

Connecting Nanostructures:Bridging Nanowires

Form trench anddeposit catalyst

Nanowire grows perpendicularto (111)-oriented sidewall

Nanowire connectsto opposite sidewall

2 µm

M Saif Islam S Sharma T I Kamins and R Stanley 2 µm

2 µmµ

1010/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 10

M. Saif Islam, S. Sharma, T. I. Kamins, and R. StanleyWilliams, Nanotechnology 15, L5-L8 (May 2004)

2 µm

Easier Interfacing, Linear and OhmicSingle Nano-bridge Current vs number of Nano-bridgesSingle Nano-bridge Current vs number of Nano-bridgesg g Current vs number of Nano bridges

0

1

2

3

t (A

)0

100

200

300

3 NWs

12 NWs

20 NWs

t (A

)

g g Current vs number of Nano bridges

0

1

2

3

t (A

)0

100

200

300

3 NWs

12 NWs

20 NWs

t (A

)

-5 -4 -3 -2 -1 0 1 2 3 4 5

-3

-2

-1C

urre

nt

V lt (V)-5 -4 -3 -2 -1 0 1 2 3 4 5

-300

-200

-100

Cur

rent

V lt (V)-5 -4 -3 -2 -1 0 1 2 3 4 5

-3

-2

-1C

urre

nt

V lt (V)-5 -4 -3 -2 -1 0 1 2 3 4 5

-300

-200

-100

Cur

rent

V lt (V)Voltage (V) Voltage (V)Voltage (V) Voltage (V)

1110/5/2009 M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 11

Bridging Si Nanowires

3.E-04

3.E-04

2.E-04

2.E-04

ent (

I) •Average current density at failure 3.8106 A/cm2

5E 05

1.E-04Cur

re •Suspended bridges help in faster thermal dissipation

0.E+00

5.E-05

0 5 10 15

Bias (V)Nano-lollipops

Bias (V)

2µm

12M. Saif Islam Integrated Nanodevices and Systems Research, University of California Davis 12

Length vs Resistance

Si electrode

Si nanowireSi-Si contactat the interface

2Rcontact2µm

Nano Letters, vol. 7, pp. 1536-1541, 2007

electrode

1310/5/2009 Saif Islam 13Integrated Nanodevices and Systems Research, University of California Davis

RNW Rcontact

nanowire

contact

nanowire

Noise in Si Nanowires

•Carrier mobility fluctuation

Noise measurement shows

1 E 10

Carrier mobility fluctuation

•Carrier trapping–detrapping etc.

•Yield information about manufacturing & i ki f d i

A is relative amplitude of 1/f noise and R is the resistance

1.E-11

1.E-10 process & inner workings of a device.

•Low voltage operation requires low noise as the signal to noise ratio is

iti l

Nanotube Hooge parameter 10-3

1.E-13

1.E-12

A/R

Si Nanowire

Carbon NanotubeSi nano-bridge

critical.

> Two orders of it d l i

1.E-15

1.E-14 magnitude lower noise than CNT

Nano-bridge

1410/5/2009 Saif Islam 14Integrated Nanodevices and Systems Research, University of California Davis

1.E-16

IEEE Trans. Nanotechnology, 5, No. 5, p523 2006ZnO, InP etc. on Si are likely have higher

noise due to interface resistance

Heteroepitaxial Growth of IIIHeteroepitaxial Growth of III--V V Nanowires on Silicon surfacesNanowires on Silicon surfaces

Agilent TechnologiesMolecular Technology Laboratory15

Issues with planar, epitaxial growth of III-V on Si

• Large lattice mismatch (~8.06%) causing high-density of misfit dislocations

~nm

Phigh density of misfit dislocations• Large difference in thermal expansion

coefficients leading to stress• Difference in crystal structures (polar vs.

InP

~µmy (p

non-polar) leading to antiphase domains and boundaries

III V

Si (111) substrate

Si substrate

III-VOPPORTUNITIES

Si Photonics (Lasers, LED, PD, displays

Si

InP

( , , , p yetc.)

Ultra-fast III-V devices integrated with Si CMOS (HEMTs, FETs, mixers etc >100GHz

Agilent TechnologiesMolecular Technology LaboratoryIntegrated Nanodevices and Systems Research, UC Davis

Si(

speed)

16

Dr. Mario Paniccia, Intel Corporation

1710/5/2009 Saif Islam 1717

GaAs & InP nanowires grown on Silicon-(111)

(A) GaAs and and (B) InP nanowires

Agilent TechnologiesMolecular Technology LaboratoryIntegrated Nanodevices and Systems Research, UC Davis

Samuelson et. al. NANO LETTERS 2004 Vol. 4, No. 10 p1987

18

SEM images of vertically aligned InP nanowires grown on Si (111)

1 µm

6 µmYoo et al

~30-50°

Yoo et al.

Si (111)

[111]

11>

0.338 nmSi (111)Yi, Girolami, Amano, Sharma, Kamins, Kimukin, Islam, IEEE Nano 2005 <1

Non-epitaxial nanowires are entangled despite

Agilent TechnologiesMolecular Technology LaboratoryIntegrated Nanodevices and Systems Research, UC Davis

perfect crystal quality & uniform diameter

19

InP Nano-Bridges Between Si Electrodes

Goals:•Si Photonics (Laser, LED, PD, displays etc)•Ultra fast III V devices integrated with Si CMOS•Ultra-fast III-V devices integrated with Si CMOS (HEMTs, FETs, mixers etc >100GHz speed)

Si SiInP

IBridge + light

InPSi Si 0

1

IBridge ( li ht)

g

(A x

10-6

)InPSi Si

SiO2 -1

(no light)C

urre

nt

Si

SiInP

Challenges::

SiYi, Girolami, Amano, Sharma, Kamins,

-10 -5 0 5 10

Voltage (V)

Si

Agilent TechnologiesMolecular Technology LaboratoryIntegrated Nanodevices and Systems Research, UC Davis

g•Interface barrier due to bandgap and workfunction mismatch•Growth of ternary and quaternary •Orientation and position of III-V on Si

Kimukin, Islam, APL, 89, 133121, 2006.

20

Growth of IIIGrowth of III--V Nanowires on V Nanowires on Amorphous SurfacesAmorphous Surfacespp

21

Ultra-fast NW photoconductor on Quartz

Active device

Coplanar waveguide

SiOSiO2

Ti/Pt 200µmActive device

Active device

Coplanar waveguide

SiOSiO2

Ti/Pt 200µmActive device

i HG

SG

O2SiO2

Ti/PtTi/Pt

Coplanar waveguide

O2

i HG

SG

O2SiO2

Ti/PtTi/Pt

Coplanar waveguide

O2

baµc-Si:HIntersecting

InP Nanowires

200nm

SiO

c1µm

baµc-Si:HIntersecting

InP Nanowires

200nm

SiO

c1µm

µc-Si:H

Intersecting Nanowires

1Intersecting

InP Nanowires

µc-Si:H

Intersecting Nanowires

1Intersecting

InP Nanowires

5µm ed

Nanowires

f

2 3

35µm ed

Nanowires

f

2 3

3

Integrated Nanodevices and Systems Research, UC Davis

Applied Phys. Lett. 91 113116 (2007).

22

Ultra-fast NW photoconductor on Quartz

Active device

Coplanar waveguide

SiO2

Ti/PtActive device

Coplanar waveguide

SiO2

Ti/PtActive device

Coplanar waveguide

SiO2

Ti/PtActive device

Coplanar waveguide

SiO2

Ti/PtApplied Phys. A, 2008

GS

G

GS

G

GS

G

GS

G

•The measured FWHM from the oscilloscope was 18 psThe measured FWHM from the oscilloscope was 18 ps•11.2 ps FWHM response for the 40-GHz oscilloscope and the laser pulse width of 1 ps•The device temporal response is estimated to be 14 ps at 780nm

222

Integrated Nanodevices and Systems Research, UC Davis

opticalscopeactualmeas K. Rush, S. Draving, and J. Kerley, IEEE Spectrum 27, 38 (1990).

23

WaveguideWaveguide--Integrated Nanowire Photoconductors Integrated Nanowire Photoconductors on a Nonon a Non--Single Crystal SurfaceSingle Crystal Surfaceg yg y

SiO2cladding

Aucatalyst Si

nanowires

Vertical walls provide

Mechanical support for bridging NW

Poly-Si

Electrical contact through Poly-Si film

Optical pathways

Poly-Si film performs as:

Seed layer for crystalline growthSeed layer for crystalline growth

Electrical contact

24

Growth on angle-deposited Au catalystWaveguide-integrated devices

WG core

SiO2

Poly-Si

WG core

Si (100)

(10 um)Different Au

Cross-section of thermal oxide trench device

patterns:A trade-off between growth requirement andrequirement and electrical signal background.

25

Photoresponse of edge-illuminated nanowires (I)

400600

dark

1.4

ratio

V=3V=-1V=-3

-2000

200

curre

nt (p

A) 2mW

1.0

1.2

0 1 2 3Input Laser power (mW)

On/

Off

-600-400

-5 -4 -3 -2 -1 0 1 2 3 4 5V bias (V)

p p ( )

On/Off Ratio ~ 1.35 Sample had poor optical

transmission due to scattering

V bias (V)

V

transmission due to scattering

26

V

Opportunities for Novel Devices

I

Bridged

Mirror at 45o II

Bridged

Mirror at 45o I

Bridged

Mirror at 45o II

Bridged

Mirror at 45o

QD

High Qit

DBR

CMOSBridged

Nanowire

QD

High Qit

DBR

CMOSBridged

Nanowire

QD

High Qit

DBR

CMOSBridged

Nanowire

QD

High Qit

DBR

CMOSBridged

Nanowire

DBR

cavity

DBR

cavity

DBR

cavity

DBR

cavity

QDElectrode NanowiresQDElectrode NanowiresQDElectrode NanowiresQDElectrode Nanowires

27

Mirrors

Lateral QD laser on Si and III-V wafer

OutputMirrors

Lateral QD laser on Si and III-V wafer

OutputMirrors

Lateral QD laser on Si and III-V wafer

Mirrors

Lateral QD laser on Si and III-V wafer

Output

27

Nanowires for MassivelyNanowires for MassivelyNanowires for Massively Nanowires for Massively Parallel InterconnectsParallel InterconnectsParallel InterconnectsParallel Interconnects

10/5/2009 Saif Islam Integrated Nanodevices and Systems Research, UC Davis 28

SiliconSilicon

Nanowire

Silicon

Nanowire

Silicon

(a-b) Schematics of vertically oriented nanowires grown and bridged between two

(a) (c)(b) Silicon(a) (c)(b) Silicon

g glateral surfaces. (c) Experimental demonstration with Si nanowires.

Si b t t

Integrated Nanodevices and Systems Research, UC Davis

Si substrate

29

Nanowires for Multi-Layer Chip Stackingg

Borgstrom et. al., 2007

10/5/2009 Saif Islam Integrated Nanodevices and Systems Research, UC Davis 30

Processed Chips Bonded Using Nanaowires

MemoryNanowires

Solder bumps

10/5/2009 Saif Islam Integrated Nanodevices and Systems Research, UC Davis

Logic

31

Vertical Interconnects in Vias

10/5/2009 Saif Islam Integrated Nanodevices and Systems Research, UC Davis

Paul C. McIntyre, Stanford UniversityIBM

32

Summary•Semiconductor nanowires can overcome issues of heteroepitaxy Enabling Devices for Si Photonicsp y g

•Nanowires can be used as short range electrical interconnects

Si electrode

Si Si contactSiO2

Aucatalyst Si

nanowires

Si SiInP

2µm

Si nanowireSi-Si contactat the interface

S O2cladding

Poly-Si

2µm

Thank You10/5/2009 Saif Islam Integrated Nanodevices and Systems Research, UC Davis 33

Thank You