Questions

Question 1

Animation: Johnson ring counter

This question consists of a series of images (one per page) that form an animation. Flip the pages withyour fingers to view this animation (or click on the ”next” button on your viewer) frame-by-frame.

The following animation shows a 4-bit Johnson ring counter circuit. Watch what happens as the clock

signal oscillates. Here are some things to look for:

• Note when the logic state at each flip-flop input gets sent to the Q output.

• Why do you think this is called a ”ring” counter circuit?

1

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0 0

1

1 0 0 0

2

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0 0

1

1 0 0 0

3

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0 0

1

1 0 0 0

4

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0 0

1

1 0 0 01 1

5

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0

1

1 0 01 1

6

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0

1

1 0 01 1

7

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0

1

1 0 01 1

8

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0

1

1 0 01 1

9

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0

1

1 0 01 1 1 1

10

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0

1

1 01 1 1 1

11

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C

Q

Q D

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Q

Q D

C

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Q D

C

Q

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0

1

1 01 1 1 1

12

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

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Q

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0

1

1 01 1 1 1

13

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0

1

1 01 1 1 1

14

D

C

Q

Q D

C

Q

Q D

C

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Q D

C

Q

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0

1

1 01 1 1 1 1 1

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D

C

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Q D

C

Q

Q D

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Q D

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Clk

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ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

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VDD

Gnd

Q2

Q3

0

1

1 1 1 1 1 1 1

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C

Q

Q D

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0

1

1 1 1 1 1 1 1

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D

C

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Q D

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Clk

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ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0

1

1 1 1 1 1 1 1

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Clk

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ClockVDD

Gnd

Q0

Q1

VDD

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VDD

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VDD

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VDD

Gnd

Q2

Q3

0

1

1 1 1 1 1 1 1

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C

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0

1

1 1 1 1 1 1 1 1

0

0

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Q D

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1 1 1

0

0

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Q D

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Clk

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ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1 1 1

0

0

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Clk

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ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1 1 1

0

0

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1 1 1

0

0

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C

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1 1 1

0

0 0 0

25

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C

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C

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1

0

0 0 0

26

D

C

Q

Q D

C

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Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1

0

0 0 0

27

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C

Q

Q D

C

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Q D

C

Q

Q D

C

Q

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1

0

0 0 0

28

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1

0

0 0 0

29

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1 1 1

0

0 0 0 0 0

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D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

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Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1

0

0 0 0 0 0

31

D

C

Q

Q D

C

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Q D

C

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Q D

C

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Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1

0

0 0 0 0 0

32

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1

0

0 0 0 0 0

33

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1

0

0 0 0 0 0

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D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1 1 1

0

0 0 0 0 0 0 0

35

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1

0

0 0 0 0 0 0 0

36

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1

0

0 0 0 0 0 0 0

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D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1

0

0 0 0 0 0 0 0

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D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1

0

0 0 0 0 0 0 0

39

D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

1

0

0 0 0 0 0 0 0 0

1

1

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D

C

Q

Q D

C

Q

Q D

C

Q

Q D

C

Q

Q

Clk

2 310

ClockVDD

Gnd

Q0

Q1

VDD

Gnd

VDD

Gnd

VDD

Gnd

VDD

Gnd

Q2

Q3

0 0 0 0 0 0 0

1

1

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41

Answers

Answer 1

Note that each rising edge of the clock pulse has its own frame in the animation sequence, to better

show you what happens at those crucial times.

42

Notes

Notes 1

The purpose of this animation is to let students study the behavior of this counter circuit and reach

their own conclusions. Similar to experimentation in the lab, except that here all the data collection is done

visually rather than through the use of test equipment, and the students are able to ”see” things that are

invisible in real life.

In this animation, I show each rising edge of the clock signal in its own frame, whereas the falling edge

of the clock shares a frame with the first half of the ”low” state. I do this because these are positive edge-

triggered flip-flops, and so the rising edge of the clock pulse is most important. I could have slowed things

down on the falling edge of the clock as well, but since there is little ”action” happening then, I decided to

save a frame and make it a shorter animation.

43