Processor Pipelines and Their Properties for Static

WCET Analysis

Jakob Engblom and Bengt Jonsson

Presented by Kiran Seth

Goals of paper

• Define mathematical model of pipeline behavior, to study Long Timing Effects (LTE).

• Examples of LTE.

• Conditions for LTE to occur.

Timing Model

• Program is set of Nodes connected by Edges.

• A Node can be one or more instructions.

• Hardware is deterministic (so same sequence of instructions gives same execution time).

• Multiple nodes are used to model variability.

• Negative timing effects – potential savings in execution time. Ignoring means WCET less tight.

• Positive timing effects – add to the execution time. Ignoring means underestimating WCET. BAD NEWS!!!

• Long timing effects (LTE) – When effects of instruction can be seen further into the pipeline. Positive LTE must be accounted for.

• Paper concentrates on explaining cause and effect of LTE. Many theorems to the effect.

• A pipeline model is also given to explain and create better examples of the LTE.

Pipeline Model

• Pipeline model captures timing behavior by temporal constraints. Each instruction Ii is seen as a sequence r1

i…rni of resource

requirements.

• r ji time instruction i wants in stage j.

• p ji is time when instruction i enters stage j.

Pipeline Model Constraints

• For sequence of m instructions in a n-stage pipeline - (1<= i

<=m, 1<=j <=n) • Instruction cannot enter next stage before current stage is

done.

• Next instruction cannot enter pipeline till previous instruction is done.

• Other Constraints-

1j j jii ip p r

11

j ji ip p

1 11

ji ip p 1j l

i kp p

Graphical Representation of Pipeline Model

• Use a weighted directed acyclic graph.

• Execution time T(I1..Im) is maximal distance from p11

to some end point in constraint system.

Theorem 1

• For a single in-order pipeline, a timing effect I1...Im<>0 can occur for a sequence of instructions I1...Im, m >= 3 only if I1 stalls the execution of some instruction in I2...Im.

• Means that if first instruction stalls one of its successors OR first instruction reaches past I2...Im-1, we will have a LTE over I1...Im.

Theorem 2

• For a sequence of instructions I1 . . . Im,m>=2, executing on a pipeline with the CCP property, I1...Im <= 0.

• Crossing Critical Path (CCP) implies that pipeline is without positive LTE.

Theorem 3

• A single in-order pipeline has the CCP property if each constraint introduced by branches and data dependences either -

a) occurs between adjacent instructions, or

b)is subsumed by the basic constraints.

• This theorem characterizes the pipelines with CCP properties.

Theorem 4-5

• For in-order pipelines, no timing anomalies can appear when we increase the execution time of an instruction.

• For in-order pipelines, no timing anomalies can appear when we decrease the execution time of an instruction.

More about LTE’s

• Parallel pipelines cause positive LTE.

• In general it is not possible to provide a bound on the length of sequences of instructions that can exhibit LTE.

Results - Safety of WCET Analysis

• Safely ignore negative LTEs.

• Make sure no positive LTEs are missed.

• Even simple pipelines can exhibit LTEs across arbitrary numbers of instructions.

• In-order single-issue processors don’t have any timing anamolies.