Presentazione attività FIRB-Renga

G. Tassielli

Consiglio di sezione di Lecce

11/7/2014

2

Drift Chambers Principles

3

Project goals

4

Project goals

5

MEG a possible application

6

Challenges

7

Schedule and Milestones

8

Schedule and Milestones

9

Members

10

Staff (2015)

Renga 100%

Voena 20%

Grancagnolo 20%

Tassielli 100%

Panareo 30%

11

Power

Switch

I-ch. Sig.

Input

Q-ch. Sig.

Input

Ext

Clock

Input Ext. Trigger

Input

DCLK_RST

LMX2541

Int Clock

LEDs

ADC08D1520

USB

Controller

USB Connector

ADC Control

Jumpers

Auxiliary Data Port (FMC connector) on bottom

ADC08D1520 Reference

Board

FPGA

(Xilinx)

Po

we

r

sect

ion

Power

Jack

12

cutting 99.7%

of noise

Peak found

condition

Set the threshold

d

nn

n

AAAD 3

2

11

22222

2

3

4

1

4

1

11

nnn

AAAd

Real Time Alogrithm (VHDL code)

Ampl [V]

sample

Dig Ampl

sample

Cluster Timing Algorithm

description

Behavioural Simulation on experimentally acquired signals

Behavioural

Simulations Simulations

don’t take into account

actual components

neither the intrinsic delay

introduced by FPGA

switching

13

Prototypes

14

Conclusions

15

Conclusions